if_pcn.c revision 110572
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 110572 2003-02-08 21:06:03Z mdodd $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85 86#include <pci/pcireg.h> 87#include <pci/pcivar.h> 88 89#define PCN_USEIOSPACE 90 91#include <pci/if_pcnreg.h> 92 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98#ifndef lint 99static const char rcsid[] = 100 "$FreeBSD: head/sys/pci/if_pcn.c 110572 2003-02-08 21:06:03Z mdodd $"; 101#endif 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct pcn_type pcn_devs[] = { 107 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 108 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 109 { 0, 0, NULL } 110}; 111 112static u_int32_t pcn_csr_read (struct pcn_softc *, int); 113static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 114static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 115static void pcn_csr_write (struct pcn_softc *, int, int); 116static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 117static void pcn_bcr_write (struct pcn_softc *, int, int); 118 119static int pcn_probe (device_t); 120static int pcn_attach (device_t); 121static int pcn_detach (device_t); 122 123static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 124static int pcn_encap (struct pcn_softc *, 125 struct mbuf *, u_int32_t *); 126static void pcn_rxeof (struct pcn_softc *); 127static void pcn_txeof (struct pcn_softc *); 128static void pcn_intr (void *); 129static void pcn_tick (void *); 130static void pcn_start (struct ifnet *); 131static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 132static void pcn_init (void *); 133static void pcn_stop (struct pcn_softc *); 134static void pcn_watchdog (struct ifnet *); 135static void pcn_shutdown (device_t); 136static int pcn_ifmedia_upd (struct ifnet *); 137static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 138 139static int pcn_miibus_readreg (device_t, int, int); 140static int pcn_miibus_writereg (device_t, int, int, int); 141static void pcn_miibus_statchg (device_t); 142 143static void pcn_setfilt (struct ifnet *); 144static void pcn_setmulti (struct pcn_softc *); 145static u_int32_t pcn_crc (caddr_t); 146static void pcn_reset (struct pcn_softc *); 147static int pcn_list_rx_init (struct pcn_softc *); 148static int pcn_list_tx_init (struct pcn_softc *); 149 150#ifdef PCN_USEIOSPACE 151#define PCN_RES SYS_RES_IOPORT 152#define PCN_RID PCN_PCI_LOIO 153#else 154#define PCN_RES SYS_RES_MEMORY 155#define PCN_RID PCN_PCI_LOMEM 156#endif 157 158static device_method_t pcn_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, pcn_probe), 161 DEVMETHOD(device_attach, pcn_attach), 162 DEVMETHOD(device_detach, pcn_detach), 163 DEVMETHOD(device_shutdown, pcn_shutdown), 164 165 /* bus interface */ 166 DEVMETHOD(bus_print_child, bus_generic_print_child), 167 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 168 169 /* MII interface */ 170 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 171 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 172 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 173 174 { 0, 0 } 175}; 176 177static driver_t pcn_driver = { 178 "pcn", 179 pcn_methods, 180 sizeof(struct pcn_softc) 181}; 182 183static devclass_t pcn_devclass; 184 185DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 186DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 187 188#define PCN_CSR_SETBIT(sc, reg, x) \ 189 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 190 191#define PCN_CSR_CLRBIT(sc, reg, x) \ 192 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 193 194#define PCN_BCR_SETBIT(sc, reg, x) \ 195 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 196 197#define PCN_BCR_CLRBIT(sc, reg, x) \ 198 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 199 200static u_int32_t 201pcn_csr_read(sc, reg) 202 struct pcn_softc *sc; 203 int reg; 204{ 205 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 206 return(CSR_READ_4(sc, PCN_IO32_RDP)); 207} 208 209static u_int16_t 210pcn_csr_read16(sc, reg) 211 struct pcn_softc *sc; 212 int reg; 213{ 214 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 215 return(CSR_READ_2(sc, PCN_IO16_RDP)); 216} 217 218static void 219pcn_csr_write(sc, reg, val) 220 struct pcn_softc *sc; 221 int reg; 222{ 223 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 224 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 225 return; 226} 227 228static u_int32_t 229pcn_bcr_read(sc, reg) 230 struct pcn_softc *sc; 231 int reg; 232{ 233 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 234 return(CSR_READ_4(sc, PCN_IO32_BDP)); 235} 236 237static u_int16_t 238pcn_bcr_read16(sc, reg) 239 struct pcn_softc *sc; 240 int reg; 241{ 242 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 243 return(CSR_READ_2(sc, PCN_IO16_BDP)); 244} 245 246static void 247pcn_bcr_write(sc, reg, val) 248 struct pcn_softc *sc; 249 int reg; 250{ 251 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 252 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 253 return; 254} 255 256static int 257pcn_miibus_readreg(dev, phy, reg) 258 device_t dev; 259 int phy, reg; 260{ 261 struct pcn_softc *sc; 262 int val; 263 264 sc = device_get_softc(dev); 265 266 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 267 return(0); 268 269 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 270 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 271 if (val == 0xFFFF) 272 return(0); 273 274 sc->pcn_phyaddr = phy; 275 276 return(val); 277} 278 279static int 280pcn_miibus_writereg(dev, phy, reg, data) 281 device_t dev; 282 int phy, reg, data; 283{ 284 struct pcn_softc *sc; 285 286 sc = device_get_softc(dev); 287 288 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 289 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 290 291 return(0); 292} 293 294static void 295pcn_miibus_statchg(dev) 296 device_t dev; 297{ 298 struct pcn_softc *sc; 299 struct mii_data *mii; 300 301 sc = device_get_softc(dev); 302 mii = device_get_softc(sc->pcn_miibus); 303 304 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 305 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 306 } else { 307 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 308 } 309 310 return; 311} 312 313#define DC_POLY 0xEDB88320 314 315static u_int32_t 316pcn_crc(addr) 317 caddr_t addr; 318{ 319 u_int32_t idx, bit, data, crc; 320 321 /* Compute CRC for the address value. */ 322 crc = 0xFFFFFFFF; /* initial value */ 323 324 for (idx = 0; idx < 6; idx++) { 325 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 326 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 327 } 328 329 return ((crc >> 26) & 0x3F); 330} 331 332static void 333pcn_setmulti(sc) 334 struct pcn_softc *sc; 335{ 336 struct ifnet *ifp; 337 struct ifmultiaddr *ifma; 338 u_int32_t h, i; 339 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 340 341 ifp = &sc->arpcom.ac_if; 342 343 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 344 345 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 346 for (i = 0; i < 4; i++) 347 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 348 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 349 return; 350 } 351 352 /* first, zot all the existing hash bits */ 353 for (i = 0; i < 4; i++) 354 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 355 356 /* now program new ones */ 357 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 358 if (ifma->ifma_addr->sa_family != AF_LINK) 359 continue; 360 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 361 hashes[h >> 4] |= 1 << (h & 0xF); 362 } 363 364 for (i = 0; i < 4; i++) 365 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 366 367 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 368 369 return; 370} 371 372static void 373pcn_reset(sc) 374 struct pcn_softc *sc; 375{ 376 /* 377 * Issue a reset by reading from the RESET register. 378 * Note that we don't know if the chip is operating in 379 * 16-bit or 32-bit mode at this point, so we attempt 380 * to reset the chip both ways. If one fails, the other 381 * will succeed. 382 */ 383 CSR_READ_2(sc, PCN_IO16_RESET); 384 CSR_READ_4(sc, PCN_IO32_RESET); 385 386 /* Wait a little while for the chip to get its brains in order. */ 387 DELAY(1000); 388 389 /* Select 32-bit (DWIO) mode */ 390 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 391 392 /* Select software style 3. */ 393 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 394 395 return; 396} 397 398/* 399 * Probe for an AMD chip. Check the PCI vendor and device 400 * IDs against our list and return a device name if we find a match. 401 */ 402static int 403pcn_probe(dev) 404 device_t dev; 405{ 406 struct pcn_type *t; 407 struct pcn_softc *sc; 408 int rid; 409 u_int32_t chip_id; 410 411 t = pcn_devs; 412 sc = device_get_softc(dev); 413 414 while(t->pcn_name != NULL) { 415 if ((pci_get_vendor(dev) == t->pcn_vid) && 416 (pci_get_device(dev) == t->pcn_did)) { 417 /* 418 * Temporarily map the I/O space 419 * so we can read the chip ID register. 420 */ 421 rid = PCN_RID; 422 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 423 0, ~0, 1, RF_ACTIVE); 424 if (sc->pcn_res == NULL) { 425 device_printf(dev, 426 "couldn't map ports/memory\n"); 427 return(ENXIO); 428 } 429 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 430 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 431 mtx_init(&sc->pcn_mtx, 432 device_get_nameunit(dev), MTX_NETWORK_LOCK, 433 MTX_DEF); 434 PCN_LOCK(sc); 435 /* 436 * Note: we can *NOT* put the chip into 437 * 32-bit mode yet. The lnc driver will only 438 * work in 16-bit mode, and once the chip 439 * goes into 32-bit mode, the only way to 440 * get it out again is with a hardware reset. 441 * So if pcn_probe() is called before the 442 * lnc driver's probe routine, the chip will 443 * be locked into 32-bit operation and the lnc 444 * driver will be unable to attach to it. 445 * Note II: if the chip happens to already 446 * be in 32-bit mode, we still need to check 447 * the chip ID, but first we have to detect 448 * 32-bit mode using only 16-bit operations. 449 * The safest way to do this is to read the 450 * PCI subsystem ID from BCR23/24 and compare 451 * that with the value read from PCI config 452 * space. 453 */ 454 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 455 chip_id <<= 16; 456 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 457 /* 458 * Note III: the test for 0x10001000 is a hack to 459 * pacify VMware, who's pseudo-PCnet interface is 460 * broken. Reading the subsystem register from PCI 461 * config space yeilds 0x00000000 while reading the 462 * same value from I/O space yeilds 0x10001000. It's 463 * not supposed to be that way. 464 */ 465 if (chip_id == pci_read_config(dev, 466 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 467 /* We're in 16-bit mode. */ 468 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 469 chip_id <<= 16; 470 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 471 } else { 472 /* We're in 32-bit mode. */ 473 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 474 chip_id <<= 16; 475 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 476 } 477 bus_release_resource(dev, PCN_RES, 478 PCN_RID, sc->pcn_res); 479 PCN_UNLOCK(sc); 480 mtx_destroy(&sc->pcn_mtx); 481 chip_id >>= 12; 482 sc->pcn_type = chip_id & PART_MASK; 483 switch(sc->pcn_type) { 484 case Am79C971: 485 case Am79C972: 486 case Am79C973: 487 case Am79C975: 488 case Am79C976: 489 case Am79C978: 490 break; 491 default: 492 return(ENXIO); 493 break; 494 } 495 device_set_desc(dev, t->pcn_name); 496 return(0); 497 } 498 t++; 499 } 500 501 return(ENXIO); 502} 503 504/* 505 * Attach the interface. Allocate softc structures, do ifmedia 506 * setup and ethernet/BPF attach. 507 */ 508static int 509pcn_attach(dev) 510 device_t dev; 511{ 512 u_int32_t eaddr[2]; 513 u_int32_t command; 514 struct pcn_softc *sc; 515 struct ifnet *ifp; 516 int unit, error = 0, rid; 517 518 sc = device_get_softc(dev); 519 unit = device_get_unit(dev); 520 521 /* Initialize our mutex. */ 522 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 523 MTX_DEF | MTX_RECURSE); 524 PCN_LOCK(sc); 525 526 /* 527 * Handle power management nonsense. 528 */ 529 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 530 u_int32_t iobase, membase, irq; 531 532 /* Save important PCI config data. */ 533 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 534 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 535 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 536 537 /* Reset the power state. */ 538 printf("pcn%d: chip is in D%d power mode " 539 "-- setting to D0\n", unit, 540 pci_get_powerstate(dev)); 541 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 542 543 /* Restore PCI config data. */ 544 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 545 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 546 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 547 } 548 549 /* 550 * Map control/status registers. 551 */ 552 pci_enable_busmaster(dev); 553 pci_enable_io(dev, SYS_RES_IOPORT); 554 pci_enable_io(dev, SYS_RES_MEMORY); 555 command = pci_read_config(dev, PCIR_COMMAND, 4); 556 557#ifdef PCN_USEIOSPACE 558 if (!(command & PCIM_CMD_PORTEN)) { 559 printf("pcn%d: failed to enable I/O ports!\n", unit); 560 error = ENXIO;; 561 goto fail; 562 } 563#else 564 if (!(command & PCIM_CMD_MEMEN)) { 565 printf("pcn%d: failed to enable memory mapping!\n", unit); 566 error = ENXIO;; 567 goto fail; 568 } 569#endif 570 571 rid = PCN_RID; 572 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 573 0, ~0, 1, RF_ACTIVE); 574 575 if (sc->pcn_res == NULL) { 576 printf("pcn%d: couldn't map ports/memory\n", unit); 577 error = ENXIO; 578 goto fail; 579 } 580 581 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 582 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 583 584 /* Allocate interrupt */ 585 rid = 0; 586 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 587 RF_SHAREABLE | RF_ACTIVE); 588 589 if (sc->pcn_irq == NULL) { 590 printf("pcn%d: couldn't map interrupt\n", unit); 591 error = ENXIO; 592 goto fail; 593 } 594 595 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 596 pcn_intr, sc, &sc->pcn_intrhand); 597 598 if (error) { 599 printf("pcn%d: couldn't set up irq\n", unit); 600 goto fail; 601 } 602 603 /* Reset the adapter. */ 604 pcn_reset(sc); 605 606 /* 607 * Get station address from the EEPROM. 608 */ 609 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 610 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 611 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 612 613 /* 614 * An AMD chip was detected. Inform the world. 615 */ 616 printf("pcn%d: Ethernet address: %6D\n", unit, 617 sc->arpcom.ac_enaddr, ":"); 618 619 sc->pcn_unit = unit; 620 callout_handle_init(&sc->pcn_stat_ch); 621 622 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 623 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 624 625 if (sc->pcn_ldata == NULL) { 626 printf("pcn%d: no memory for list buffers!\n", unit); 627 error = ENXIO; 628 goto fail; 629 } 630 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 631 632 ifp = &sc->arpcom.ac_if; 633 ifp->if_softc = sc; 634 ifp->if_unit = unit; 635 ifp->if_name = "pcn"; 636 ifp->if_mtu = ETHERMTU; 637 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 638 ifp->if_ioctl = pcn_ioctl; 639 ifp->if_output = ether_output; 640 ifp->if_start = pcn_start; 641 ifp->if_watchdog = pcn_watchdog; 642 ifp->if_init = pcn_init; 643 ifp->if_baudrate = 10000000; 644 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 645 646 /* 647 * Do MII setup. 648 */ 649 if (mii_phy_probe(dev, &sc->pcn_miibus, 650 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 651 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 652 error = ENXIO; 653 goto fail; 654 } 655 656 /* 657 * Call MI attach routine. 658 */ 659 ether_ifattach(ifp, (u_int8_t *) eaddr); 660 PCN_UNLOCK(sc); 661 return(0); 662 663fail: 664 PCN_UNLOCK(sc); 665 666 if (sc->pcn_intrhand) 667 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 668 if (sc->pcn_irq) 669 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 670 if (sc->pcn_res) 671 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 672 673 if (mtx_initialized(&sc->pcn_mtx) != 0) 674 mtx_destroy(&sc->pcn_mtx); 675 676 return(error); 677} 678 679static int 680pcn_detach(dev) 681 device_t dev; 682{ 683 struct pcn_softc *sc; 684 struct ifnet *ifp; 685 686 sc = device_get_softc(dev); 687 ifp = &sc->arpcom.ac_if; 688 689 PCN_LOCK(sc); 690 691 pcn_reset(sc); 692 pcn_stop(sc); 693 ether_ifdetach(ifp); 694 695 if (sc->pcn_miibus != NULL) { 696 bus_generic_detach(dev); 697 device_delete_child(dev, sc->pcn_miibus); 698 } 699 700 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 701 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 702 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 703 704 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 705 PCN_UNLOCK(sc); 706 707 mtx_destroy(&sc->pcn_mtx); 708 709 return(0); 710} 711 712/* 713 * Initialize the transmit descriptors. 714 */ 715static int 716pcn_list_tx_init(sc) 717 struct pcn_softc *sc; 718{ 719 struct pcn_list_data *ld; 720 struct pcn_ring_data *cd; 721 int i; 722 723 cd = &sc->pcn_cdata; 724 ld = sc->pcn_ldata; 725 726 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 727 cd->pcn_tx_chain[i] = NULL; 728 ld->pcn_tx_list[i].pcn_tbaddr = 0; 729 ld->pcn_tx_list[i].pcn_txctl = 0; 730 ld->pcn_tx_list[i].pcn_txstat = 0; 731 } 732 733 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 734 735 return(0); 736} 737 738 739/* 740 * Initialize the RX descriptors and allocate mbufs for them. 741 */ 742static int 743pcn_list_rx_init(sc) 744 struct pcn_softc *sc; 745{ 746 struct pcn_list_data *ld; 747 struct pcn_ring_data *cd; 748 int i; 749 750 ld = sc->pcn_ldata; 751 cd = &sc->pcn_cdata; 752 753 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 754 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 755 return(ENOBUFS); 756 } 757 758 cd->pcn_rx_prod = 0; 759 760 return(0); 761} 762 763/* 764 * Initialize an RX descriptor and attach an MBUF cluster. 765 */ 766static int 767pcn_newbuf(sc, idx, m) 768 struct pcn_softc *sc; 769 int idx; 770 struct mbuf *m; 771{ 772 struct mbuf *m_new = NULL; 773 struct pcn_rx_desc *c; 774 775 c = &sc->pcn_ldata->pcn_rx_list[idx]; 776 777 if (m == NULL) { 778 MGETHDR(m_new, M_NOWAIT, MT_DATA); 779 if (m_new == NULL) 780 return(ENOBUFS); 781 782 MCLGET(m_new, M_NOWAIT); 783 if (!(m_new->m_flags & M_EXT)) { 784 m_freem(m_new); 785 return(ENOBUFS); 786 } 787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 788 } else { 789 m_new = m; 790 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 791 m_new->m_data = m_new->m_ext.ext_buf; 792 } 793 794 m_adj(m_new, ETHER_ALIGN); 795 796 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 797 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 798 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 799 c->pcn_bufsz |= PCN_RXLEN_MBO; 800 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 801 802 return(0); 803} 804 805/* 806 * A frame has been uploaded: pass the resulting mbuf chain up to 807 * the higher level protocols. 808 */ 809static void 810pcn_rxeof(sc) 811 struct pcn_softc *sc; 812{ 813 struct ether_header *eh; 814 struct mbuf *m; 815 struct ifnet *ifp; 816 struct pcn_rx_desc *cur_rx; 817 int i; 818 819 ifp = &sc->arpcom.ac_if; 820 i = sc->pcn_cdata.pcn_rx_prod; 821 822 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 823 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 824 m = sc->pcn_cdata.pcn_rx_chain[i]; 825 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 826 827 /* 828 * If an error occurs, update stats, clear the 829 * status word and leave the mbuf cluster in place: 830 * it should simply get re-used next time this descriptor 831 * comes up in the ring. 832 */ 833 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 834 ifp->if_ierrors++; 835 pcn_newbuf(sc, i, m); 836 PCN_INC(i, PCN_RX_LIST_CNT); 837 continue; 838 } 839 840 if (pcn_newbuf(sc, i, NULL)) { 841 /* Ran out of mbufs; recycle this one. */ 842 pcn_newbuf(sc, i, m); 843 ifp->if_ierrors++; 844 PCN_INC(i, PCN_RX_LIST_CNT); 845 continue; 846 } 847 848 PCN_INC(i, PCN_RX_LIST_CNT); 849 850 /* No errors; receive the packet. */ 851 ifp->if_ipackets++; 852 eh = mtod(m, struct ether_header *); 853 m->m_len = m->m_pkthdr.len = 854 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 855 m->m_pkthdr.rcvif = ifp; 856 857 (*ifp->if_input)(ifp, m); 858 } 859 860 sc->pcn_cdata.pcn_rx_prod = i; 861 862 return; 863} 864 865/* 866 * A frame was downloaded to the chip. It's safe for us to clean up 867 * the list buffers. 868 */ 869 870static void 871pcn_txeof(sc) 872 struct pcn_softc *sc; 873{ 874 struct pcn_tx_desc *cur_tx = NULL; 875 struct ifnet *ifp; 876 u_int32_t idx; 877 878 ifp = &sc->arpcom.ac_if; 879 880 /* 881 * Go through our tx list and free mbufs for those 882 * frames that have been transmitted. 883 */ 884 idx = sc->pcn_cdata.pcn_tx_cons; 885 while (idx != sc->pcn_cdata.pcn_tx_prod) { 886 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 887 888 if (!PCN_OWN_TXDESC(cur_tx)) 889 break; 890 891 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 892 sc->pcn_cdata.pcn_tx_cnt--; 893 PCN_INC(idx, PCN_TX_LIST_CNT); 894 continue; 895 } 896 897 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 898 ifp->if_oerrors++; 899 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 900 ifp->if_collisions++; 901 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 902 ifp->if_collisions++; 903 } 904 905 ifp->if_collisions += 906 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 907 908 ifp->if_opackets++; 909 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 910 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 911 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 912 } 913 914 sc->pcn_cdata.pcn_tx_cnt--; 915 PCN_INC(idx, PCN_TX_LIST_CNT); 916 } 917 918 if (idx != sc->pcn_cdata.pcn_tx_cons) { 919 /* Some buffers have been freed. */ 920 sc->pcn_cdata.pcn_tx_cons = idx; 921 ifp->if_flags &= ~IFF_OACTIVE; 922 } 923 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 924 925 return; 926} 927 928static void 929pcn_tick(xsc) 930 void *xsc; 931{ 932 struct pcn_softc *sc; 933 struct mii_data *mii; 934 struct ifnet *ifp; 935 936 sc = xsc; 937 ifp = &sc->arpcom.ac_if; 938 PCN_LOCK(sc); 939 940 mii = device_get_softc(sc->pcn_miibus); 941 mii_tick(mii); 942 943 /* link just died */ 944 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 945 sc->pcn_link = 0; 946 947 /* link just came up, restart */ 948 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 949 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 950 sc->pcn_link++; 951 if (ifp->if_snd.ifq_head != NULL) 952 pcn_start(ifp); 953 } 954 955 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 956 957 PCN_UNLOCK(sc); 958 959 return; 960} 961 962static void 963pcn_intr(arg) 964 void *arg; 965{ 966 struct pcn_softc *sc; 967 struct ifnet *ifp; 968 u_int32_t status; 969 970 sc = arg; 971 ifp = &sc->arpcom.ac_if; 972 973 /* Supress unwanted interrupts */ 974 if (!(ifp->if_flags & IFF_UP)) { 975 pcn_stop(sc); 976 return; 977 } 978 979 PCN_LOCK(sc); 980 981 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 982 983 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 984 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 985 986 if (status & PCN_CSR_RINT) 987 pcn_rxeof(sc); 988 989 if (status & PCN_CSR_TINT) 990 pcn_txeof(sc); 991 992 if (status & PCN_CSR_ERR) { 993 pcn_init(sc); 994 break; 995 } 996 } 997 998 if (ifp->if_snd.ifq_head != NULL) 999 pcn_start(ifp); 1000 1001 PCN_UNLOCK(sc); 1002 return; 1003} 1004 1005/* 1006 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1007 * pointers to the fragment pointers. 1008 */ 1009static int 1010pcn_encap(sc, m_head, txidx) 1011 struct pcn_softc *sc; 1012 struct mbuf *m_head; 1013 u_int32_t *txidx; 1014{ 1015 struct pcn_tx_desc *f = NULL; 1016 struct mbuf *m; 1017 int frag, cur, cnt = 0; 1018 1019 /* 1020 * Start packing the mbufs in this chain into 1021 * the fragment pointers. Stop when we run out 1022 * of fragments or hit the end of the mbuf chain. 1023 */ 1024 m = m_head; 1025 cur = frag = *txidx; 1026 1027 for (m = m_head; m != NULL; m = m->m_next) { 1028 if (m->m_len != 0) { 1029 if ((PCN_TX_LIST_CNT - 1030 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1031 return(ENOBUFS); 1032 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1033 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1034 f->pcn_txctl |= PCN_TXCTL_MBO; 1035 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1036 if (cnt == 0) 1037 f->pcn_txctl |= PCN_TXCTL_STP; 1038 else 1039 f->pcn_txctl |= PCN_TXCTL_OWN; 1040 cur = frag; 1041 PCN_INC(frag, PCN_TX_LIST_CNT); 1042 cnt++; 1043 } 1044 } 1045 1046 if (m != NULL) 1047 return(ENOBUFS); 1048 1049 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1050 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1051 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1052 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1053 sc->pcn_cdata.pcn_tx_cnt += cnt; 1054 *txidx = frag; 1055 1056 return(0); 1057} 1058 1059/* 1060 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1061 * to the mbuf data regions directly in the transmit lists. We also save a 1062 * copy of the pointers since the transmit list fragment pointers are 1063 * physical addresses. 1064 */ 1065static void 1066pcn_start(ifp) 1067 struct ifnet *ifp; 1068{ 1069 struct pcn_softc *sc; 1070 struct mbuf *m_head = NULL; 1071 u_int32_t idx; 1072 1073 sc = ifp->if_softc; 1074 1075 PCN_LOCK(sc); 1076 1077 if (!sc->pcn_link) { 1078 PCN_UNLOCK(sc); 1079 return; 1080 } 1081 1082 idx = sc->pcn_cdata.pcn_tx_prod; 1083 1084 if (ifp->if_flags & IFF_OACTIVE) { 1085 PCN_UNLOCK(sc); 1086 return; 1087 } 1088 1089 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1090 IF_DEQUEUE(&ifp->if_snd, m_head); 1091 if (m_head == NULL) 1092 break; 1093 1094 if (pcn_encap(sc, m_head, &idx)) { 1095 IF_PREPEND(&ifp->if_snd, m_head); 1096 ifp->if_flags |= IFF_OACTIVE; 1097 break; 1098 } 1099 1100 /* 1101 * If there's a BPF listener, bounce a copy of this frame 1102 * to him. 1103 */ 1104 BPF_MTAP(ifp, m_head); 1105 1106 } 1107 1108 /* Transmit */ 1109 sc->pcn_cdata.pcn_tx_prod = idx; 1110 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1111 1112 /* 1113 * Set a timeout in case the chip goes out to lunch. 1114 */ 1115 ifp->if_timer = 5; 1116 1117 PCN_UNLOCK(sc); 1118 1119 return; 1120} 1121 1122static void 1123pcn_setfilt(ifp) 1124 struct ifnet *ifp; 1125{ 1126 struct pcn_softc *sc; 1127 1128 sc = ifp->if_softc; 1129 1130 /* If we want promiscuous mode, set the allframes bit. */ 1131 if (ifp->if_flags & IFF_PROMISC) { 1132 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1133 } else { 1134 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1135 } 1136 1137 /* Set the capture broadcast bit to capture broadcast frames. */ 1138 if (ifp->if_flags & IFF_BROADCAST) { 1139 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1140 } else { 1141 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1142 } 1143 1144 return; 1145} 1146 1147static void 1148pcn_init(xsc) 1149 void *xsc; 1150{ 1151 struct pcn_softc *sc = xsc; 1152 struct ifnet *ifp = &sc->arpcom.ac_if; 1153 struct mii_data *mii = NULL; 1154 1155 PCN_LOCK(sc); 1156 1157 /* 1158 * Cancel pending I/O and free all RX/TX buffers. 1159 */ 1160 pcn_stop(sc); 1161 pcn_reset(sc); 1162 1163 mii = device_get_softc(sc->pcn_miibus); 1164 1165 /* Set MAC address */ 1166 pcn_csr_write(sc, PCN_CSR_PAR0, 1167 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1168 pcn_csr_write(sc, PCN_CSR_PAR1, 1169 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1170 pcn_csr_write(sc, PCN_CSR_PAR2, 1171 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1172 1173 /* Init circular RX list. */ 1174 if (pcn_list_rx_init(sc) == ENOBUFS) { 1175 printf("pcn%d: initialization failed: no " 1176 "memory for rx buffers\n", sc->pcn_unit); 1177 pcn_stop(sc); 1178 PCN_UNLOCK(sc); 1179 return; 1180 } 1181 1182 /* 1183 * Init tx descriptors. 1184 */ 1185 pcn_list_tx_init(sc); 1186 1187 /* Set up the mode register. */ 1188 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1189 1190 /* Set up RX filter. */ 1191 pcn_setfilt(ifp); 1192 1193 /* 1194 * Load the multicast filter. 1195 */ 1196 pcn_setmulti(sc); 1197 1198 /* 1199 * Load the addresses of the RX and TX lists. 1200 */ 1201 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1202 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1203 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1204 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1205 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1206 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1207 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1208 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1209 1210 /* Set the RX and TX ring sizes. */ 1211 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1212 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1213 1214 /* We're not using the initialization block. */ 1215 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1216 1217 /* Enable fast suspend mode. */ 1218 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1219 1220 /* 1221 * Enable burst read and write. Also set the no underflow 1222 * bit. This will avoid transmit underruns in certain 1223 * conditions while still providing decent performance. 1224 */ 1225 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1226 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1227 1228 /* Enable graceful recovery from underflow. */ 1229 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1230 1231 /* Enable auto-padding of short TX frames. */ 1232 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1233 1234 /* Disable MII autoneg (we handle this ourselves). */ 1235 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1236 1237 if (sc->pcn_type == Am79C978) 1238 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1239 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1240 1241 /* Enable interrupts and start the controller running. */ 1242 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1243 1244 mii_mediachg(mii); 1245 1246 ifp->if_flags |= IFF_RUNNING; 1247 ifp->if_flags &= ~IFF_OACTIVE; 1248 1249 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1250 PCN_UNLOCK(sc); 1251 1252 return; 1253} 1254 1255/* 1256 * Set media options. 1257 */ 1258static int 1259pcn_ifmedia_upd(ifp) 1260 struct ifnet *ifp; 1261{ 1262 struct pcn_softc *sc; 1263 struct mii_data *mii; 1264 1265 sc = ifp->if_softc; 1266 mii = device_get_softc(sc->pcn_miibus); 1267 1268 sc->pcn_link = 0; 1269 if (mii->mii_instance) { 1270 struct mii_softc *miisc; 1271 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1272 mii_phy_reset(miisc); 1273 } 1274 mii_mediachg(mii); 1275 1276 return(0); 1277} 1278 1279/* 1280 * Report current media status. 1281 */ 1282static void 1283pcn_ifmedia_sts(ifp, ifmr) 1284 struct ifnet *ifp; 1285 struct ifmediareq *ifmr; 1286{ 1287 struct pcn_softc *sc; 1288 struct mii_data *mii; 1289 1290 sc = ifp->if_softc; 1291 1292 mii = device_get_softc(sc->pcn_miibus); 1293 mii_pollstat(mii); 1294 ifmr->ifm_active = mii->mii_media_active; 1295 ifmr->ifm_status = mii->mii_media_status; 1296 1297 return; 1298} 1299 1300static int 1301pcn_ioctl(ifp, command, data) 1302 struct ifnet *ifp; 1303 u_long command; 1304 caddr_t data; 1305{ 1306 struct pcn_softc *sc = ifp->if_softc; 1307 struct ifreq *ifr = (struct ifreq *) data; 1308 struct mii_data *mii = NULL; 1309 int error = 0; 1310 1311 PCN_LOCK(sc); 1312 1313 switch(command) { 1314 case SIOCSIFFLAGS: 1315 if (ifp->if_flags & IFF_UP) { 1316 if (ifp->if_flags & IFF_RUNNING && 1317 ifp->if_flags & IFF_PROMISC && 1318 !(sc->pcn_if_flags & IFF_PROMISC)) { 1319 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1320 PCN_EXTCTL1_SPND); 1321 pcn_setfilt(ifp); 1322 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1323 PCN_EXTCTL1_SPND); 1324 pcn_csr_write(sc, PCN_CSR_CSR, 1325 PCN_CSR_INTEN|PCN_CSR_START); 1326 } else if (ifp->if_flags & IFF_RUNNING && 1327 !(ifp->if_flags & IFF_PROMISC) && 1328 sc->pcn_if_flags & IFF_PROMISC) { 1329 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1330 PCN_EXTCTL1_SPND); 1331 pcn_setfilt(ifp); 1332 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1333 PCN_EXTCTL1_SPND); 1334 pcn_csr_write(sc, PCN_CSR_CSR, 1335 PCN_CSR_INTEN|PCN_CSR_START); 1336 } else if (!(ifp->if_flags & IFF_RUNNING)) 1337 pcn_init(sc); 1338 } else { 1339 if (ifp->if_flags & IFF_RUNNING) 1340 pcn_stop(sc); 1341 } 1342 sc->pcn_if_flags = ifp->if_flags; 1343 error = 0; 1344 break; 1345 case SIOCADDMULTI: 1346 case SIOCDELMULTI: 1347 pcn_setmulti(sc); 1348 error = 0; 1349 break; 1350 case SIOCGIFMEDIA: 1351 case SIOCSIFMEDIA: 1352 mii = device_get_softc(sc->pcn_miibus); 1353 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1354 break; 1355 default: 1356 error = ether_ioctl(ifp, command, data); 1357 break; 1358 } 1359 1360 PCN_UNLOCK(sc); 1361 1362 return(error); 1363} 1364 1365static void 1366pcn_watchdog(ifp) 1367 struct ifnet *ifp; 1368{ 1369 struct pcn_softc *sc; 1370 1371 sc = ifp->if_softc; 1372 1373 PCN_LOCK(sc); 1374 1375 ifp->if_oerrors++; 1376 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1377 1378 pcn_stop(sc); 1379 pcn_reset(sc); 1380 pcn_init(sc); 1381 1382 if (ifp->if_snd.ifq_head != NULL) 1383 pcn_start(ifp); 1384 1385 PCN_UNLOCK(sc); 1386 1387 return; 1388} 1389 1390/* 1391 * Stop the adapter and free any mbufs allocated to the 1392 * RX and TX lists. 1393 */ 1394static void 1395pcn_stop(sc) 1396 struct pcn_softc *sc; 1397{ 1398 register int i; 1399 struct ifnet *ifp; 1400 1401 ifp = &sc->arpcom.ac_if; 1402 PCN_LOCK(sc); 1403 ifp->if_timer = 0; 1404 1405 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1406 1407 /* Turn off interrupts */ 1408 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1409 /* Stop adapter */ 1410 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1411 sc->pcn_link = 0; 1412 1413 /* 1414 * Free data in the RX lists. 1415 */ 1416 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1417 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1418 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1419 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1420 } 1421 } 1422 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1423 sizeof(sc->pcn_ldata->pcn_rx_list)); 1424 1425 /* 1426 * Free the TX list buffers. 1427 */ 1428 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1429 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1430 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1431 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1432 } 1433 } 1434 1435 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1436 sizeof(sc->pcn_ldata->pcn_tx_list)); 1437 1438 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1439 PCN_UNLOCK(sc); 1440 1441 return; 1442} 1443 1444/* 1445 * Stop all chip I/O so that the kernel's probe routines don't 1446 * get confused by errant DMAs when rebooting. 1447 */ 1448static void 1449pcn_shutdown(dev) 1450 device_t dev; 1451{ 1452 struct pcn_softc *sc; 1453 1454 sc = device_get_softc(dev); 1455 1456 PCN_LOCK(sc); 1457 pcn_reset(sc); 1458 pcn_stop(sc); 1459 PCN_UNLOCK(sc); 1460 1461 return; 1462} 1463