pci_pci.c revision 124641
1204431Sraj/*- 2204431Sraj * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3204431Sraj * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4204431Sraj * Copyright (c) 2000 BSDi 5204431Sraj * All rights reserved. 6204431Sraj * 7204431Sraj * Redistribution and use in source and binary forms, with or without 8204431Sraj * modification, are permitted provided that the following conditions 9204431Sraj * are met: 10204431Sraj * 1. Redistributions of source code must retain the above copyright 11204431Sraj * notice, this list of conditions and the following disclaimer. 12204431Sraj * 2. Redistributions in binary form must reproduce the above copyright 13204431Sraj * notice, this list of conditions and the following disclaimer in the 14204431Sraj * documentation and/or other materials provided with the distribution. 15204431Sraj * 3. The name of the author may not be used to endorse or promote products 16204431Sraj * derived from this software without specific prior written permission. 17204431Sraj * 18204431Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19204431Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20204431Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21204431Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22204431Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23204431Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24204431Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25204431Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26204431Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27204431Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28204431Sraj * SUCH DAMAGE. 29204431Sraj */ 30204431Sraj 31204431Sraj#include <sys/cdefs.h> 32204431Sraj__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 124641 2004-01-17 21:54:04Z imp $"); 33204431Sraj 34204431Sraj/* 35204431Sraj * PCI:PCI bridge support. 36204431Sraj */ 37204431Sraj 38204431Sraj#include <sys/param.h> 39204431Sraj#include <sys/systm.h> 40204431Sraj#include <sys/kernel.h> 41204431Sraj#include <sys/bus.h> 42204431Sraj#include <machine/bus.h> 43204431Sraj#include <sys/rman.h> 44204431Sraj#include <sys/sysctl.h> 45204431Sraj 46204431Sraj#include <machine/resource.h> 47204431Sraj 48204431Sraj#include <dev/pci/pcivar.h> 49204431Sraj#include <dev/pci/pcireg.h> 50204431Sraj#include <dev/pci/pcib_private.h> 51204431Sraj 52204431Sraj#include "pcib_if.h" 53204431Sraj 54204431Srajstatic int pcib_probe(device_t dev); 55204431Sraj 56204431Srajstatic device_method_t pcib_methods[] = { 57204431Sraj /* Device interface */ 58204431Sraj DEVMETHOD(device_probe, pcib_probe), 59204431Sraj DEVMETHOD(device_attach, pcib_attach), 60204431Sraj DEVMETHOD(device_shutdown, bus_generic_shutdown), 61204431Sraj DEVMETHOD(device_suspend, bus_generic_suspend), 62204431Sraj DEVMETHOD(device_resume, bus_generic_resume), 63204431Sraj 64204431Sraj /* Bus interface */ 65204431Sraj DEVMETHOD(bus_print_child, bus_generic_print_child), 66204431Sraj DEVMETHOD(bus_read_ivar, pcib_read_ivar), 67204431Sraj DEVMETHOD(bus_write_ivar, pcib_write_ivar), 68204431Sraj DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 69204431Sraj DEVMETHOD(bus_release_resource, bus_generic_release_resource), 70204431Sraj DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 71204431Sraj DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 72204431Sraj DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 73204433Sraj DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 74204431Sraj 75204431Sraj /* pcib interface */ 76204431Sraj DEVMETHOD(pcib_maxslots, pcib_maxslots), 77204431Sraj DEVMETHOD(pcib_read_config, pcib_read_config), 78204431Sraj DEVMETHOD(pcib_write_config, pcib_write_config), 79204431Sraj DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 80204431Sraj 81204431Sraj { 0, 0 } 82204431Sraj}; 83204431Sraj 84204431Srajstatic driver_t pcib_driver = { 85204433Sraj "pcib", 86204431Sraj pcib_methods, 87204431Sraj sizeof(struct pcib_softc), 88204431Sraj}; 89204431Sraj 90204431Srajdevclass_t pcib_devclass; 91204431Sraj 92204431SrajDRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 93204431Sraj 94204431Sraj/* 95204431Sraj * Generic device interface 96204431Sraj */ 97204431Srajstatic int 98204431Srajpcib_probe(device_t dev) 99204431Sraj{ 100204431Sraj if ((pci_get_class(dev) == PCIC_BRIDGE) && 101204431Sraj (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 102204431Sraj device_set_desc(dev, "PCI-PCI bridge"); 103204431Sraj return(-10000); 104204431Sraj } 105204431Sraj return(ENXIO); 106204431Sraj} 107204431Sraj 108204431Srajvoid 109204431Srajpcib_attach_common(device_t dev) 110204431Sraj{ 111204431Sraj struct pcib_softc *sc; 112204431Sraj uint8_t iolow; 113204431Sraj 114204431Sraj sc = device_get_softc(dev); 115204431Sraj sc->dev = dev; 116204431Sraj 117204431Sraj /* 118204431Sraj * Get current bridge configuration. 119204431Sraj */ 120204431Sraj sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 121204431Sraj sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 122204431Sraj sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 123204431Sraj sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 124204431Sraj sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 125204431Sraj sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 126204431Sraj 127204431Sraj /* 128204431Sraj * Determine current I/O decode. 129204431Sraj */ 130204431Sraj if (sc->command & PCIM_CMD_PORTEN) { 131204431Sraj iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 132204431Sraj if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 133204431Sraj sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 134204431Sraj pci_read_config(dev, PCIR_IOBASEL_1, 1)); 135204431Sraj } else { 136204431Sraj sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 137204431Sraj } 138204431Sraj 139204431Sraj iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 140204431Sraj if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 141204431Sraj sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 142204431Sraj pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 143204431Sraj } else { 144204431Sraj sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 145204431Sraj } 146204431Sraj } 147204431Sraj 148204431Sraj /* 149204431Sraj * Determine current memory decode. 150204431Sraj */ 151204431Sraj if (sc->command & PCIM_CMD_MEMEN) { 152204431Sraj sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 153204431Sraj sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 154204431Sraj sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 155204431Sraj pci_read_config(dev, PCIR_PMBASEL_1, 2)); 156204431Sraj sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 157204431Sraj pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 158204431Sraj } 159204431Sraj 160204431Sraj /* 161204431Sraj * Quirk handling. 162204431Sraj */ 163204431Sraj switch (pci_get_devid(dev)) { 164204431Sraj case 0x12258086: /* Intel 82454KX/GX (Orion) */ 165204431Sraj { 166204431Sraj uint8_t supbus; 167204431Sraj 168204431Sraj supbus = pci_read_config(dev, 0x41, 1); 169204431Sraj if (supbus != 0xff) { 170204431Sraj sc->secbus = supbus + 1; 171204431Sraj sc->subbus = supbus + 1; 172204431Sraj } 173204431Sraj break; 174204431Sraj } 175204431Sraj 176204431Sraj /* 177204431Sraj * The i82380FB mobile docking controller is a PCI-PCI bridge, 178204431Sraj * and it is a subtractive bridge. However, the ProgIf is wrong 179204431Sraj * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 180204431Sraj * happen. There's also a Toshiba bridge that behaves this 181204431Sraj * way. 182204431Sraj */ 183204431Sraj case 0x124b8086: /* Intel 82380FB Mobile */ 184204431Sraj case 0x060513d7: /* Toshiba ???? */ 185204431Sraj sc->flags |= PCIB_SUBTRACTIVE; 186204431Sraj break; 187204431Sraj } 188204431Sraj 189204431Sraj /* 190204431Sraj * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 191204431Sraj * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 192204431Sraj * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 193204431Sraj * This means they act as if they were subtractively decoding 194204431Sraj * bridges and pass all transactions. Mark them and real ProgIf 1 195204431Sraj * parts as subtractive. 196204431Sraj */ 197204431Sraj if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 198204431Sraj pci_read_config(dev, PCIR_PROGIF, 1) == 1) 199204431Sraj sc->flags |= PCIB_SUBTRACTIVE; 200204431Sraj 201204431Sraj if (bootverbose) { 202204431Sraj device_printf(dev, " secondary bus %d\n", sc->secbus); 203204431Sraj device_printf(dev, " subordinate bus %d\n", sc->subbus); 204204431Sraj device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 205204431Sraj device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 206204431Sraj device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 207204431Sraj if (sc->flags & PCIB_SUBTRACTIVE) 208204431Sraj device_printf(dev, " Subtractively decoded bridge.\n"); 209204431Sraj } 210204431Sraj 211204431Sraj /* 212204431Sraj * XXX If the secondary bus number is zero, we should assign a bus number 213204431Sraj * since the BIOS hasn't, then initialise the bridge. 214204431Sraj */ 215204431Sraj 216204431Sraj /* 217204431Sraj * XXX If the subordinate bus number is less than the secondary bus number, 218204431Sraj * we should pick a better value. One sensible alternative would be to 219204431Sraj * pick 255; the only tradeoff here is that configuration transactions 220204431Sraj * would be more widely routed than absolutely necessary. 221204431Sraj */ 222204431Sraj} 223204431Sraj 224204431Srajint 225204431Srajpcib_attach(device_t dev) 226204431Sraj{ 227204431Sraj struct pcib_softc *sc; 228204431Sraj device_t child; 229204431Sraj 230204431Sraj pcib_attach_common(dev); 231204431Sraj sc = device_get_softc(dev); 232204431Sraj if (sc->secbus != 0) { 233204431Sraj child = device_add_child(dev, "pci", sc->secbus); 234204431Sraj if (child != NULL) 235204431Sraj return(bus_generic_attach(dev)); 236204431Sraj } 237204431Sraj 238204431Sraj /* no secondary bus; we should have fixed this */ 239204431Sraj return(0); 240204433Sraj} 241204431Sraj 242204431Srajint 243204431Srajpcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 244204431Sraj{ 245204431Sraj struct pcib_softc *sc = device_get_softc(dev); 246204431Sraj 247204431Sraj switch (which) { 248204431Sraj case PCIB_IVAR_BUS: 249204433Sraj *result = sc->secbus; 250204433Sraj return(0); 251204431Sraj } 252204431Sraj return(ENOENT); 253204431Sraj} 254204431Sraj 255204431Srajint 256204431Srajpcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 257{ 258 struct pcib_softc *sc = device_get_softc(dev); 259 260 switch (which) { 261 case PCIB_IVAR_BUS: 262 sc->secbus = value; 263 break; 264 } 265 return(ENOENT); 266} 267 268/* 269 * Is the prefetch window open (eg, can we allocate memory in it?) 270 */ 271static int 272pcib_is_prefetch_open(struct pcib_softc *sc) 273{ 274 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 275} 276 277/* 278 * Is the nonprefetch window open (eg, can we allocate memory in it?) 279 */ 280static int 281pcib_is_nonprefetch_open(struct pcib_softc *sc) 282{ 283 return (sc->membase > 0 && sc->membase < sc->memlimit); 284} 285 286/* 287 * Is the io window open (eg, can we allocate ports in it?) 288 */ 289static int 290pcib_is_io_open(struct pcib_softc *sc) 291{ 292 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 293} 294 295/* 296 * We have to trap resource allocation requests and ensure that the bridge 297 * is set up to, or capable of handling them. 298 */ 299struct resource * 300pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 301 u_long start, u_long end, u_long count, u_int flags) 302{ 303 struct pcib_softc *sc = device_get_softc(dev); 304 int ok; 305 306 /* 307 * Fail the allocation for this range if it's not supported. 308 */ 309 switch (type) { 310 case SYS_RES_IOPORT: 311 ok = 0; 312 if (!pcib_is_io_open(sc)) 313 break; 314 ok = (start >= sc->iobase && end <= sc->iolimit); 315 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 316 if (!ok) { 317 if (start < sc->iobase) 318 start = sc->iobase; 319 if (end > sc->iolimit) 320 end = sc->iolimit; 321 } 322 } else { 323 ok = 1; 324#if 0 325 if (start < sc->iobase && end > sc->iolimit) { 326 start = sc->iobase; 327 end = sc->iolimit; 328 } 329#endif 330 } 331 if (end < start) { 332 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start); 333 start = 0; 334 end = 0; 335 ok = 0; 336 } 337 if (!ok) { 338 device_printf(dev, "device %s requested unsupported I/O " 339 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 340 device_get_nameunit(child), start, end, 341 sc->iobase, sc->iolimit); 342 return (NULL); 343 } 344 if (bootverbose) 345 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n", 346 device_get_nameunit(child), start, end); 347 break; 348 349 case SYS_RES_MEMORY: 350 ok = 0; 351 if (pcib_is_nonprefetch_open(sc)) 352 ok = ok || (start >= sc->membase && end <= sc->memlimit); 353 if (pcib_is_prefetch_open(sc)) 354 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 355 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 356 if (!ok) { 357 ok = 1; 358 if (flags & RF_PREFETCHABLE) { 359 if (pcib_is_prefetch_open(sc)) { 360 if (start < sc->pmembase) 361 start = sc->pmembase; 362 if (end > sc->pmemlimit) 363 end = sc->pmemlimit; 364 } else { 365 ok = 0; 366 } 367 } else { /* non-prefetchable */ 368 if (pcib_is_nonprefetch_open(sc)) { 369 if (start < sc->membase) 370 start = sc->membase; 371 if (end > sc->memlimit) 372 end = sc->memlimit; 373 } else { 374 ok = 0; 375 } 376 } 377 } 378 } else if (!ok) { 379 ok = 1; /* subtractive bridge: always ok */ 380#if 0 381 if (pcib_is_nonprefetch_open(sc)) { 382 if (start < sc->membase && end > sc->memlimit) { 383 start = sc->membase; 384 end = sc->memlimit; 385 } 386 } 387 if (pcib_is_prefetch_open(sc)) { 388 if (start < sc->pmembase && end > sc->pmemlimit) { 389 start = sc->pmembase; 390 end = sc->pmemlimit; 391 } 392 } 393#endif 394 } 395 if (end < start) { 396 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start); 397 start = 0; 398 end = 0; 399 ok = 0; 400 } 401 if (!ok && bootverbose) 402 device_printf(dev, 403 "device %s requested unsupported memory range " 404 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 405 device_get_nameunit(child), start, end, 406 sc->membase, sc->memlimit, sc->pmembase, 407 sc->pmemlimit); 408 if (!ok) 409 return (NULL); 410 if (bootverbose) 411 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n", 412 device_get_nameunit(child), start, end); 413 break; 414 415 default: 416 break; 417 } 418 /* 419 * Bridge is OK decoding this resource, so pass it up. 420 */ 421 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 422} 423 424/* 425 * PCIB interface. 426 */ 427int 428pcib_maxslots(device_t dev) 429{ 430 return(PCI_SLOTMAX); 431} 432 433/* 434 * Since we are a child of a PCI bus, its parent must support the pcib interface. 435 */ 436uint32_t 437pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 438{ 439 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 440} 441 442void 443pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 444{ 445 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 446} 447 448/* 449 * Route an interrupt across a PCI bridge. 450 */ 451int 452pcib_route_interrupt(device_t pcib, device_t dev, int pin) 453{ 454 device_t bus; 455 int parent_intpin; 456 int intnum; 457 458 /* 459 * 460 * The PCI standard defines a swizzle of the child-side device/intpin to 461 * the parent-side intpin as follows. 462 * 463 * device = device on child bus 464 * child_intpin = intpin on child bus slot (0-3) 465 * parent_intpin = intpin on parent bus slot (0-3) 466 * 467 * parent_intpin = (device + child_intpin) % 4 468 */ 469 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 470 471 /* 472 * Our parent is a PCI bus. Its parent must export the pcib interface 473 * which includes the ability to route interrupts. 474 */ 475 bus = device_get_parent(pcib); 476 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 477 if (PCI_INTERRUPT_VALID(intnum)) { 478 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 479 pci_get_slot(dev), 'A' + pin - 1, intnum); 480 } 481 return(intnum); 482} 483 484/* 485 * Try to read the bus number of a host-PCI bridge using appropriate config 486 * registers. 487 */ 488int 489host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 490 uint8_t *busnum) 491{ 492 uint32_t id; 493 494 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 495 if (id == 0xffffffff) 496 return (0); 497 498 switch (id) { 499 case 0x12258086: 500 /* Intel 824?? */ 501 /* XXX This is a guess */ 502 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 503 *busnum = bus; 504 break; 505 case 0x84c48086: 506 /* Intel 82454KX/GX (Orion) */ 507 *busnum = read_config(bus, slot, func, 0x4a, 1); 508 break; 509 case 0x84ca8086: 510 /* 511 * For the 450nx chipset, there is a whole bundle of 512 * things pretending to be host bridges. The MIOC will 513 * be seen first and isn't really a pci bridge (the 514 * actual busses are attached to the PXB's). We need to 515 * read the registers of the MIOC to figure out the 516 * bus numbers for the PXB channels. 517 * 518 * Since the MIOC doesn't have a pci bus attached, we 519 * pretend it wasn't there. 520 */ 521 return (0); 522 case 0x84cb8086: 523 switch (slot) { 524 case 0x12: 525 /* Intel 82454NX PXB#0, Bus#A */ 526 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 527 break; 528 case 0x13: 529 /* Intel 82454NX PXB#0, Bus#B */ 530 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 531 break; 532 case 0x14: 533 /* Intel 82454NX PXB#1, Bus#A */ 534 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 535 break; 536 case 0x15: 537 /* Intel 82454NX PXB#1, Bus#B */ 538 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 539 break; 540 } 541 break; 542 543 /* ServerWorks -- vendor 0x1166 */ 544 case 0x00051166: 545 case 0x00061166: 546 case 0x00081166: 547 case 0x00091166: 548 case 0x00101166: 549 case 0x00111166: 550 case 0x00171166: 551 case 0x01011166: 552 case 0x010f1014: 553 case 0x02011166: 554 case 0x03021014: 555 *busnum = read_config(bus, slot, func, 0x44, 1); 556 break; 557 default: 558 /* Don't know how to read bus number. */ 559 return 0; 560 } 561 562 return 1; 563} 564