pccbbreg.h revision 90751
1/* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pccbb/pccbbreg.h 90751 2002-02-17 03:11:11Z imp $ 29 */ 30 31/* 32 * Register definitions for PCI to Cardbus Bridge chips 33 */ 34 35 36/* PCI header registers */ 37#define CBBR_SOCKBASE 0x10 /* len=4 */ 38 39#define CBBR_MEMBASE0 0x1c /* len=4 */ 40#define CBBR_MEMLIMIT0 0x20 /* len=4 */ 41#define CBBR_MEMBASE1 0x24 /* len=4 */ 42#define CBBR_MEMLIMIT1 0x28 /* len=4 */ 43#define CBBR_IOBASE0 0x2c /* len=4 */ 44#define CBBR_IOLIMIT0 0x30 /* len=4 */ 45#define CBBR_IOBASE1 0x34 /* len=4 */ 46#define CBBR_IOLIMIT1 0x38 /* len=4 */ 47#define CBB_MEMALIGN 4096 48#define CBB_IOALIGN 4 49 50#define CBBR_INTRLINE 0x3c /* len=1 */ 51#define CBBR_INTRPIN 0x3d /* len=1 */ 52#define CBBR_BRIDGECTRL 0x3e /* len=2 */ 53# define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 54# define CBBM_BRIDGECTRL_RESET 0x0040 55# define CBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080 56# define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 57# define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 58# define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 59 /* additional bit for RF5C46[567] */ 60# define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 61# define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 62 63#define CBBR_LEGACY 0x44 /* len=4 */ 64 65#define CBBR_CBCTRL 0x91 /* len=1 */ 66 /* bits for TI 113X */ 67# define CBBM_CBCTRL_113X_RI_EN 0x80 68# define CBBM_CBCTRL_113X_ZV_EN 0x40 69# define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 70# define CBBM_CBCTRL_113X_PCI_INTR 0x10 71# define CBBM_CBCTRL_113X_PCI_CSC 0x08 72# define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 73# define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 74# define CBBM_CBCTRL_113X_INTR_DET 0x01 75 /* bits for TI 12XX */ 76# define CBBM_CBCTRL_12XX_RI_EN 0x80 77# define CBBM_CBCTRL_12XX_ZV_EN 0x40 78# define CBBM_CBCTRL_12XX_AUD2MUX 0x04 79# define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 80# define CBBM_CBCTRL_12XX_INTR_DET 0x01 81#define CBBR_DEVCTRL 0x92 /* len=1 */ 82# define CBBM_DEVCTRL_INT_SERIAL 0x04 83# define CBBM_DEVCTRL_INT_PCI 0x02 84 85/* ToPIC 95 ONLY */ 86#define CBBR_TOPIC_SOCKETCTRL 0x90 87# define CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 88/* ToPIC 97, 100 */ 89#define CBBR_TOPIC_ZV_CONTROL 0x9c /* 1 byte */ 90# define CBBM_TOPIC_ZVC_ENABLE 0x1 91 92/* TOPIC 95+ */ 93#define CBBR_TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 94# define CBBM_TOPIC_SLOTCTRL_SLOTON 0x80 95# define CBBM_TOPIC_SLOTCTRL_SLOTEN 0x40 96# define CBBM_TOPIC_SLOTCTRL_ID_LOCK 0x20 97# define CBBM_TOPIC_SLOTCTRL_ID_WP 0x10 98# define CBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0c 99# define CBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2 100# define CBBM_TOPIC_SLOTCTRL_OSF_MASK 0x03 101# define CBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0 102 103/* TOPIC 95+ */ 104#define CBBR_TOPIC_INTCTRL 0xa1 /* 1 byte */ 105# define CBBM_TOPIC_INTCTRL_INTB 0x20 106# define CBBM_TOPIC_INTCTRL_INTA 0x10 107# define CBBM_TOPIC_INTCTRL_INT_MASK 0x30 108/* The following bits may be for ToPIC 95 only */ 109# define CBBM_TOPIC_INTCTRL_CLOCK_MASK 0x0c 110# define CBBM_TOPIC_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 111# define CBBM_TOPIC_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 112# define CBBM_TOPIC_INTCTRL_CLOCK_0 0x00 /* no clock */ 113/* ToPIC97, 100 defines the following bits */ 114# define CBBM_TOPIC_INTCTRL_STSIRQNP 0x04 115# define CBBM_TOPIC_INTCTRL_IRQNP 0x02 116# define CBBM_TOPIC_INTCTRL_INTIRQSEL 0x01 117 118/* TOPIC 95+ */ 119#define CBBR_TOPIC_CDC 0xa3 /* 1 byte */ 120# define CBBM_TOPIC_CDC_CARDBUS 0x80 121# define CBBM_TOPIC_CDC_VS1 0x04 122# define CBBM_TOPIC_CDC_VS2 0x02 123# define CBBM_TOPIC_CDC_SWDETECT 0x01 124 125/* Socket definitions */ 126#define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 127#define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 128#define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 129#define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 130#define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 131 132#define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 133#define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 134#define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 135 136#define CBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */ 137#define CBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */ 138#define CBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */ 139#define CBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */ 140#define CBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */ 141#define CBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */ 142#define CBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */ 143#define CBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */ 144#define CBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */ 145#define CBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */ 146#define CBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */ 147#define CBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */ 148#define CBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */ 149#define CBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */ 150#define CBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */ 151#define CBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 152#define CBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 153#define CBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 154#define CBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 155 156#define CBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */ 157 158#define CBB_SOCKET_CTRL_VPPMASK 0x07 159#define CBB_SOCKET_CTRL_VPP_OFF 0x00 160#define CBB_SOCKET_CTRL_VPP_12V 0x01 161#define CBB_SOCKET_CTRL_VPP_5V 0x02 162#define CBB_SOCKET_CTRL_VPP_3V 0x03 163#define CBB_SOCKET_CTRL_VPP_XV 0x04 164#define CBB_SOCKET_CTRL_VPP_YV 0x05 165 166#define CBB_SOCKET_CTRL_VCCMASK 0x70 167#define CBB_SOCKET_CTRL_VCC_OFF 0x00 168#define CBB_SOCKET_CTRL_VCC_5V 0x20 169#define CBB_SOCKET_CTRL_VCC_3V 0x30 170#define CBB_SOCKET_CTRL_VCC_XV 0x40 171#define CBB_SOCKET_CTRL_VCC_YV 0x50 172 173#define CBB_SOCKET_CTRL_STOPCLK 0x80 174 175#include <dev/pccbb/pccbbdevid.h> 176 177#define CBB_SOCKET_EVENT 0x00 178#define CBB_SOCKET_MASK 0x04 179#define CBB_SOCKET_STATE 0x08 180#define CBB_SOCKET_FORCE 0x0c 181#define CBB_SOCKET_CONTROL 0x10 182#define CBB_SOCKET_POWER 0x14 183