pccbbreg.h revision 100704
1/* 2 * Copyright (c) 2000,2001 Jonathan Chen. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/pccbb/pccbbreg.h 100704 2002-07-26 08:05:25Z imp $ 29 */ 30 31/* 32 * Copyright (c) 1998, 1999 and 2000 33 * HAYAKAWA Koichi. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by HAYAKAWA Koichi. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61/* 62 * Register definitions for PCI to Cardbus Bridge chips 63 */ 64 65 66/* PCI header registers */ 67#define CBBR_SOCKBASE 0x10 /* len=4 */ 68 69#define CBBR_MEMBASE0 0x1c /* len=4 */ 70#define CBBR_MEMLIMIT0 0x20 /* len=4 */ 71#define CBBR_MEMBASE1 0x24 /* len=4 */ 72#define CBBR_MEMLIMIT1 0x28 /* len=4 */ 73#define CBBR_IOBASE0 0x2c /* len=4 */ 74#define CBBR_IOLIMIT0 0x30 /* len=4 */ 75#define CBBR_IOBASE1 0x34 /* len=4 */ 76#define CBBR_IOLIMIT1 0x38 /* len=4 */ 77#define CBB_MEMALIGN 4096 78#define CBB_IOALIGN 4 79 80#define CBBR_INTRLINE 0x3c /* len=1 */ 81#define CBBR_INTRPIN 0x3d /* len=1 */ 82#define CBBR_BRIDGECTRL 0x3e /* len=2 */ 83# define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 84# define CBBM_BRIDGECTRL_RESET 0x0040 85# define CBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080 86# define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 87# define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 88# define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 89 /* additional bit for RF5C46[567] */ 90# define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 91# define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 92 93#define CBBR_LEGACY 0x44 /* len=4 */ 94 95/* TI * */ 96#define CBBR_SYSCTRL 0x80 /* len=4 */ 97# define CBBM_SYSCTRL_INTRTIE 0x20000000u 98 99/* TI [14][245]xx */ 100#define CBBR_MMCTRL 0x84 /* len=4 */ 101 102/* TI 12xx/14xx/15xx (except 1250/1251/1251B/1450) */ 103#define CBBR_MFUNC 0x8c /* len=4 */ 104# define CBBM_MFUNC_PIN0 0x0000000f 105# define CBBM_MFUNC_PIN0_INTA 0x02 106# define CBBM_MFUNC_PIN1 0x000000f0 107# define CBBM_MFUNC_PIN1_INTB 0x20 108# define CBBM_MFUNC_PIN2 0x00000f00 109# define CBBM_MFUNC_PIN3 0x0000f000 110# define CBBM_MFUNC_PIN4 0x000f0000 111# define CBBM_MFUNC_PIN5 0x00f00000 112# define CBBM_MFUNC_PIN6 0x0f000000 113 114#define CBBR_CBCTRL 0x91 /* len=1 */ 115 /* bits for TI 113X */ 116# define CBBM_CBCTRL_113X_RI_EN 0x80 117# define CBBM_CBCTRL_113X_ZV_EN 0x40 118# define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 119# define CBBM_CBCTRL_113X_PCI_INTR 0x10 120# define CBBM_CBCTRL_113X_PCI_CSC 0x08 121# define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 122# define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 123# define CBBM_CBCTRL_113X_INTR_DET 0x01 124 /* TI [14][245]xx */ 125# define CBBM_CBCTRL_12XX_RI_EN 0x80 126# define CBBM_CBCTRL_12XX_ZV_EN 0x40 127# define CBBM_CBCTRL_12XX_AUD2MUX 0x04 128# define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 129# define CBBM_CBCTRL_12XX_INTR_DET 0x01 130#define CBBR_DEVCTRL 0x92 /* len=1 */ 131# define CBBM_DEVCTRL_INT_SERIAL 0x04 132# define CBBM_DEVCTRL_INT_PCI 0x02 133 134/* ToPIC 95 ONLY */ 135#define CBBR_TOPIC_SOCKETCTRL 0x90 136# define CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 137/* ToPIC 97, 100 */ 138#define CBBR_TOPIC_ZV_CONTROL 0x9c /* 1 byte */ 139# define CBBM_TOPIC_ZVC_ENABLE 0x1 140 141/* TOPIC 95+ */ 142#define CBBR_TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 143# define CBBM_TOPIC_SLOTCTRL_SLOTON 0x80 144# define CBBM_TOPIC_SLOTCTRL_SLOTEN 0x40 145# define CBBM_TOPIC_SLOTCTRL_ID_LOCK 0x20 146# define CBBM_TOPIC_SLOTCTRL_ID_WP 0x10 147# define CBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0c 148# define CBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2 149# define CBBM_TOPIC_SLOTCTRL_OSF_MASK 0x03 150# define CBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0 151 152/* TOPIC 95+ */ 153#define CBBR_TOPIC_INTCTRL 0xa1 /* 1 byte */ 154# define CBBM_TOPIC_INTCTRL_INTB 0x20 155# define CBBM_TOPIC_INTCTRL_INTA 0x10 156# define CBBM_TOPIC_INTCTRL_INT_MASK 0x30 157/* The following bits may be for ToPIC 95 only */ 158# define CBBM_TOPIC_INTCTRL_CLOCK_MASK 0x0c 159# define CBBM_TOPIC_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 160# define CBBM_TOPIC_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 161# define CBBM_TOPIC_INTCTRL_CLOCK_0 0x00 /* no clock */ 162/* ToPIC97, 100 defines the following bits */ 163# define CBBM_TOPIC_INTCTRL_STSIRQNP 0x04 164# define CBBM_TOPIC_INTCTRL_IRQNP 0x02 165# define CBBM_TOPIC_INTCTRL_INTIRQSEL 0x01 166 167/* TOPIC 95+ */ 168#define CBBR_TOPIC_CDC 0xa3 /* 1 byte */ 169# define CBBM_TOPIC_CDC_CARDBUS 0x80 170# define CBBM_TOPIC_CDC_VS1 0x04 171# define CBBM_TOPIC_CDC_VS2 0x02 172# define CBBM_TOPIC_CDC_SWDETECT 0x01 173 174/* Socket definitions */ 175#define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 176#define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 177#define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 178#define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 179#define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 180 181#define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 182#define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 183#define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 184 185#define CBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */ 186#define CBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */ 187#define CBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */ 188#define CBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */ 189#define CBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */ 190#define CBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */ 191#define CBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */ 192#define CBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */ 193#define CBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */ 194#define CBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */ 195#define CBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */ 196#define CBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */ 197#define CBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */ 198#define CBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */ 199#define CBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */ 200#define CBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */ 201#define CBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */ 202#define CBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */ 203#define CBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */ 204 205#define CBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */ 206 207#define CBB_SOCKET_CTRL_VPPMASK 0x07 208#define CBB_SOCKET_CTRL_VPP_OFF 0x00 209#define CBB_SOCKET_CTRL_VPP_12V 0x01 210#define CBB_SOCKET_CTRL_VPP_5V 0x02 211#define CBB_SOCKET_CTRL_VPP_3V 0x03 212#define CBB_SOCKET_CTRL_VPP_XV 0x04 213#define CBB_SOCKET_CTRL_VPP_YV 0x05 214 215#define CBB_SOCKET_CTRL_VCCMASK 0x70 216#define CBB_SOCKET_CTRL_VCC_OFF 0x00 217#define CBB_SOCKET_CTRL_VCC_5V 0x20 218#define CBB_SOCKET_CTRL_VCC_3V 0x30 219#define CBB_SOCKET_CTRL_VCC_XV 0x40 220#define CBB_SOCKET_CTRL_VCC_YV 0x50 221 222#define CBB_SOCKET_CTRL_STOPCLK 0x80 223 224#include <dev/pccbb/pccbbdevid.h> 225 226#define CBB_SOCKET_EVENT 0x00 227#define CBB_SOCKET_MASK 0x04 228#define CBB_SOCKET_STATE 0x08 229#define CBB_SOCKET_FORCE 0x0c 230#define CBB_SOCKET_CONTROL 0x10 231#define CBB_SOCKET_POWER 0x14 232 233#define CBB_EXCA_OFFSET 0x800 /* offset for exca regs */ 234