1193240Ssam/*-
2193240Ssam * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
3193240Ssam * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
4193240Ssam * All rights reserved.
5193240Ssam *
6193240Ssam * Redistribution and use in source and binary forms, with or without
7193240Ssam * modification, are permitted provided that the following conditions
8193240Ssam * are met:
9193240Ssam * 1. Redistributions of source code must retain the above copyright
10193240Ssam *    notice, this list of conditions and the following disclaimer,
11193240Ssam *    without modification.
12193240Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13193240Ssam *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14193240Ssam *    redistribution must be conditioned upon including a substantially
15193240Ssam *    similar Disclaimer requirement for further binary redistribution.
16193240Ssam *
17193240Ssam * NO WARRANTY
18193240Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19193240Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20193240Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21193240Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22193240Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23193240Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24193240Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25193240Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26193240Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27193240Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28193240Ssam * THE POSSIBILITY OF SUCH DAMAGES.
29193240Ssam *
30193240Ssam * $FreeBSD: releng/11.0/sys/dev/mwl/mwlreg.h 195171 2009-06-29 18:42:54Z sam $
31193240Ssam */
32193240Ssam
33193240Ssam/*
34193240Ssam * Definitions for the Marvell Wireless LAN controller Hardware Access Layer.
35193240Ssam */
36193240Ssam#ifndef _MWL_HALREG_H_
37193240Ssam#define _MWL_HALREG_H_
38193240Ssam
39193240Ssam#define MWL_ANT_INFO_SUPPORT		/* per-antenna data in rx descriptor */
40193240Ssam
41193240Ssam#define	MACREG_REG_TSF_LOW	0xa600		/* TSF lo */
42193240Ssam#define	MACREG_REG_TSF_HIGH	0xa604		/* TSF hi */
43193240Ssam#define	MACREG_REG_CHIP_REV	0xa814		/* chip rev */
44193240Ssam
45193240Ssam//          Map to 0x80000000 (Bus control) on BAR0
46193240Ssam#define MACREG_REG_H2A_INTERRUPT_EVENTS     	0x00000C18 // (From host to ARM)
47193240Ssam#define MACREG_REG_H2A_INTERRUPT_CAUSE      	0x00000C1C // (From host to ARM)
48193240Ssam#define MACREG_REG_H2A_INTERRUPT_MASK       	0x00000C20 // (From host to ARM)
49193240Ssam#define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL      0x00000C24 // (From host to ARM)
50193240Ssam#define MACREG_REG_H2A_INTERRUPT_STATUS_MASK	0x00000C28 // (From host to ARM)
51193240Ssam
52193240Ssam#define MACREG_REG_A2H_INTERRUPT_EVENTS     	0x00000C2C // (From ARM to host)
53193240Ssam#define MACREG_REG_A2H_INTERRUPT_CAUSE      	0x00000C30 // (From ARM to host)
54193240Ssam#define MACREG_REG_A2H_INTERRUPT_MASK       	0x00000C34 // (From ARM to host)
55193240Ssam#define MACREG_REG_A2H_INTERRUPT_CLEAR_SEL      0x00000C38 // (From ARM to host)
56193240Ssam#define MACREG_REG_A2H_INTERRUPT_STATUS_MASK    0x00000C3C // (From ARM to host)
57193240Ssam
58193240Ssam
59193240Ssam//  Map to 0x80000000 on BAR1
60193240Ssam#define MACREG_REG_GEN_PTR                  0x00000C10
61193240Ssam#define MACREG_REG_INT_CODE                 0x00000C14
62193240Ssam#define MACREG_REG_SCRATCH                  0x00000C40
63193240Ssam#define MACREG_REG_FW_PRESENT		0x0000BFFC
64193240Ssam
65193240Ssam#define	MACREG_REG_PROMISCUOUS		0xA300
66193240Ssam
67193240Ssam//	Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC)
68193240Ssam#define MACREG_A2HRIC_BIT_TX_DONE       0x00000001 // bit 0
69193240Ssam#define MACREG_A2HRIC_BIT_RX_RDY        0x00000002 // bit 1
70193240Ssam#define MACREG_A2HRIC_BIT_OPC_DONE      0x00000004 // bit 2
71193240Ssam#define MACREG_A2HRIC_BIT_MAC_EVENT     0x00000008 // bit 3
72193240Ssam#define MACREG_A2HRIC_BIT_RX_PROBLEM    0x00000010 // bit 4
73193240Ssam
74193240Ssam#define MACREG_A2HRIC_BIT_RADIO_OFF     0x00000020 // bit 5
75193240Ssam#define MACREG_A2HRIC_BIT_RADIO_ON      0x00000040 // bit 6
76193240Ssam
77193240Ssam#define MACREG_A2HRIC_BIT_RADAR_DETECT  0x00000080 // bit 7
78193240Ssam
79193240Ssam#define MACREG_A2HRIC_BIT_ICV_ERROR     0x00000100 // bit 8
80193240Ssam#define MACREG_A2HRIC_BIT_MIC_ERROR     0x00000200 // bit 9
81193240Ssam#define MACREG_A2HRIC_BIT_QUEUE_EMPTY	0x00004000
82193240Ssam#define MACREG_A2HRIC_BIT_QUEUE_FULL	0x00000800
83193240Ssam#define MACREG_A2HRIC_BIT_CHAN_SWITCH   0x00001000
84193240Ssam#define MACREG_A2HRIC_BIT_TX_WATCHDOG	0x00002000
85193240Ssam#define MACREG_A2HRIC_BIT_BA_WATCHDOG	0x00000400
86195171Ssam#define	MACREQ_A2HRIC_BIT_TX_ACK	0x00008000
87193240Ssam#define ISR_SRC_BITS        ((MACREG_A2HRIC_BIT_RX_RDY)   | \
88193240Ssam                             (MACREG_A2HRIC_BIT_TX_DONE)  | \
89193240Ssam                             (MACREG_A2HRIC_BIT_OPC_DONE) | \
90193240Ssam                             (MACREG_A2HRIC_BIT_MAC_EVENT)| \
91193240Ssam                             (MACREG_A2HRIC_BIT_MIC_ERROR)| \
92193240Ssam                             (MACREG_A2HRIC_BIT_ICV_ERROR)| \
93193240Ssam                             (MACREG_A2HRIC_BIT_RADAR_DETECT)| \
94193240Ssam                             (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \
95193240Ssam                             (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \
96193240Ssam                             (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \
97195171Ssam                             (MACREG_A2HRIC_BIT_BA_WATCHDOG)| \
98195171Ssam			     (MACREQ_A2HRIC_BIT_TX_ACK))
99193240Ssam
100193240Ssam#define MACREG_A2HRIC_BIT_MASK      ISR_SRC_BITS
101193240Ssam
102193240Ssam
103193240Ssam//	Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC)
104195171Ssam#define MACREG_H2ARIC_BIT_PPA_READY	0x00000001 // bit 0
105195171Ssam#define MACREG_H2ARIC_BIT_DOOR_BELL	0x00000002 // bit 1
106193240Ssam#define ISR_RESET           				(1<<15)
107193240Ssam
108193240Ssam//	INT code register event definition
109193240Ssam#define MACREG_INT_CODE_CMD_FINISHED        0x00000005
110193240Ssam
111193240Ssam/*
112193240Ssam * Host/Firmware Interface definitions.
113193240Ssam */
114193240Ssam
115193240Ssam/**
116193240Ssam * Define total number of TX queues in the shared memory.
117193240Ssam * This count includes the EDCA queues, Block Ack queues, and HCCA queues
118193240Ssam * In addition to this, there could be a management packet queue some
119193240Ssam * time in the future
120193240Ssam */
121193240Ssam#define NUM_EDCA_QUEUES		4
122193240Ssam#define NUM_HCCA_QUEUES		0
123193240Ssam#define NUM_BA_QUEUES		0
124193240Ssam#define NUM_MGMT_QUEUES		0
125195171Ssam#define	NUM_ACK_EVENT_QUEUE	1
126193240Ssam#define TOTAL_TX_QUEUES \
127195171Ssam	(NUM_EDCA_QUEUES + NUM_HCCA_QUEUES + NUM_BA_QUEUES + NUM_MGMT_QUEUES + NUM_ACK_EVENT_QUEUE)
128195171Ssam#define MAX_TXWCB_QUEUES	TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE
129193240Ssam#define MAX_RXWCB_QUEUES	1
130193240Ssam
131193240Ssam//=============================================================================
132193240Ssam//          PUBLIC DEFINITIONS
133193240Ssam//=============================================================================
134193240Ssam
135193240Ssam#define RATE_INDEX_MAX_ARRAY        14
136193240Ssam#define WOW_MAX_STATION         32
137193240Ssam
138193240Ssam/*
139193240Ssam * Hardware tx/rx descriptors.
140193240Ssam *
141193240Ssam * NB: tx descriptor size must match f/w expected size
142193240Ssam * because f/w prefetch's the next descriptor linearly
143193240Ssam * and doesn't chase the next pointer.
144193240Ssam */
145193240Ssamstruct mwl_txdesc {
146193240Ssam	uint32_t	Status;
147193240Ssam#define	EAGLE_TXD_STATUS_IDLE		0x00000000
148193240Ssam#define	EAGLE_TXD_STATUS_USED		0x00000001
149193240Ssam#define	EAGLE_TXD_STATUS_OK		0x00000001
150193240Ssam#define	EAGLE_TXD_STATUS_OK_RETRY	0x00000002
151193240Ssam#define	EAGLE_TXD_STATUS_OK_MORE_RETRY	0x00000004
152193240Ssam#define	EAGLE_TXD_STATUS_MULTICAST_TX	0x00000008
153193240Ssam#define	EAGLE_TXD_STATUS_BROADCAST_TX	0x00000010
154193240Ssam#define	EAGLE_TXD_STATUS_FAILED_LINK_ERROR		0x00000020
155193240Ssam#define	EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT		0x00000040
156193240Ssam#define	EAGLE_TXD_STATUS_FAILED_XRETRY	EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT
157193240Ssam#define	EAGLE_TXD_STATUS_FAILED_AGING	0x00000080
158193240Ssam#define	EAGLE_TXD_STATUS_FW_OWNED	0x80000000
159193240Ssam	uint8_t		DataRate;
160193240Ssam	uint8_t		TxPriority;
161193240Ssam	uint16_t	QosCtrl;
162193240Ssam	uint32_t	PktPtr;
163193240Ssam	uint16_t	PktLen;
164193240Ssam	uint8_t		DestAddr[6];
165193240Ssam	uint32_t	pPhysNext;
166193240Ssam	uint32_t	SapPktInfo;
167193240Ssam#define	EAGLE_TXD_MODE_BONLY	1
168193240Ssam#define	EAGLE_TXD_MODE_GONLY	2
169193240Ssam#define	EAGLE_TXD_MODE_BG	3
170193240Ssam#define	EAGLE_TXD_MODE_NONLY	4
171193240Ssam#define	EAGLE_TXD_MODE_BN	5
172193240Ssam#define	EAGLE_TXD_MODE_GN	6
173193240Ssam#define	EAGLE_TXD_MODE_BGN	7
174193240Ssam#define	EAGLE_TXD_MODE_AONLY	8
175193240Ssam#define	EAGLE_TXD_MODE_AG	10
176193240Ssam#define	EAGLE_TXD_MODE_AN	12
177193240Ssam	uint16_t	Format;
178193240Ssam#define	EAGLE_TXD_FORMAT	0x0001	/* frame format/rate */
179193240Ssam#define	EAGLE_TXD_FORMAT_LEGACY	0x0000	/* legacy rate frame */
180193240Ssam#define	EAGLE_TXD_FORMAT_HT	0x0001	/* HT rate frame */
181193240Ssam#define	EAGLE_TXD_GI		0x0002	/* guard interval */
182193240Ssam#define	EAGLE_TXD_GI_SHORT	0x0002	/* short guard interval */
183193240Ssam#define	EAGLE_TXD_GI_LONG	0x0000	/* long guard interval */
184193240Ssam#define	EAGLE_TXD_CHW		0x0004	/* channel width */
185193240Ssam#define	EAGLE_TXD_CHW_20	0x0000	/* 20MHz channel width */
186193240Ssam#define	EAGLE_TXD_CHW_40	0x0004	/* 40MHz channel width */
187193240Ssam#define	EAGLE_TXD_RATE		0x01f8	/* tx rate (legacy)/ MCS */
188193240Ssam#define	EAGLE_TXD_RATE_S	3
189193240Ssam#define	EAGLE_TXD_ADV		0x0600	/* advanced coding */
190193240Ssam#define	EAGLE_TXD_ADV_S		9
191193240Ssam#define	EAGLE_TXD_ADV_NONE	0x0000
192193240Ssam#define	EAGLE_TXD_ADV_LDPC	0x0200
193193240Ssam#define	EAGLE_TXD_ADV_RS	0x0400
194193240Ssam/* NB: 3 is reserved */
195193240Ssam#define	EAGLE_TXD_ANTENNA	0x1800	/* antenna select */
196193240Ssam#define	EAGLE_TXD_ANTENNA_S	11
197193240Ssam#define	EAGLE_TXD_EXTCHAN	0x6000	/* extension channel */
198193240Ssam#define	EAGLE_TXD_EXTCHAN_S	13
199193240Ssam#define	EAGLE_TXD_EXTCHAN_HI	0x0000	/* above */
200193240Ssam#define	EAGLE_TXD_EXTCHAN_LO	0x2000	/* below */
201193240Ssam#define	EAGLE_TXD_PREAMBLE	0x8000
202193240Ssam#define	EAGLE_TXD_PREAMBLE_SHORT 0x8000	/* short preamble */
203193240Ssam#define	EAGLE_TXD_PREAMBLE_LONG 0x0000	/* long preamble */
204193240Ssam	uint16_t	pad;		/* align to 4-byte boundary */
205193240Ssam#define	EAGLE_TXD_FIXED_RATE	0x0100	/* get tx rate from Format */
206193240Ssam#define	EAGLE_TXD_DONT_AGGR	0x0200	/* don't aggregate frame */
207195171Ssam	uint32_t	ack_wcb_addr;
208193240Ssam} __packed;
209193240Ssam
210193240Ssamstruct mwl_ant_info {
211193240Ssam	uint8_t		rssi_a;	/* RSSI for antenna A */
212193240Ssam	uint8_t		rssi_b;	/* RSSI for antenna B */
213193240Ssam	uint8_t		rssi_c;	/* RSSI for antenna C */
214193240Ssam	uint8_t		rsvd1;	/* Reserved */
215193240Ssam	uint8_t		nf_a;	/* Noise floor for antenna A */
216193240Ssam	uint8_t		nf_b;	/* Noise floor for antenna B */
217193240Ssam	uint8_t		nf_c;	/* Noise floor for antenna C */
218193240Ssam	uint8_t		rsvd2;	/* Reserved */
219193240Ssam	uint8_t		nf;		/* Noise floor */
220195171Ssam	uint8_t		rsvd3[3];   /* Reserved - To make word aligned */
221193240Ssam} __packed;
222193240Ssam
223193240Ssamstruct mwl_rxdesc {
224193240Ssam	uint8_t		RxControl;	/* control element */
225193240Ssam#define	EAGLE_RXD_CTRL_DRIVER_OWN	0x00
226193240Ssam#define	EAGLE_RXD_CTRL_OS_OWN		0x04
227193240Ssam#define	EAGLE_RXD_CTRL_DMA_OWN		0x80
228193240Ssam	uint8_t		RSSI;		/* received signal strengt indication */
229193240Ssam	uint8_t		Status;		/* status field w/ USED bit */
230193240Ssam#define	EAGLE_RXD_STATUS_IDLE		0x00
231193240Ssam#define	EAGLE_RXD_STATUS_OK		0x01
232193240Ssam#define	EAGLE_RXD_STATUS_MULTICAST_RX	0x02
233193240Ssam#define	EAGLE_RXD_STATUS_BROADCAST_RX	0x04
234193240Ssam#define	EAGLE_RXD_STATUS_FRAGMENT_RX	0x08
235193240Ssam#define	EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR	0xff
236193240Ssam#define	EAGLE_RXD_STATUS_DECRYPT_ERR_MASK	0x80
237193240Ssam#define	EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR	0x02
238193240Ssam#define	EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR	0x04
239193240Ssam#define	EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR	0x08
240193240Ssam	uint8_t		Channel;	/* channel # pkt received on */
241193240Ssam	uint16_t	PktLen;		/* total length of received data */
242193240Ssam	uint8_t		SQ2;		/* not used */
243193240Ssam	uint8_t		Rate;		/* received data rate */
244193240Ssam	uint32_t	pPhysBuffData;	/* physical address of payload data */
245193240Ssam	uint32_t	pPhysNext;	/* physical address of next RX desc */
246193240Ssam	uint16_t	QosCtrl;	/* received QosCtrl field variable */
247193240Ssam	uint16_t	HtSig2;		/* like name states */
248193240Ssam#ifdef MWL_ANT_INFO_SUPPORT
249193240Ssam	struct mwl_ant_info ai;		/* antenna info */
250193240Ssam#endif
251193240Ssam} __packed;
252193240Ssam
253193240Ssam/*
254193240Ssam//          Define OpMode for SoftAP/Station mode
255193240Ssam//
256193240Ssam//  The following mode signature has to be written to PCI scratch register#0
257193240Ssam//  right after successfully downloading the last block of firmware and
258193240Ssam//  before waiting for firmware ready signature
259193240Ssam */
260193240Ssam#define HostCmd_STA_MODE     0x5A
261193240Ssam#define HostCmd_SOFTAP_MODE  0xA5
262193240Ssam
263193240Ssam#define HostCmd_STA_FWRDY_SIGNATURE     0xF0F1F2F4
264193240Ssam#define HostCmd_SOFTAP_FWRDY_SIGNATURE  0xF1F2F4A5
265193240Ssam
266193240Ssam//***************************************************************************
267193240Ssam//***************************************************************************
268193240Ssam
269193240Ssam//***************************************************************************
270193240Ssam
271193240Ssam#define HostCmd_CMD_CODE_DNLD                   0x0001
272193240Ssam#define HostCmd_CMD_GET_HW_SPEC                 0x0003
273193240Ssam#define HostCmd_CMD_SET_HW_SPEC			0x0004
274193240Ssam#define HostCmd_CMD_MAC_MULTICAST_ADR           0x0010
275193240Ssam#define HostCmd_CMD_802_11_GET_STAT             0x0014
276193240Ssam#define HostCmd_CMD_MAC_REG_ACCESS              0x0019
277193240Ssam#define HostCmd_CMD_BBP_REG_ACCESS              0x001a
278193240Ssam#define HostCmd_CMD_RF_REG_ACCESS               0x001b
279193240Ssam#define HostCmd_CMD_802_11_RADIO_CONTROL        0x001c
280193240Ssam#define HostCmd_CMD_802_11_RF_TX_POWER          0x001e
281193240Ssam#define HostCmd_CMD_802_11_RF_ANTENNA           0x0020
282193240Ssam#define HostCmd_CMD_SET_BEACON                  0x0100
283193240Ssam#define HostCmd_CMD_SET_AID                     0x010d
284193240Ssam#define HostCmd_CMD_SET_RF_CHANNEL              0x010a
285193240Ssam#define HostCmd_CMD_SET_INFRA_MODE              0x010e
286193240Ssam#define HostCmd_CMD_SET_G_PROTECT_FLAG          0x010f
287193240Ssam#define HostCmd_CMD_802_11_RTS_THSD             0x0113
288193240Ssam#define HostCmd_CMD_802_11_SET_SLOT             0x0114
289193240Ssam
290193240Ssam#define HostCmd_CMD_802_11H_DETECT_RADAR	0x0120
291193240Ssam#define HostCmd_CMD_SET_WMM_MODE                0x0123
292193240Ssam#define HostCmd_CMD_HT_GUARD_INTERVAL		0x0124
293193240Ssam#define HostCmd_CMD_SET_FIXED_RATE              0x0126
294193240Ssam#define HostCmd_CMD_SET_LINKADAPT_CS_MODE	0x0129
295193240Ssam#define HostCmd_CMD_SET_MAC_ADDR                0x0202
296193240Ssam#define HostCmd_CMD_SET_RATE_ADAPT_MODE		0x0203
297193240Ssam#define HostCmd_CMD_GET_WATCHDOG_BITMAP		0x0205
298193240Ssam
299193240Ssam//SoftAP command code
300193240Ssam#define HostCmd_CMD_BSS_START                   0x1100
301193240Ssam#define HostCmd_CMD_SET_NEW_STN              	0x1111
302193240Ssam#define HostCmd_CMD_SET_KEEP_ALIVE           	0x1112
303193240Ssam#define HostCmd_CMD_SET_APMODE           	0x1114
304193240Ssam#define HostCmd_CMD_SET_SWITCH_CHANNEL          0x1121
305193240Ssam
306193240Ssam/*
307193240Ssam	@HWENCR@
308193240Ssam	Command to update firmware encryption keys.
309193240Ssam*/
310193240Ssam#define HostCmd_CMD_UPDATE_ENCRYPTION		0x1122
311193240Ssam/*
312193240Ssam	@11E-BA@
313193240Ssam	Command to create/destroy block ACK
314193240Ssam*/
315193240Ssam#define HostCmd_CMD_BASTREAM			0x1125
316193240Ssam#define HostCmd_CMD_SET_RIFS                	0x1126
317193240Ssam#define HostCmd_CMD_SET_N_PROTECT_FLAG          0x1131
318193240Ssam#define HostCmd_CMD_SET_N_PROTECT_OPMODE        0x1132
319193240Ssam#define HostCmd_CMD_SET_OPTIMIZATION_LEVEL      0x1133
320193240Ssam#define HostCmd_CMD_GET_CALTABLE                0x1134
321193240Ssam#define HostCmd_CMD_SET_MIMOPSHT                0x1135
322193240Ssam#define HostCmd_CMD_GET_BEACON                  0x1138
323193240Ssam#define HostCmd_CMD_SET_REGION_CODE            0x1139
324193240Ssam#define HostCmd_CMD_SET_POWERSAVESTATION	0x1140
325193240Ssam#define HostCmd_CMD_SET_TIM			0x1141
326193240Ssam#define HostCmd_CMD_GET_TIM			0x1142
327193240Ssam#define	HostCmd_CMD_GET_SEQNO			0x1143
328195171Ssam#define	HostCmd_CMD_DWDS_ENABLE			0x1144
329195171Ssam#define	HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE	0x1145
330195171Ssam#define	HostCmd_CMD_CFEND_ENABLE		0x1146
331193240Ssam
332193240Ssam/*
333193240Ssam//          Define general result code for each command
334193240Ssam */
335193240Ssam#define HostCmd_RESULT_OK                       0x0000 // OK
336193240Ssam#define HostCmd_RESULT_ERROR                    0x0001 // Genenral error
337193240Ssam#define HostCmd_RESULT_NOT_SUPPORT              0x0002 // Command is not valid
338193240Ssam#define HostCmd_RESULT_PENDING                  0x0003 // Command is pending (will be processed)
339193240Ssam#define HostCmd_RESULT_BUSY                     0x0004 // System is busy (command ignored)
340193240Ssam#define HostCmd_RESULT_PARTIAL_DATA             0x0005 // Data buffer is not big enough
341193240Ssam
342193240Ssam
343193240Ssam/*
344193240Ssam//          Definition of action or option for each command
345193240Ssam//
346193240Ssam//          Define general purpose action
347193240Ssam */
348193240Ssam#define HostCmd_ACT_GEN_READ                    0x0000
349193240Ssam#define HostCmd_ACT_GEN_WRITE                   0x0001
350193240Ssam#define HostCmd_ACT_GEN_GET                     0x0000
351193240Ssam#define HostCmd_ACT_GEN_SET                     0x0001
352193240Ssam#define HostCmd_ACT_GEN_OFF                     0x0000
353193240Ssam#define HostCmd_ACT_GEN_ON                      0x0001
354193240Ssam
355193240Ssam#define HostCmd_ACT_DIFF_CHANNEL                0x0002
356193240Ssam#define HostCmd_ACT_GEN_SET_LIST                0x0002
357193240Ssam
358193240Ssam//          Define action or option for HostCmd_FW_USE_FIXED_RATE
359193240Ssam#define HostCmd_ACT_USE_FIXED_RATE              0x0001
360193240Ssam#define HostCmd_ACT_NOT_USE_FIXED_RATE          0x0002
361193240Ssam
362193240Ssam//          Define action or option for HostCmd_CMD_802_11_SET_WEP
363193240Ssam//#define HostCmd_ACT_ENABLE                    0x0001 // Use MAC control for WEP on/off
364193240Ssam//#define HostCmd_ACT_DISABLE                   0x0000
365193240Ssam#define HostCmd_ACT_ADD                         0x0002
366193240Ssam#define HostCmd_ACT_REMOVE                      0x0004
367193240Ssam#define HostCmd_ACT_USE_DEFAULT                 0x0008
368193240Ssam
369193240Ssam#define HostCmd_TYPE_WEP_40_BIT                 0x0001 // 40 bit
370193240Ssam#define HostCmd_TYPE_WEP_104_BIT                0x0002 // 104 bit
371193240Ssam#define HostCmd_TYPE_WEP_128_BIT                0x0003 // 128 bit
372193240Ssam#define HostCmd_TYPE_WEP_TX_KEY                 0x0004 // TX WEP
373193240Ssam
374193240Ssam#define HostCmd_NUM_OF_WEP_KEYS                 4
375193240Ssam
376193240Ssam#define HostCmd_WEP_KEY_INDEX_MASK              0x3fffffff
377193240Ssam
378193240Ssam
379193240Ssam//          Define action or option for HostCmd_CMD_802_11_RESET
380193240Ssam#define HostCmd_ACT_HALT                        0x0001
381193240Ssam#define HostCmd_ACT_RESTART                     0x0002
382193240Ssam
383193240Ssam//          Define action or option for HostCmd_CMD_802_11_RADIO_CONTROL
384193240Ssam#define HostCmd_TYPE_AUTO_PREAMBLE              0x0001
385193240Ssam#define HostCmd_TYPE_SHORT_PREAMBLE             0x0002
386193240Ssam#define HostCmd_TYPE_LONG_PREAMBLE              0x0003
387193240Ssam
388193240Ssam//          Define action or option for CMD_802_11_RF_CHANNEL
389193240Ssam#define HostCmd_TYPE_802_11A                    0x0001
390193240Ssam#define HostCmd_TYPE_802_11B                    0x0002
391193240Ssam
392193240Ssam//          Define action or option for HostCmd_CMD_802_11_RF_TX_POWER
393193240Ssam#define HostCmd_ACT_TX_POWER_OPT_SET_HIGH       0x0003
394193240Ssam#define HostCmd_ACT_TX_POWER_OPT_SET_MID        0x0002
395193240Ssam#define HostCmd_ACT_TX_POWER_OPT_SET_LOW        0x0001
396193240Ssam#define HostCmd_ACT_TX_POWER_OPT_SET_AUTO        0x0000
397193240Ssam
398193240Ssam#define HostCmd_ACT_TX_POWER_LEVEL_MIN          0x000e // in dbm
399193240Ssam#define HostCmd_ACT_TX_POWER_LEVEL_GAP          0x0001 // in dbm
400193240Ssam//          Define action or option for HostCmd_CMD_802_11_DATA_RATE
401193240Ssam#define HostCmd_ACT_SET_TX_AUTO			0x0000
402193240Ssam#define HostCmd_ACT_SET_TX_FIX_RATE		0x0001
403193240Ssam#define HostCmd_ACT_GET_TX_RATE			0x0002
404193240Ssam
405193240Ssam#define HostCmd_ACT_SET_RX                      0x0001
406193240Ssam#define HostCmd_ACT_SET_TX                      0x0002
407193240Ssam#define HostCmd_ACT_SET_BOTH                    0x0003
408193240Ssam#define HostCmd_ACT_GET_RX                      0x0004
409193240Ssam#define HostCmd_ACT_GET_TX                      0x0008
410193240Ssam#define HostCmd_ACT_GET_BOTH                    0x000c
411193240Ssam
412193240Ssam#define TYPE_ANTENNA_DIVERSITY                  0xffff
413193240Ssam
414193240Ssam//          Define action or option for HostCmd_CMD_802_11_PS_MODE
415193240Ssam#define HostCmd_TYPE_CAM                        0x0000
416193240Ssam#define HostCmd_TYPE_MAX_PSP                    0x0001
417193240Ssam#define HostCmd_TYPE_FAST_PSP                   0x0002
418193240Ssam
419193240Ssam#define HostCmd_CMD_SET_EDCA_PARAMS             0x0115
420193240Ssam
421193240Ssam//=============================================================================
422193240Ssam//			HOST COMMAND DEFINITIONS
423193240Ssam//=============================================================================
424193240Ssam
425193240Ssam//
426193240Ssam//          Definition of data structure for each command
427193240Ssam//
428193240Ssam//          Define general data structure
429193240Ssamtypedef struct {
430193240Ssam    uint16_t     Cmd;
431193240Ssam    uint16_t     Length;
432193240Ssam#ifdef MWL_MBSS_SUPPORT
433193240Ssam    uint8_t      SeqNum;
434193240Ssam    uint8_t      MacId;
435193240Ssam#else
436193240Ssam    uint16_t     SeqNum;
437193240Ssam#endif
438193240Ssam    uint16_t     Result;
439193240Ssam} __packed FWCmdHdr;
440193240Ssam
441193240Ssamtypedef struct {
442193240Ssam    FWCmdHdr	CmdHdr;
443193240Ssam    uint8_t	Version;		// HW revision
444193240Ssam    uint8_t	HostIf; 		// Host interface
445193240Ssam    uint16_t	NumOfMCastAdr;		// Max. number of Multicast address FW can handle
446193240Ssam    uint8_t	PermanentAddr[6];	// MAC address
447193240Ssam    uint16_t	RegionCode; 		// Region Code
448193240Ssam    uint32_t	FWReleaseNumber;	// 4 byte of FW release number
449193240Ssam    uint32_t	ulFwAwakeCookie;	// Firmware awake cookie
450193240Ssam    uint32_t	DeviceCaps; 		// Device capabilities (see above)
451193240Ssam    uint32_t	RxPdWrPtr;		// Rx shared memory queue
452193240Ssam    uint32_t	NumTxQueues;		// # TX queues in WcbBase array
453193240Ssam    uint32_t	WcbBase[MAX_TXWCB_QUEUES];	// TX WCB Rings
454193240Ssam    uint32_t	Flags;
455193240Ssam#define	SET_HW_SPEC_DISABLEMBSS		0x08
456193240Ssam#define	SET_HW_SPEC_HOSTFORM_BEACON	0x10
457193240Ssam#define	SET_HW_SPEC_HOSTFORM_PROBERESP	0x20
458193240Ssam#define	SET_HW_SPEC_HOST_POWERSAVE	0x40
459193240Ssam#define	SET_HW_SPEC_HOSTENCRDECR_MGMT	0x80
460193240Ssam    uint32_t	TxWcbNumPerQueue;
461193240Ssam    uint32_t	TotalRxWcb;
462193240Ssam} __packed HostCmd_DS_SET_HW_SPEC;
463193240Ssam
464193240Ssamtypedef struct {
465193240Ssam    FWCmdHdr    CmdHdr;
466193240Ssam    u_int8_t    Version;          /* version of the HW                    */
467193240Ssam    u_int8_t    HostIf;           /* host interface                       */
468193240Ssam    u_int16_t   NumOfWCB;         /* Max. number of WCB FW can handle     */
469193240Ssam    u_int16_t   NumOfMCastAddr;   /* MaxNbr of MC addresses FW can handle */
470193240Ssam    u_int8_t    PermanentAddr[6]; /* MAC address programmed in HW         */
471193240Ssam    u_int16_t   RegionCode;
472193240Ssam    u_int16_t   NumberOfAntenna;  /* Number of antenna used      */
473193240Ssam    u_int32_t   FWReleaseNumber;  /* 4 byte of FW release number */
474193240Ssam    u_int32_t   WcbBase0;
475193240Ssam    u_int32_t   RxPdWrPtr;
476193240Ssam    u_int32_t   RxPdRdPtr;
477193240Ssam    u_int32_t   ulFwAwakeCookie;
478195171Ssam    u_int32_t   WcbBase1[TOTAL_TX_QUEUES-1];
479193240Ssam} __packed HostCmd_DS_GET_HW_SPEC;
480193240Ssam
481193240Ssamtypedef struct {
482193240Ssam    FWCmdHdr    CmdHdr;
483193240Ssam    u_int32_t   Enable;   /* FALSE: Disable or TRUE: Enable */
484193240Ssam} __packed HostCmd_DS_BSS_START;
485193240Ssam
486193240Ssam
487193240Ssamtypedef struct {
488193240Ssam    u_int8_t    ElemId;
489193240Ssam    u_int8_t    Len;
490193240Ssam    u_int8_t    OuiType[4]; /* 00:50:f2:01 */
491193240Ssam    u_int8_t    Ver[2];
492193240Ssam    u_int8_t    GrpKeyCipher[4];
493193240Ssam    u_int8_t    PwsKeyCnt[2];
494193240Ssam    u_int8_t    PwsKeyCipherList[4];
495193240Ssam    u_int8_t    AuthKeyCnt[2];
496193240Ssam    u_int8_t    AuthKeyList[4];
497193240Ssam} __packed RsnIE_t;
498193240Ssam
499193240Ssamtypedef struct {
500193240Ssam    u_int8_t    ElemId;
501193240Ssam    u_int8_t    Len;
502193240Ssam    u_int8_t    Ver[2];
503193240Ssam    u_int8_t    GrpKeyCipher[4];
504193240Ssam    u_int8_t    PwsKeyCnt[2];
505193240Ssam    u_int8_t    PwsKeyCipherList[4];
506193240Ssam    u_int8_t    AuthKeyCnt[2];
507193240Ssam    u_int8_t    AuthKeyList[4];
508193240Ssam    u_int8_t    RsnCap[2];
509193240Ssam} __packed Rsn48IE_t;
510193240Ssam
511193240Ssamtypedef struct {
512193240Ssam    u_int8_t    ElementId;
513193240Ssam    u_int8_t    Len;
514193240Ssam    u_int8_t    CfpCnt;
515193240Ssam    u_int8_t    CfpPeriod;
516193240Ssam    u_int16_t   CfpMaxDuration;
517193240Ssam    u_int16_t   CfpDurationRemaining;
518193240Ssam} __packed CfParams_t;
519193240Ssam
520193240Ssamtypedef struct {
521193240Ssam    u_int8_t    ElementId;
522193240Ssam    u_int8_t    Len;
523193240Ssam    u_int16_t   AtimWindow;
524193240Ssam} __packed IbssParams_t;
525193240Ssam
526193240Ssamtypedef union {
527193240Ssam    CfParams_t   CfParamSet;
528193240Ssam    IbssParams_t IbssParamSet;
529193240Ssam} __packed SsParams_t;
530193240Ssam
531193240Ssamtypedef struct {
532193240Ssam    u_int8_t    ElementId;
533193240Ssam    u_int8_t    Len;
534193240Ssam    u_int16_t   DwellTime;
535193240Ssam    u_int8_t    HopSet;
536193240Ssam    u_int8_t    HopPattern;
537193240Ssam    u_int8_t    HopIndex;
538193240Ssam} __packed FhParams_t;
539193240Ssam
540193240Ssamtypedef struct {
541193240Ssam    u_int8_t    ElementId;
542193240Ssam    u_int8_t    Len;
543193240Ssam    u_int8_t    CurrentChan;
544193240Ssam} __packed DsParams_t;
545193240Ssam
546193240Ssamtypedef union {
547193240Ssam    FhParams_t  FhParamSet;
548193240Ssam    DsParams_t  DsParamSet;
549193240Ssam} __packed PhyParams_t;
550193240Ssam
551193240Ssamtypedef struct {
552193240Ssam    u_int8_t    FirstChannelNum;
553193240Ssam    u_int8_t    NumOfChannels;
554193240Ssam    u_int8_t    MaxTxPwrLevel;
555193240Ssam} __packed ChannelInfo_t;
556193240Ssam
557193240Ssamtypedef struct {
558193240Ssam    u_int8_t       ElementId;
559193240Ssam    u_int8_t       Len;
560193240Ssam    u_int8_t       CountryStr[3];
561193240Ssam    ChannelInfo_t  ChannelInfo[40];
562193240Ssam} __packed Country_t;
563193240Ssam
564193240Ssamtypedef struct {
565193240Ssam    u_int8_t AIFSN : 4;
566193240Ssam    u_int8_t ACM : 1;
567193240Ssam    u_int8_t ACI : 2;
568193240Ssam    u_int8_t rsvd : 1;
569193240Ssam
570193240Ssam}__packed ACIAIFSN_field_t;
571193240Ssam
572193240Ssamtypedef  struct {
573193240Ssam    u_int8_t ECW_min : 4;
574193240Ssam    u_int8_t ECW_max : 4;
575193240Ssam}__packed  ECWmin_max_field_t;
576193240Ssam
577193240Ssamtypedef struct {
578193240Ssam    ACIAIFSN_field_t ACI_AIFSN;
579193240Ssam    ECWmin_max_field_t ECW_min_max;
580193240Ssam    u_int16_t TXOP_lim;
581193240Ssam}__packed  ACparam_rcd_t;
582193240Ssam
583193240Ssamtypedef struct {
584193240Ssam    u_int8_t    ElementId;
585193240Ssam    u_int8_t    Len;
586193240Ssam    u_int8_t    OUI[3];
587193240Ssam    u_int8_t    Type;
588193240Ssam    u_int8_t    Subtype;
589193240Ssam    u_int8_t    version;
590193240Ssam    u_int8_t    rsvd;
591193240Ssam    ACparam_rcd_t AC_BE;
592193240Ssam    ACparam_rcd_t AC_BK;
593193240Ssam    ACparam_rcd_t AC_VI;
594193240Ssam    ACparam_rcd_t AC_VO;
595193240Ssam} __packed WMM_param_elem_t ;
596193240Ssam
597193240Ssamtypedef struct {
598193240Ssam#ifdef MWL_MBSS_SUPPORT
599193240Ssam    u_int8_t	StaMacAddr[6];
600193240Ssam#endif
601193240Ssam    u_int8_t    SsId[32];
602193240Ssam    u_int8_t    BssType;
603193240Ssam    u_int16_t   BcnPeriod;
604193240Ssam    u_int8_t    DtimPeriod;
605193240Ssam    SsParams_t  SsParamSet;
606193240Ssam    PhyParams_t PhyParamSet;
607193240Ssam    u_int16_t   ProbeDelay;
608193240Ssam    u_int16_t   CapInfo;		/* see below */
609193240Ssam    u_int8_t    BssBasicRateSet[14];
610193240Ssam    u_int8_t    OpRateSet[14];
611193240Ssam    RsnIE_t     RsnIE;
612193240Ssam    Rsn48IE_t   Rsn48IE;
613193240Ssam    WMM_param_elem_t  WMMParam;
614193240Ssam    Country_t   Country;
615193240Ssam    u_int32_t   ApRFType; /* 0->B, 1->G, 2->Mixed, 3->A, 4->11J */
616193240Ssam} __packed StartCmd_t;
617193240Ssam
618193240Ssam#define HostCmd_CAPINFO_DEFAULT                0x0000
619193240Ssam#define HostCmd_CAPINFO_ESS                    0x0001
620193240Ssam#define HostCmd_CAPINFO_IBSS                   0x0002
621193240Ssam#define HostCmd_CAPINFO_CF_POLLABLE            0x0004
622193240Ssam#define HostCmd_CAPINFO_CF_REQUEST             0x0008
623193240Ssam#define HostCmd_CAPINFO_PRIVACY                0x0010
624193240Ssam#define HostCmd_CAPINFO_SHORT_PREAMBLE         0x0020
625193240Ssam#define HostCmd_CAPINFO_PBCC                   0x0040
626193240Ssam#define HostCmd_CAPINFO_CHANNEL_AGILITY        0x0080
627193240Ssam#define HostCmd_CAPINFO_SHORT_SLOT             0x0400
628193240Ssam#define HostCmd_CAPINFO_DSSS_OFDM              0x2000
629193240Ssam
630193240Ssamtypedef struct {
631193240Ssam    FWCmdHdr    CmdHdr;
632193240Ssam    StartCmd_t  StartCmd;
633193240Ssam} __packed HostCmd_DS_AP_BEACON;
634193240Ssam
635193240Ssamtypedef struct {
636193240Ssam    FWCmdHdr    CmdHdr;
637193240Ssam    uint16_t	FrmBodyLen;
638193240Ssam    uint8_t	FrmBody[1];		/* NB: variable length */
639193240Ssam} __packed HostCmd_DS_SET_BEACON;
640193240Ssam
641193240Ssam//          Define data structure for HostCmd_CMD_MAC_MULTICAST_ADR
642193240Ssamtypedef struct {
643193240Ssam   FWCmdHdr    CmdHdr;
644193240Ssam   uint16_t      Action;
645193240Ssam   uint16_t      NumOfAdrs;
646193240Ssam#define	MWL_HAL_MCAST_MAX	32
647193240Ssam   uint8_t       MACList[6*32];
648193240Ssam} __packed HostCmd_DS_MAC_MULTICAST_ADR;
649193240Ssam
650193240Ssam// Indicate to FW the current state of AP ERP info
651193240Ssamtypedef struct {
652193240Ssam   FWCmdHdr    CmdHdr;
653193240Ssam   uint32_t      GProtectFlag;
654193240Ssam} __packed HostCmd_FW_SET_G_PROTECT_FLAG;
655193240Ssam
656193240Ssamtypedef struct {
657193240Ssam   FWCmdHdr    CmdHdr;
658193240Ssam} __packed HostCmd_FW_SET_INFRA_MODE;
659193240Ssam
660193240Ssam//          Define data structure for HostCmd_CMD_802_11_RF_CHANNEL
661193240Ssamtypedef struct {
662193240Ssam   FWCmdHdr    CmdHdr;
663193240Ssam   uint16_t      Action;
664193240Ssam   uint8_t       CurrentChannel;	/* channel # */
665193240Ssam   uint32_t  	ChannelFlags;		/* see below */
666193240Ssam} __packed HostCmd_FW_SET_RF_CHANNEL;
667193240Ssam
668193240Ssam/* bits 0-5 specify frequency band */
669193240Ssam#define FREQ_BAND_2DOT4GHZ	0x0001
670193240Ssam#define FREQ_BAND_4DOT9GHZ	0x0002	/* XXX not implemented */
671193240Ssam#define FREQ_BAND_5GHZ      	0x0004
672193240Ssam#define FREQ_BAND_5DOT2GHZ	0x0008 	/* XXX not implemented */
673193240Ssam/* bits 6-10 specify channel width */
674193240Ssam#define CH_AUTO_WIDTH  		0x0000	/* XXX not used? */
675193240Ssam#define CH_10_MHz_WIDTH  	0x0040
676193240Ssam#define CH_20_MHz_WIDTH  	0x0080
677193240Ssam#define CH_40_MHz_WIDTH  	0x0100
678193240Ssam/* bits 11-12 specify extension channel */
679193240Ssam#define EXT_CH_NONE		0x0000	/* no extension channel */
680193240Ssam#define EXT_CH_ABOVE_CTRL_CH 	0x0800	/* extension channel above */
681193240Ssam#define EXT_CH_AUTO		0x1000	/* XXX not used? */
682193240Ssam#define EXT_CH_BELOW_CTRL_CH 	0x1800	/* extension channel below */
683193240Ssam/* bits 13-31 are reserved */
684193240Ssam
685193240Ssam#define FIXED_RATE_WITH_AUTO_RATE_DROP           0
686193240Ssam#define FIXED_RATE_WITHOUT_AUTORATE_DROP        1
687193240Ssam
688193240Ssam#define LEGACY_RATE_TYPE   0
689193240Ssam#define HT_RATE_TYPE  	1
690193240Ssam
691193240Ssam#define RETRY_COUNT_VALID   0
692193240Ssam#define RETRY_COUNT_INVALID     1
693193240Ssam
694193240Ssamtypedef  struct {
695193240Ssam    							// lower rate after the retry count
696193240Ssam    uint32_t   FixRateType;	//0: legacy, 1: HT
697193240Ssam    uint32_t   RetryCountValid; //0: retry count is not valid, 1: use retry count specified
698193240Ssam} __packed FIX_RATE_FLAG;
699193240Ssam
700193240Ssamtypedef  struct {
701193240Ssam    FIX_RATE_FLAG FixRateTypeFlags;
702193240Ssam    uint32_t 	FixedRate;	// legacy rate(not index) or an MCS code.
703193240Ssam    uint32_t	RetryCount;
704193240Ssam} __packed FIXED_RATE_ENTRY;
705193240Ssam
706193240Ssamtypedef  struct {
707193240Ssam    FWCmdHdr	CmdHdr;
708193240Ssam    uint32_t    Action;	//HostCmd_ACT_GEN_GET		0x0000
709193240Ssam			//HostCmd_ACT_GEN_SET 		0x0001
710193240Ssam			//HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002
711193240Ssam    uint32_t   	AllowRateDrop;  // use fixed rate specified but firmware can drop to
712193240Ssam    uint32_t	EntryCount;
713193240Ssam    FIXED_RATE_ENTRY FixedRateTable[4];
714193240Ssam    uint8_t	MulticastRate;
715193240Ssam    uint8_t	MultiRateTxType;
716193240Ssam    uint8_t	ManagementRate;
717193240Ssam} __packed HostCmd_FW_USE_FIXED_RATE;
718193240Ssam
719193240Ssamtypedef struct {
720193240Ssam    uint32_t   	AllowRateDrop;
721193240Ssam    uint32_t	EntryCount;
722193240Ssam    FIXED_RATE_ENTRY FixedRateTable[4];
723193240Ssam} __packed USE_FIXED_RATE_INFO;
724193240Ssam
725193240Ssamtypedef struct {
726193240Ssam   FWCmdHdr    CmdHdr;
727193240Ssam   uint32_t    Action;
728193240Ssam   uint32_t     GIType;
729193240Ssam#define	GI_TYPE_LONG	0x0001
730193240Ssam#define	GI_TYPE_SHORT	0x0002
731193240Ssam} __packed HostCmd_FW_HT_GUARD_INTERVAL;
732193240Ssam
733193240Ssamtypedef struct {
734193240Ssam   FWCmdHdr	CmdHdr;
735193240Ssam   uint32_t    	Action;
736193240Ssam   uint8_t	RxAntennaMap;
737193240Ssam   uint8_t	TxAntennaMap;
738193240Ssam} __packed HostCmd_FW_HT_MIMO_CONFIG;
739193240Ssam
740193240Ssamtypedef struct {
741193240Ssam   FWCmdHdr    CmdHdr;
742193240Ssam   uint16_t    Action;
743193240Ssam   uint8_t     Slot;   // Slot=0 if regular, Slot=1 if short.
744193240Ssam} __packed HostCmd_FW_SET_SLOT;
745193240Ssam
746193240Ssam
747193240Ssam//          Define data structure for HostCmd_CMD_802_11_GET_STAT
748193240Ssamtypedef struct {
749193240Ssam    FWCmdHdr    CmdHdr;
750193240Ssam    uint32_t	TxRetrySuccesses;
751193240Ssam    uint32_t	TxMultipleRetrySuccesses;
752193240Ssam    uint32_t	TxFailures;
753193240Ssam    uint32_t	RTSSuccesses;
754193240Ssam    uint32_t	RTSFailures;
755193240Ssam    uint32_t	AckFailures;
756193240Ssam    uint32_t	RxDuplicateFrames;
757193240Ssam    uint32_t	FCSErrorCount;
758193240Ssam    uint32_t	TxWatchDogTimeouts;
759193240Ssam    uint32_t 	RxOverflows;		//used
760193240Ssam    uint32_t 	RxFragErrors;		//used
761193240Ssam    uint32_t 	RxMemErrors;		//used
762193240Ssam    uint32_t 	PointerErrors;		//used
763193240Ssam    uint32_t 	TxUnderflows;		//used
764193240Ssam    uint32_t 	TxDone;
765193240Ssam    uint32_t 	TxDoneBufTryPut;
766193240Ssam    uint32_t 	TxDoneBufPut;
767193240Ssam    uint32_t 	Wait4TxBuf;		// Put size of requested buffer in here
768193240Ssam    uint32_t 	TxAttempts;
769193240Ssam    uint32_t 	TxSuccesses;
770193240Ssam    uint32_t 	TxFragments;
771193240Ssam    uint32_t 	TxMulticasts;
772193240Ssam    uint32_t 	RxNonCtlPkts;
773193240Ssam    uint32_t 	RxMulticasts;
774193240Ssam    uint32_t 	RxUndecryptableFrames;
775193240Ssam    uint32_t 	RxICVErrors;
776193240Ssam    uint32_t 	RxExcludedFrames;
777193240Ssam} __packed HostCmd_DS_802_11_GET_STAT;
778193240Ssam
779193240Ssam
780193240Ssam//          Define data structure for HostCmd_CMD_MAC_REG_ACCESS
781193240Ssamtypedef struct {
782193240Ssam   FWCmdHdr    CmdHdr;
783193240Ssam   uint16_t      Action;
784193240Ssam   uint16_t      Offset;
785193240Ssam   uint32_t      Value;
786193240Ssam   uint16_t      Reserved;
787193240Ssam} __packed HostCmd_DS_MAC_REG_ACCESS;
788193240Ssam
789193240Ssam//          Define data structure for HostCmd_CMD_BBP_REG_ACCESS
790193240Ssamtypedef struct {
791193240Ssam   FWCmdHdr    CmdHdr;
792193240Ssam   uint16_t      Action;
793193240Ssam   uint16_t      Offset;
794193240Ssam   uint8_t       Value;
795193240Ssam   uint8_t       Reserverd[3];
796193240Ssam} __packed HostCmd_DS_BBP_REG_ACCESS;
797193240Ssam
798193240Ssam//          Define data structure for HostCmd_CMD_RF_REG_ACCESS
799193240Ssamtypedef struct {
800193240Ssam   FWCmdHdr    CmdHdr;
801193240Ssam   uint16_t      Action;
802193240Ssam   uint16_t      Offset;
803193240Ssam   uint8_t       Value;
804193240Ssam   uint8_t       Reserverd[3];
805193240Ssam} __packed HostCmd_DS_RF_REG_ACCESS;
806193240Ssam
807193240Ssam
808193240Ssam//          Define data structure for HostCmd_CMD_802_11_RADIO_CONTROL
809193240Ssamtypedef struct {
810193240Ssam   FWCmdHdr    CmdHdr;
811193240Ssam   uint16_t      Action;
812193240Ssam   uint16_t      Control;	// @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix
813193240Ssam   uint16_t      RadioOn;
814193240Ssam} __packed HostCmd_DS_802_11_RADIO_CONTROL;
815193240Ssam
816193240Ssam
817193240Ssam#define TX_POWER_LEVEL_TOTAL  8
818193240Ssam//          Define data structure for HostCmd_CMD_802_11_RF_TX_POWER
819193240Ssamtypedef struct {
820193240Ssam   FWCmdHdr    CmdHdr;
821193240Ssam   uint16_t      Action;
822193240Ssam   uint16_t      SupportTxPowerLevel;
823193240Ssam   uint16_t      CurrentTxPowerLevel;
824193240Ssam   uint16_t      Reserved;
825193240Ssam   uint16_t      PowerLevelList[TX_POWER_LEVEL_TOTAL];
826193240Ssam} __packed HostCmd_DS_802_11_RF_TX_POWER;
827193240Ssam
828193240Ssam//          Define data structure for HostCmd_CMD_802_11_RF_ANTENNA
829193240Ssamtypedef struct _HostCmd_DS_802_11_RF_ANTENNA {
830193240Ssam   FWCmdHdr    CmdHdr;
831193240Ssam   uint16_t      Action;
832193240Ssam   uint16_t      AntennaMode;             // Number of antennas or 0xffff(diversity)
833193240Ssam} __packed HostCmd_DS_802_11_RF_ANTENNA;
834193240Ssam
835193240Ssam//          Define data structure for HostCmd_CMD_802_11_PS_MODE
836193240Ssamtypedef struct {
837193240Ssam   FWCmdHdr    CmdHdr;
838193240Ssam   uint16_t      Action;
839193240Ssam   uint16_t      PowerMode;               // CAM, Max.PSP or Fast PSP
840193240Ssam} __packed HostCmd_DS_802_11_PS_MODE;
841193240Ssam
842193240Ssamtypedef struct {
843193240Ssam   FWCmdHdr		CmdHdr;
844193240Ssam   uint16_t		Action;
845193240Ssam   uint16_t		Threshold;
846193240Ssam} __packed HostCmd_DS_802_11_RTS_THSD;
847193240Ssam
848193240Ssam// used for stand alone bssid sets/clears
849193240Ssamtypedef struct {
850193240Ssam   FWCmdHdr    CmdHdr;
851193240Ssam#ifdef MWL_MBSS_SUPPORT
852193240Ssam   uint16_t	 MacType;
853193240Ssam#define	WL_MAC_TYPE_PRIMARY_CLIENT	0
854193240Ssam#define	WL_MAC_TYPE_SECONDARY_CLIENT	1
855193240Ssam#define	WL_MAC_TYPE_PRIMARY_AP		2
856193240Ssam#define	WL_MAC_TYPE_SECONDARY_AP	3
857193240Ssam#endif
858193240Ssam   uint8_t       MacAddr[6];
859193240Ssam} __packed HostCmd_DS_SET_MAC,
860193240Ssam  HostCmd_FW_SET_BSSID,
861193240Ssam  HostCmd_FW_SET_MAC;
862193240Ssam
863193240Ssam// Indicate to FW to send out PS Poll
864193240Ssamtypedef struct {
865193240Ssam   FWCmdHdr    CmdHdr;
866193240Ssam   uint32_t      PSPoll;
867193240Ssam} __packed HostCmd_FW_TX_POLL;
868193240Ssam
869193240Ssam// used for AID sets/clears
870193240Ssamtypedef struct {
871193240Ssam   FWCmdHdr    CmdHdr;
872193240Ssam   uint16_t      AssocID;
873193240Ssam   uint8_t       MacAddr[6]; //AP's Mac Address(BSSID)
874193240Ssam   uint32_t      GProtection;
875193240Ssam   uint8_t       ApRates[ RATE_INDEX_MAX_ARRAY];
876193240Ssam} __packed HostCmd_FW_SET_AID;
877193240Ssam
878193240Ssamtypedef struct {
879193240Ssam   uint32_t	LegacyRateBitMap;
880193240Ssam   uint32_t	HTRateBitMap;
881193240Ssam   uint16_t	CapInfo;
882193240Ssam   uint16_t	HTCapabilitiesInfo;
883193240Ssam   uint8_t	MacHTParamInfo;
884193240Ssam   uint8_t	Rev;
885193240Ssam   struct {
886193240Ssam	uint8_t	ControlChan;
887193240Ssam	uint8_t	AddChan;
888193240Ssam	uint16_t OpMode;
889193240Ssam	uint16_t stbc;
890193240Ssam   } __packed AddHtInfo;
891193240Ssam} __packed PeerInfo_t;
892193240Ssam
893193240Ssamtypedef struct {
894193240Ssam   FWCmdHdr    CmdHdr;
895193240Ssam   uint16_t      AID;
896193240Ssam   uint8_t       MacAddr[6];
897193240Ssam   uint16_t      StnId;
898193240Ssam   uint16_t      Action;
899193240Ssam   uint16_t      Reserved;
900193240Ssam   PeerInfo_t	 PeerInfo;
901193240Ssam   uint8_t       Qosinfo;
902193240Ssam   uint8_t       isQosSta;
903195171Ssam   uint32_t      FwStaPtr;
904193240Ssam} __packed HostCmd_FW_SET_NEW_STN;
905193240Ssam
906193240Ssamtypedef struct {
907193240Ssam   FWCmdHdr    CmdHdr;
908193240Ssam   uint8_t           tick;
909193240Ssam} __packed HostCmd_FW_SET_KEEP_ALIVE_TICK;
910193240Ssam
911193240Ssamtypedef struct {
912193240Ssam   FWCmdHdr    CmdHdr;
913193240Ssam   uint8_t           QNum;
914193240Ssam} __packed HostCmd_FW_SET_RIFS;
915193240Ssam
916193240Ssamtypedef struct {
917193240Ssam   FWCmdHdr    CmdHdr;
918193240Ssam   uint8_t	ApMode;
919193240Ssam} __packed HostCmd_FW_SET_APMODE;
920193240Ssam
921193240Ssamtypedef struct {
922193240Ssam    FWCmdHdr    CmdHdr;
923193240Ssam    uint16_t Action;			// see following
924193240Ssam    uint16_t RadarTypeCode;
925193240Ssam} __packed HostCmd_802_11h_Detect_Radar;
926193240Ssam
927193240Ssam#define DR_DFS_DISABLE				0
928193240Ssam#define DR_CHK_CHANNEL_AVAILABLE_START		1
929193240Ssam#define DR_CHK_CHANNEL_AVAILABLE_STOP		2
930193240Ssam#define DR_IN_SERVICE_MONITOR_START		3
931193240Ssam
932193240Ssam//New Structure for Update Tim 30/9/2003
933193240Ssamtypedef	struct	{
934193240Ssam   FWCmdHdr    CmdHdr;
935193240Ssam   uint16_t	   Aid;
936193240Ssam   uint32_t      Set;
937193240Ssam} __packed HostCmd_UpdateTIM;
938193240Ssam
939193240Ssamtypedef struct {
940193240Ssam    FWCmdHdr	CmdHdr;
941193240Ssam    uint32_t    SsidBroadcastEnable;
942193240Ssam} __packed HostCmd_SSID_BROADCAST;
943193240Ssam
944193240Ssamtypedef struct {
945193240Ssam    FWCmdHdr	CmdHdr;
946193240Ssam    uint32_t    WdsEnable;
947193240Ssam} __packed HostCmd_WDS;
948193240Ssam
949193240Ssamtypedef struct {
950193240Ssam    FWCmdHdr    CmdHdr;
951193240Ssam    uint32_t    Next11hChannel;
952193240Ssam    uint32_t    Mode;
953193240Ssam    uint32_t    InitialCount;
954193240Ssam	uint32_t ChannelFlags ;
955193240Ssam} __packed HostCmd_SET_SWITCH_CHANNEL;
956193240Ssam
957193240Ssamtypedef struct {
958193240Ssam    FWCmdHdr    CmdHdr;
959193240Ssam    uint32_t   	SpectrumMgmt;
960193240Ssam} __packed HostCmd_SET_SPECTRUM_MGMT;
961193240Ssam
962193240Ssamtypedef struct {
963193240Ssam    FWCmdHdr    CmdHdr;
964193240Ssam    int32_t    	PowerConstraint;
965193240Ssam} __packed HostCmd_SET_POWER_CONSTRAINT;
966193240Ssam
967193240Ssamtypedef  struct {
968193240Ssam    uint8_t FirstChannelNo;
969193240Ssam    uint8_t NoofChannel;
970193240Ssam    uint8_t MaxTransmitPw;
971193240Ssam} __packed DomainChannelEntry;
972193240Ssam
973193240Ssamtypedef  struct {
974193240Ssam    uint8_t CountryString[3];
975193240Ssam    uint8_t GChannelLen;
976193240Ssam    DomainChannelEntry DomainEntryG[1]; /** Assume only 1 G zone **/
977193240Ssam    uint8_t AChannelLen;
978193240Ssam    DomainChannelEntry DomainEntryA[20]; /** Assume max of 5 A zone **/
979193240Ssam} __packed DomainCountryInfo;
980193240Ssam
981193240Ssamtypedef struct {
982193240Ssam    FWCmdHdr    CmdHdr;
983193240Ssam    uint32_t	Action ; // 0 -> unset, 1 ->set
984193240Ssam    DomainCountryInfo DomainInfo ;
985193240Ssam} __packed HostCmd_SET_COUNTRY_INFO;
986193240Ssam
987193240Ssamtypedef struct {
988193240Ssam	FWCmdHdr    CmdHdr;
989193240Ssam	uint16_t    regionCode ;
990193240Ssam} __packed HostCmd_SET_REGIONCODE_INFO;
991193240Ssam
992193240Ssam// for HostCmd_CMD_SET_WMM_MODE
993193240Ssamtypedef struct {
994193240Ssam    FWCmdHdr    CmdHdr;
995193240Ssam    uint16_t    Action;  // 0->unset, 1->set
996193240Ssam} __packed HostCmd_FW_SetWMMMode;
997193240Ssam
998193240Ssamtypedef struct {
999193240Ssam    FWCmdHdr    CmdHdr;
1000193240Ssam    uint16_t    Action;  // 0->unset, 1->set
1001193240Ssam    uint16_t    IeListLen;
1002193240Ssam    uint8_t     IeList[200];
1003193240Ssam} __packed HostCmd_FW_SetIEs;
1004193240Ssam
1005193240Ssam#define EDCA_PARAM_SIZE				18
1006193240Ssam#define BA_PARAM_SIZE				2
1007193240Ssam
1008193240Ssamtypedef struct {
1009193240Ssam    FWCmdHdr    CmdHdr;
1010193240Ssam    uint16_t	Action;   //0 = get all, 0x1 =set CWMin/Max,  0x2 = set TXOP , 0x4 =set AIFSN
1011193240Ssam    uint16_t	TxOP;     // in unit of 32 us
1012193240Ssam    uint32_t	CWMax;    // 0~15
1013193240Ssam    uint32_t	CWMin;    // 0~15
1014193240Ssam    uint8_t	AIFSN;
1015193240Ssam    uint8_t	TxQNum;   // Tx Queue number.
1016193240Ssam} __packed HostCmd_FW_SET_EDCA_PARAMS;
1017193240Ssam
1018193240Ssam/******************************************************************************
1019193240Ssam	@HWENCR@
1020193240Ssam	Hardware Encryption related data structures and constant definitions.
1021193240Ssam	Note that all related changes are marked with the @HWENCR@ tag.
1022193240Ssam*******************************************************************************/
1023193240Ssam
1024193240Ssam#define MAX_ENCR_KEY_LENGTH	16	/* max 128 bits - depends on type */
1025193240Ssam#define MIC_KEY_LENGTH		8	/* size of Tx/Rx MIC key - 8 bytes*/
1026193240Ssam
1027193240Ssam#define ENCR_KEY_TYPE_ID_WEP	0x00	/* Key type is WEP		*/
1028193240Ssam#define ENCR_KEY_TYPE_ID_TKIP	0x01	/* Key type is TKIP		*/
1029193240Ssam#define ENCR_KEY_TYPE_ID_AES	0x02	/* Key type is AES-CCMP	*/
1030193240Ssam
1031193240Ssam/* flags used in structure - same as driver EKF_XXX flags */
1032193240Ssam#define ENCR_KEY_FLAG_INUSE	0x00000001	/* indicate key is in use */
1033193240Ssam#define ENCR_KEY_FLAG_RXGROUPKEY 0x00000002	/* Group key for RX only */
1034193240Ssam#define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004	/* Group key for TX */
1035193240Ssam#define ENCR_KEY_FLAG_PAIRWISE	0x00000008	/* pairwise */
1036193240Ssam#define ENCR_KEY_FLAG_RXONLY	0x00000010	/* only used for RX */
1037193240Ssam// These flags are new additions - for hardware encryption commands only.
1038193240Ssam#define ENCR_KEY_FLAG_AUTHENTICATOR	0x00000020	/* Key is for Authenticator */
1039193240Ssam#define ENCR_KEY_FLAG_TSC_VALID	0x00000040	/* Sequence counters valid */
1040193240Ssam#define ENCR_KEY_FLAG_WEP_TXKEY	0x01000000	/* Tx key for WEP */
1041193240Ssam#define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000	/* Tx/Rx MIC keys are valid */
1042193240Ssam
1043193240Ssam/*
1044193240Ssam	UPDATE_ENCRYPTION command action type.
1045193240Ssam*/
1046193240Ssamtypedef enum {
1047193240Ssam	// request to enable/disable HW encryption
1048193240Ssam	EncrActionEnableHWEncryption,
1049193240Ssam	// request to set encryption key
1050193240Ssam	EncrActionTypeSetKey,
1051193240Ssam	// request to remove one or more keys
1052193240Ssam	EncrActionTypeRemoveKey,
1053193240Ssam	EncrActionTypeSetGroupKey
1054193240Ssam} ENCR_ACTION_TYPE;
1055193240Ssam
1056193240Ssam/*
1057193240Ssam	Key material definitions (for WEP, TKIP, & AES-CCMP)
1058193240Ssam*/
1059193240Ssam
1060193240Ssam/*
1061193240Ssam	WEP Key material definition
1062193240Ssam	----------------------------
1063193240Ssam	WEPKey	--> An array of 'MAX_ENCR_KEY_LENGTH' bytes.
1064193240Ssam				Note that we do not support 152bit WEP keys
1065193240Ssam*/
1066193240Ssamtypedef struct {
1067193240Ssam    // WEP key material (max 128bit)
1068193240Ssam    uint8_t   KeyMaterial[ MAX_ENCR_KEY_LENGTH ];
1069193240Ssam} __packed WEP_TYPE_KEY;
1070193240Ssam
1071193240Ssam/*
1072193240Ssam	TKIP Key material definition
1073193240Ssam	----------------------------
1074193240Ssam	This structure defines TKIP key material. Note that
1075193240Ssam	the TxMicKey and RxMicKey may or may not be valid.
1076193240Ssam*/
1077193240Ssam/* TKIP Sequence counter - 24 bits */
1078193240Ssam/* Incremented on each fragment MPDU */
1079193240Ssamtypedef struct {
1080193240Ssam    uint16_t low;
1081193240Ssam    uint32_t high;
1082193240Ssam} __packed ENCR_TKIPSEQCNT;
1083193240Ssam
1084193240Ssamtypedef struct {
1085193240Ssam    // TKIP Key material. Key type (group or pairwise key) is
1086193240Ssam    // determined by flags in KEY_PARAM_SET structure.
1087193240Ssam    uint8_t		KeyMaterial[ MAX_ENCR_KEY_LENGTH ];
1088193240Ssam    uint8_t		TkipTxMicKey[ MIC_KEY_LENGTH ];
1089193240Ssam    uint8_t		TkipRxMicKey[ MIC_KEY_LENGTH ];
1090193240Ssam    ENCR_TKIPSEQCNT	TkipRsc;
1091193240Ssam    ENCR_TKIPSEQCNT	TkipTsc;
1092193240Ssam} __packed TKIP_TYPE_KEY;
1093193240Ssam
1094193240Ssam/*
1095193240Ssam	AES-CCMP Key material definition
1096193240Ssam	--------------------------------
1097193240Ssam	This structure defines AES-CCMP key material.
1098193240Ssam*/
1099193240Ssamtypedef struct {
1100193240Ssam    // AES Key material
1101193240Ssam    uint8_t   KeyMaterial[ MAX_ENCR_KEY_LENGTH ];
1102193240Ssam} __packed AES_TYPE_KEY;
1103193240Ssam
1104193240Ssam/*
1105193240Ssam	Encryption key definition.
1106193240Ssam	--------------------------
1107193240Ssam	This structure provides all required/essential
1108193240Ssam	information about the key being set/removed.
1109193240Ssam*/
1110193240Ssamtypedef struct {
1111193240Ssam    uint16_t  Length;		// Total length of this structure
1112193240Ssam    uint16_t  KeyTypeId;	// Key type - WEP, TKIP or AES-CCMP.
1113193240Ssam    uint32_t  KeyInfo;		// key flags (ENCR_KEY_FLAG_XXX_
1114193240Ssam    uint32_t  KeyIndex; 	// For WEP only - actual key index
1115193240Ssam    uint16_t  KeyLen;		// Size of the key
1116193240Ssam    union {			// Key material (variable size array)
1117193240Ssam	WEP_TYPE_KEY	WepKey;
1118193240Ssam	TKIP_TYPE_KEY	TkipKey;
1119193240Ssam	AES_TYPE_KEY	AesKey;
1120193240Ssam    }__packed Key;
1121193240Ssam#ifdef MWL_MBSS_SUPPORT
1122193240Ssam    uint8_t   Macaddr[6];
1123193240Ssam#endif
1124193240Ssam} __packed KEY_PARAM_SET;
1125193240Ssam
1126193240Ssam/*
1127193240Ssam	HostCmd_FW_UPDATE_ENCRYPTION
1128193240Ssam	----------------------------
1129193240Ssam	Define data structure for updating firmware encryption keys.
1130193240Ssam
1131193240Ssam*/
1132193240Ssamtypedef struct {
1133193240Ssam    FWCmdHdr    CmdHdr;
1134193240Ssam    uint32_t	ActionType;		// ENCR_ACTION_TYPE
1135193240Ssam    uint32_t	DataLength;		// size of the data buffer attached.
1136193240Ssam#ifdef MWL_MBSS_SUPPORT
1137193240Ssam    uint8_t	macaddr[6];
1138193240Ssam#endif
1139193240Ssam    uint8_t	ActionData[1];
1140193240Ssam} __packed HostCmd_FW_UPDATE_ENCRYPTION;
1141193240Ssam
1142193240Ssam
1143193240Ssamtypedef struct {
1144193240Ssam    FWCmdHdr    CmdHdr;
1145193240Ssam    uint32_t	ActionType;		// ENCR_ACTION_TYPE
1146193240Ssam    uint32_t	DataLength;		// size of the data buffer attached.
1147193240Ssam    KEY_PARAM_SET KeyParam;
1148193240Ssam#ifndef MWL_MBSS_SUPPORT
1149193240Ssam    uint8_t     Macaddr[8];		/* XXX? */
1150193240Ssam#endif
1151193240Ssam} __packed HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY;
1152193240Ssam
1153193240Ssamtypedef struct {
1154193240Ssam	// Rate flags - see above.
1155193240Ssam	uint32_t	Flags;
1156193240Ssam	// Rate in 500Kbps units.
1157193240Ssam	uint8_t		RateKbps;
1158193240Ssam	// 802.11 rate to conversion table index value.
1159193240Ssam	// This is the value required by the firmware/hardware.
1160193240Ssam	uint16_t	RateCodeToIndex;
1161193240Ssam}__packed RATE_INFO;
1162193240Ssam
1163193240Ssam/*
1164193240Ssam	UPDATE_STADB command action type.
1165193240Ssam*/
1166193240Ssamtypedef enum {
1167193240Ssam	// request to add entry to stainfo db
1168193240Ssam	StaInfoDbActionAddEntry,
1169193240Ssam	// request to modify peer entry
1170193240Ssam	StaInfoDbActionModifyEntry,
1171193240Ssam	// request to remove peer from stainfo db
1172193240Ssam	StaInfoDbActionRemoveEntry
1173193240Ssam}__packed STADB_ACTION_TYPE;
1174193240Ssam
1175193240Ssam/*
1176193240Ssam	@11E-BA@
1177193240Ssam	802.11e/WMM Related command(s)/data structures
1178193240Ssam*/
1179193240Ssam
1180193240Ssam// Flag to indicate if the stream is an immediate block ack stream.
1181193240Ssam// if this bit is not set, the stream is delayed block ack stream.
1182193240Ssam#define BASTREAM_FLAG_DELAYED_TYPE		0x00
1183193240Ssam#define BASTREAM_FLAG_IMMEDIATE_TYPE		0x01
1184193240Ssam
1185193240Ssam// Flag to indicate the direction of the stream (upstream/downstream).
1186193240Ssam// If this bit is not set, the direction is downstream.
1187193240Ssam#define BASTREAM_FLAG_DIRECTION_UPSTREAM	0x00
1188193240Ssam#define BASTREAM_FLAG_DIRECTION_DOWNSTREAM	0x02
1189193240Ssam#define BASTREAM_FLAG_DIRECTION_DLP		0x04
1190193240Ssam#define BASTREAM_FLAG_DIRECTION_BOTH		0x06
1191193240Ssam
1192193240Ssamtypedef enum {
1193193240Ssam	BaCreateStream,
1194193240Ssam	BaUpdateStream,
1195193240Ssam	BaDestroyStream,
1196193240Ssam	BaFlushStream,
1197193240Ssam	BaCheckCreateStream
1198193240Ssam} BASTREAM_ACTION_TYPE;
1199193240Ssam
1200193240Ssamtypedef struct {
1201193240Ssam	uint32_t	Context;
1202193240Ssam} __packed BASTREAM_CONTEXT;
1203193240Ssam
1204193240Ssam// parameters for block ack creation
1205193240Ssamtypedef struct {
1206193240Ssam	// BA Creation flags - see above
1207193240Ssam	uint32_t	Flags;
1208193240Ssam	// idle threshold
1209193240Ssam	uint32_t	IdleThrs;
1210193240Ssam	// block ack transmit threshold (after how many pkts should we send BAR?)
1211193240Ssam	uint32_t	BarThrs;
1212193240Ssam	// receiver window size
1213193240Ssam	uint32_t	WindowSize;
1214193240Ssam	// MAC Address of the BA partner
1215193240Ssam	uint8_t		PeerMacAddr[6];
1216193240Ssam	// Dialog Token
1217193240Ssam	uint8_t		DialogToken;
1218193240Ssam	//TID for the traffic stream in this BA
1219193240Ssam	uint8_t		Tid;
1220193240Ssam	// shared memory queue ID (not sure if this is required)
1221193240Ssam	uint8_t		QueueId;
1222193240Ssam	uint8_t         ParamInfo;
1223193240Ssam	// returned by firmware - firmware context pointer.
1224193240Ssam	// this context pointer will be passed to firmware for all future commands.
1225193240Ssam	BASTREAM_CONTEXT FwBaContext;
1226193240Ssam	uint8_t		ResetSeqNo;  /** 0 or 1**/
1227193240Ssam	uint16_t	StartSeqNo;
1228195171Ssam
1229195171Ssam	// proxy sta MAC Address
1230195171Ssam	uint8_t		StaSrcMacAddr[6];
1231193240Ssam}__packed BASTREAM_CREATE_STREAM;
1232193240Ssam
1233193240Ssam// new transmit sequence number information
1234193240Ssamtypedef struct {
1235193240Ssam	// BA flags - see above
1236193240Ssam	uint32_t	Flags;
1237193240Ssam	// returned by firmware in the create ba stream response
1238193240Ssam	BASTREAM_CONTEXT FwBaContext;
1239193240Ssam	// new sequence number for this block ack stream
1240193240Ssam	uint16_t			 BaSeqNum;
1241193240Ssam}__packed BASTREAM_UPDATE_STREAM;
1242193240Ssam
1243193240Ssamtypedef struct {
1244193240Ssam	// BA Stream flags
1245193240Ssam	uint32_t	 Flags;
1246193240Ssam	// returned by firmware in the create ba stream response
1247193240Ssam	BASTREAM_CONTEXT FwBaContext;
1248193240Ssam}__packed BASTREAM_STREAM_INFO;
1249193240Ssam
1250193240Ssam//Command to create/destroy block ACK
1251193240Ssamtypedef struct {
1252193240Ssam	FWCmdHdr	CmdHdr;
1253193240Ssam	uint32_t	ActionType;
1254193240Ssam	union
1255193240Ssam	{
1256193240Ssam		// information required to create BA Stream...
1257193240Ssam		BASTREAM_CREATE_STREAM	CreateParams;
1258193240Ssam		// update starting/new sequence number etc.
1259193240Ssam		BASTREAM_UPDATE_STREAM	UpdtSeqNum;
1260193240Ssam		// destroy an existing stream...
1261193240Ssam		BASTREAM_STREAM_INFO	DestroyParams;
1262193240Ssam		// destroy an existing stream...
1263193240Ssam		BASTREAM_STREAM_INFO	FlushParams;
1264193240Ssam	}__packed BaInfo;
1265193240Ssam}__packed HostCmd_FW_BASTREAM;
1266193240Ssam
1267193240Ssam//          Define data structure for HostCmd_CMD_GET_WATCHDOG_BITMAP
1268193240Ssamtypedef struct {
1269193240Ssam   FWCmdHdr	CmdHdr;
1270193240Ssam   uint8_t	Watchdogbitmap;		// for SW/BA
1271193240Ssam} __packed HostCmd_FW_GET_WATCHDOG_BITMAP;
1272193240Ssam
1273193240Ssam
1274193240Ssam
1275193240Ssam//          Define data structure for HostCmd_CMD_SET_REGION_POWER
1276193240Ssamtypedef struct {
1277193240Ssam   FWCmdHdr    CmdHdr;
1278193240Ssam   uint16_t    MaxPowerLevel;
1279193240Ssam   uint16_t    Reserved;
1280193240Ssam} __packed HostCmd_DS_SET_REGION_POWER;
1281193240Ssam
1282193240Ssam//          Define data structure for HostCmd_CMD_SET_RATE_ADAPT_MODE
1283193240Ssamtypedef struct {
1284193240Ssam   FWCmdHdr	CmdHdr;
1285193240Ssam   uint16_t	Action;
1286193240Ssam   uint16_t	RateAdaptMode;
1287193240Ssam} __packed HostCmd_DS_SET_RATE_ADAPT_MODE;
1288193240Ssam
1289193240Ssam//          Define data structure for HostCmd_CMD_SET_LINKADAPT_CS_MODE
1290193240Ssamtypedef struct {
1291193240Ssam   FWCmdHdr	CmdHdr;
1292193240Ssam   uint16_t	Action;
1293193240Ssam   uint16_t	CSMode;
1294193240Ssam} __packed HostCmd_DS_SET_LINKADAPT_CS_MODE;
1295193240Ssam
1296193240Ssamtypedef struct {
1297193240Ssam   FWCmdHdr    CmdHdr;
1298193240Ssam   uint32_t     NProtectFlag;
1299193240Ssam} __packed HostCmd_FW_SET_N_PROTECT_FLAG;
1300193240Ssam
1301193240Ssamtypedef struct {
1302193240Ssam   FWCmdHdr    CmdHdr;
1303193240Ssam   uint8_t       NProtectOpMode;
1304193240Ssam} __packed HostCmd_FW_SET_N_PROTECT_OPMODE;
1305193240Ssam
1306193240Ssamtypedef struct {
1307193240Ssam   FWCmdHdr    CmdHdr;
1308193240Ssam   uint8_t       OptLevel;
1309193240Ssam} __packed HostCmd_FW_SET_OPTIMIZATION_LEVEL;
1310193240Ssam
1311193240Ssamtypedef struct {
1312193240Ssam   FWCmdHdr    CmdHdr;
1313193240Ssam   uint8_t     annex;
1314193240Ssam   uint8_t     index;
1315193240Ssam   uint8_t     len;
1316193240Ssam   uint8_t     Reserverd;
1317193240Ssam#define CAL_TBL_SIZE        160
1318193240Ssam   uint8_t     calTbl[CAL_TBL_SIZE];
1319193240Ssam} __packed HostCmd_FW_GET_CALTABLE;
1320193240Ssam
1321193240Ssamtypedef struct {
1322193240Ssam   FWCmdHdr    CmdHdr;
1323193240Ssam   uint8_t     Addr[6];
1324193240Ssam   uint8_t     Enable;
1325193240Ssam   uint8_t     Mode;
1326193240Ssam} __packed HostCmd_FW_SET_MIMOPSHT;
1327193240Ssam
1328193240Ssam#define MAX_BEACON_SIZE        1024
1329193240Ssamtypedef struct {
1330193240Ssam   FWCmdHdr    CmdHdr;
1331193240Ssam   uint16_t    Bcnlen;
1332193240Ssam   uint8_t     Reserverd[2];
1333193240Ssam   uint8_t     Bcn[MAX_BEACON_SIZE];
1334193240Ssam} __packed HostCmd_FW_GET_BEACON;
1335193240Ssam
1336193240Ssamtypedef struct {
1337193240Ssam	FWCmdHdr CmdHdr;
1338193240Ssam	uint8_t	NumberOfPowersave;
1339193240Ssam	uint8_t	reserved;
1340193240Ssam} __packed HostCmd_SET_POWERSAVESTATION;
1341193240Ssam
1342193240Ssamtypedef struct {
1343193240Ssam	FWCmdHdr CmdHdr;
1344193240Ssam	uint16_t Aid;
1345193240Ssam	uint32_t Set;
1346193240Ssam	uint8_t	reserved;
1347193240Ssam} __packed HostCmd_SET_TIM;
1348193240Ssam
1349193240Ssamtypedef struct {
1350193240Ssam	FWCmdHdr CmdHdr;
1351193240Ssam	uint8_t	TrafficMap[251];
1352193240Ssam	uint8_t	reserved;
1353193240Ssam} __packed HostCmd_GET_TIM;
1354193240Ssam
1355193240Ssamtypedef struct {
1356193240Ssam	FWCmdHdr CmdHdr;
1357193240Ssam	uint8_t	MacAddr[6];
1358193240Ssam	uint8_t	TID;
1359193240Ssam	uint16_t SeqNo;
1360193240Ssam	uint8_t	reserved;
1361193240Ssam} __packed HostCmd_GET_SEQNO;
1362195171Ssam
1363195171Ssamtypedef struct {
1364195171Ssam	FWCmdHdr    CmdHdr;
1365195171Ssam	uint32_t    Enable;    //0 -- Disbale. or 1 -- Enable.
1366195171Ssam} __packed HostCmd_DWDS_ENABLE;
1367195171Ssam
1368195171Ssamtypedef struct {
1369195171Ssam	FWCmdHdr    CmdHdr;
1370195171Ssam	uint16_t    Action;  /* 0: Get. 1:Set */
1371195171Ssam	uint32_t    Option;  /* 0: default. 1:Aggressive */
1372195171Ssam	uint32_t    Threshold;  /* Range 0-200, default 8 */
1373195171Ssam}__packed HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE;
1374195171Ssam
1375195171Ssamtypedef struct {
1376195171Ssam	FWCmdHdr    CmdHdr;
1377195171Ssam	uint32_t    Enable; /* 0 -- Disable. or 1 -- Enable */
1378195171Ssam}__packed HostCmd_CFEND_ENABLE;
1379193240Ssam#endif /* _MWL_HALREG_H_ */
1380