1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: releng/11.0/sys/dev/mmc/host/dwmmc_reg.h 287258 2015-08-28 15:27:55Z andrew $ 31 */ 32 33#ifndef DEV_MMC_HOST_DWMMC_REG_H 34#define DEV_MMC_HOST_DWMMC_REG_H 35 36#define SDMMC_CTRL 0x0 /* Control Register */ 37#define SDMMC_CTRL_USE_IDMAC (1 << 25) /* Use Internal DMAC */ 38#define SDMMC_CTRL_DMA_ENABLE (1 << 5) /* */ 39#define SDMMC_CTRL_INT_ENABLE (1 << 4) /* Enable interrupts */ 40#define SDMMC_CTRL_DMA_RESET (1 << 2) /* Reset DMA */ 41#define SDMMC_CTRL_FIFO_RESET (1 << 1) /* Reset FIFO */ 42#define SDMMC_CTRL_RESET (1 << 0) /* Reset SD/MMC controller */ 43#define SDMMC_PWREN 0x4 /* Power Enable Register */ 44#define SDMMC_PWREN_PE (1 << 0) /* Power On */ 45#define SDMMC_CLKDIV 0x8 /* Clock Divider Register */ 46#define SDMMC_CLKSRC 0xC /* SD Clock Source Register */ 47#define SDMMC_CLKENA 0x10 /* Clock Enable Register */ 48#define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */ 49#define SDMMC_CLKENA_CCLK_EN (1 << 0) /* SD/MMC Enable */ 50#define SDMMC_TMOUT 0x14 /* Timeout Register */ 51#define SDMMC_CTYPE 0x18 /* Card Type Register */ 52#define SDMMC_CTYPE_8BIT (1 << 16) 53#define SDMMC_CTYPE_4BIT (1 << 0) 54#define SDMMC_BLKSIZ 0x1C /* Block Size Register */ 55#define SDMMC_BYTCNT 0x20 /* Byte Count Register */ 56#define SDMMC_INTMASK 0x24 /* Interrupt Mask Register */ 57#define SDMMC_INTMASK_SDIO (1 << 16) /* SDIO Interrupt Enable */ 58#define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */ 59#define SDMMC_INTMASK_ACD (1 << 14) /* Auto command done */ 60#define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */ 61#define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */ 62#define SDMMC_INTMASK_FRUN (1 << 11) /* FIFO underrun/overrun err */ 63#define SDMMC_INTMASK_HTO (1 << 10) /* Data starvation by host timeout */ 64#define SDMMC_INTMASK_DRT (1 << 9) /* Data read timeout */ 65#define SDMMC_INTMASK_RTO (1 << 8) /* Response timeout */ 66#define SDMMC_INTMASK_DCRC (1 << 7) /* Data CRC error */ 67#define SDMMC_INTMASK_RCRC (1 << 6) /* Response CRC error */ 68#define SDMMC_INTMASK_RXDR (1 << 5) /* Receive FIFO data request */ 69#define SDMMC_INTMASK_TXDR (1 << 4) /* Transmit FIFO data request */ 70#define SDMMC_INTMASK_DTO (1 << 3) /* Data transfer over */ 71#define SDMMC_INTMASK_CMD_DONE (1 << 2) /* Command done */ 72#define SDMMC_INTMASK_RE (1 << 1) /* Response error */ 73#define SDMMC_INTMASK_CD (1 << 0) /* Card Detected */ 74#define SDMMC_CMDARG 0x28 /* Command Argument Register */ 75#define SDMMC_CMD 0x2C /* Command Register */ 76#define SDMMC_CMD_START (1 << 31) 77#define SDMMC_CMD_USE_HOLD_REG (1 << 29) 78#define SDMMC_CMD_UPD_CLK_ONLY (1 << 21) /* Update clk only */ 79#define SDMMC_CMD_SEND_INIT (1 << 15) /* Send initialization */ 80#define SDMMC_CMD_STOP_ABORT (1 << 14) /* stop current data transfer */ 81#define SDMMC_CMD_WAIT_PRVDATA (1 << 13) /* Wait for prev data transfer completion */ 82#define SDMMC_CMD_SEND_ASTOP (1 << 12) /* Send stop command at end of data tx/rx */ 83#define SDMMC_CMD_MODE_STREAM (1 << 11) /* Stream data transfer */ 84#define SDMMC_CMD_DATA_WRITE (1 << 10) /* Write to card */ 85#define SDMMC_CMD_DATA_EXP (1 << 9) /* Data transfer expected */ 86#define SDMMC_CMD_RESP_CRC (1 << 8) /* Check Response CRC */ 87#define SDMMC_CMD_RESP_LONG (1 << 7) /* Long response expected */ 88#define SDMMC_CMD_RESP_EXP (1 << 6) /* Response expected */ 89#define SDMMC_RESP0 0x30 /* Response Register 0 */ 90#define SDMMC_RESP1 0x34 /* Response Register 1 */ 91#define SDMMC_RESP2 0x38 /* Response Register 2 */ 92#define SDMMC_RESP3 0x3C /* Response Register 3 */ 93#define SDMMC_MINTSTS 0x40 /* Masked Interrupt Status Register */ 94#define SDMMC_RINTSTS 0x44 /* Raw Interrupt Status Register */ 95#define SDMMC_STATUS 0x48 /* Status Register */ 96#define SDMMC_STATUS_DATA_BUSY (1 << 9) /* card_data[0] */ 97#define SDMMC_STATUS_FIFO_FULL (1 << 3) /* FIFO full */ 98#define SDMMC_STATUS_FIFO_EMPTY (1 << 2) /* FIFO empty */ 99#define SDMMC_FIFOTH 0x4C /* FIFO Threshold Watermark Register */ 100#define SDMMC_FIFOTH_MSIZE_S 28 /* Burst size of multiple transaction */ 101#define SDMMC_FIFOTH_RXWMARK_S 16 /* FIFO threshold watermark level */ 102#define SDMMC_FIFOTH_TXWMARK_S 0 /* FIFO threshold watermark level */ 103#define SDMMC_CDETECT 0x50 /* Card Detect Register */ 104#define SDMMC_WRTPRT 0x54 /* Write Protect Register */ 105#define SDMMC_TCBCNT 0x5C /* Transferred CIU Card Byte Count */ 106#define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */ 107#define SDMMC_DEBNCE 0x64 /* Debounce Count Register */ 108#define SDMMC_USRID 0x68 /* User ID Register */ 109#define SDMMC_VERID 0x6C /* Version ID Register */ 110#define SDMMC_HCON 0x70 /* Hardware Configuration Register */ 111#define SDMMC_UHS_REG 0x74 /* UHS-1 Register */ 112#define SDMMC_UHS_REG_DDR (1 << 16) /* DDR mode */ 113#define SDMMC_RST_N 0x78 /* Hardware Reset Register */ 114#define SDMMC_BMOD 0x80 /* Bus Mode Register */ 115#define SDMMC_BMOD_DE (1 << 7) /* IDMAC Enable */ 116#define SDMMC_BMOD_FB (1 << 1) /* AHB Master Fixed Burst */ 117#define SDMMC_BMOD_SWR (1 << 0) /* Reset DMA */ 118#define SDMMC_PLDMND 0x84 /* Poll Demand Register */ 119#define SDMMC_DBADDR 0x88 /* Descriptor List Base Address */ 120#define SDMMC_IDSTS 0x8C /* Internal DMAC Status Register */ 121#define SDMMC_IDINTEN 0x90 /* Internal DMAC Interrupt Enable */ 122#define SDMMC_IDINTEN_AI (1 << 9) /* Abnormal Interrupt Summary */ 123#define SDMMC_IDINTEN_NI (1 << 8) /* Normal Interrupt Summary */ 124#define SDMMC_IDINTEN_CES (1 << 5) /* Card Error Summary */ 125#define SDMMC_IDINTEN_DU (1 << 4) /* Descriptor Unavailable */ 126#define SDMMC_IDINTEN_FBE (1 << 2) /* Fatal Bus Error */ 127#define SDMMC_IDINTEN_RI (1 << 1) /* Receive Interrupt */ 128#define SDMMC_IDINTEN_TI (1 << 0) /* Transmit Interrupt */ 129#define SDMMC_IDINTEN_MASK (SDMMC_IDINTEN_AI | SDMMC_IDINTEN_NI | SDMMC_IDINTEN_CES | \ 130 SDMMC_IDINTEN_DU | SDMMC_IDINTEN_FBE | SDMMC_IDINTEN_RI | \ 131 SDMMC_IDINTEN_TI) 132#define SDMMC_DSCADDR 0x94 /* Current Host Descriptor Address */ 133#define SDMMC_BUFADDR 0x98 /* Current Buffer Descriptor Address */ 134#define SDMMC_CARDTHRCTL 0x100 /* Card Threshold Control Register */ 135#define SDMMC_BACK_END_POWER_R 0x104 /* Back End Power Register */ 136#define SDMMC_DATA 0x200 /* Data FIFO Access */ 137 138/* eMMC */ 139#define EMMCP_MPSBEGIN0 0x1200 /* */ 140#define EMMCP_SEND0 0x1204 /* */ 141#define EMMCP_CTRL0 0x120C /* */ 142#define MPSCTRL_SECURE_READ_BIT (1 << 7) 143#define MPSCTRL_SECURE_WRITE_BIT (1 << 6) 144#define MPSCTRL_NON_SECURE_READ_BIT (1 << 5) 145#define MPSCTRL_NON_SECURE_WRITE_BIT (1 << 4) 146#define MPSCTRL_USE_FUSE_KEY (1 << 3) 147#define MPSCTRL_ECB_MODE (1 << 2) 148#define MPSCTRL_ENCRYPTION (1 << 1) 149#define MPSCTRL_VALID (1 << 0) 150 151/* Platform-specific defines */ 152#define SDMMC_CLKSEL 0x9C 153#define SDMMC_CLKSEL_SAMPLE_SHIFT 0 154#define SDMMC_CLKSEL_DRIVE_SHIFT 16 155#define SDMMC_CLKSEL_DIVIDER_SHIFT 24 156 157#endif /* DEV_MMC_HOST_DWMMC_REG_H */ 158