en.h revision 291932
1290650Shselasky/*- 2290650Shselasky * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: head/sys/dev/mlx5/mlx5_en/en.h 291932 2015-12-07 11:04:50Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef _MLX5_EN_H_ 29290650Shselasky#define _MLX5_EN_H_ 30290650Shselasky 31290650Shselasky#include <linux/kmod.h> 32290650Shselasky#include <linux/page.h> 33290650Shselasky#include <linux/slab.h> 34290650Shselasky#include <linux/if_vlan.h> 35290650Shselasky#include <linux/if_ether.h> 36290650Shselasky#include <linux/vmalloc.h> 37290650Shselasky#include <linux/moduleparam.h> 38290650Shselasky#include <linux/delay.h> 39290650Shselasky#include <linux/netdevice.h> 40290650Shselasky#include <linux/etherdevice.h> 41290650Shselasky 42290650Shselasky#include <netinet/in_systm.h> 43290650Shselasky#include <netinet/in.h> 44290650Shselasky#include <netinet/if_ether.h> 45290650Shselasky#include <netinet/ip.h> 46290650Shselasky#include <netinet/ip6.h> 47290650Shselasky#include <netinet/tcp.h> 48290650Shselasky#include <netinet/tcp_lro.h> 49290650Shselasky#include <netinet/udp.h> 50290650Shselasky#include <net/ethernet.h> 51290650Shselasky#include <sys/buf_ring.h> 52290650Shselasky 53290650Shselasky#include <machine/bus.h> 54290650Shselasky 55290650Shselasky#ifdef HAVE_TURBO_LRO 56290650Shselasky#include "tcp_tlro.h" 57290650Shselasky#endif 58290650Shselasky 59290650Shselasky#include <dev/mlx5/driver.h> 60290650Shselasky#include <dev/mlx5/qp.h> 61290650Shselasky#include <dev/mlx5/cq.h> 62290650Shselasky#include <dev/mlx5/vport.h> 63290650Shselasky 64290650Shselasky#include <dev/mlx5/mlx5_core/wq.h> 65290650Shselasky#include <dev/mlx5/mlx5_core/transobj.h> 66290650Shselasky#include <dev/mlx5/mlx5_core/mlx5_core.h> 67290650Shselasky 68290650Shselasky#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 69290650Shselasky#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 70290650Shselasky#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 71290650Shselasky 72290650Shselasky#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 73290650Shselasky#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 74290650Shselasky#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 75290650Shselasky 76290650Shselasky/* freeBSD HW LRO is limited by 16KB - the size of max mbuf */ 77291070Shselasky#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 78290650Shselasky#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 79291070Shselasky#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 80290650Shselasky#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 81290650Shselasky#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 82290650Shselasky#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 83290650Shselasky#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 84290650Shselasky#define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 85290650Shselasky#define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 86290650Shselasky#define MLX5E_HW2SW_MTU(hwmtu) \ 87290650Shselasky ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 88290650Shselasky#define MLX5E_SW2HW_MTU(swmtu) \ 89290650Shselasky ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 90290650Shselasky#define MLX5E_SW2MB_MTU(swmtu) \ 91290650Shselasky (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 92291070Shselasky#define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 93291070Shselasky#define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 94291070Shselasky * jumbo frames */ 95290650Shselasky 96290650Shselasky#define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 97290650Shselasky#define MLX5E_RX_BUDGET_MAX 256 98290650Shselasky#define MLX5E_SQ_BF_BUDGET 16 99291070Shselasky#define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 100290650Shselasky 101290650Shselasky#define MLX5E_MAX_TX_NUM_TC 8 /* units */ 102290650Shselasky#define MLX5E_MAX_TX_HEADER 128 /* bytes */ 103290650Shselasky#define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 104290650Shselasky#define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 105290650Shselasky#define MLX5E_MAX_TX_MBUF_FRAGS \ 106290650Shselasky ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 107290650Shselasky (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */ 108290650Shselasky#define MLX5E_MAX_TX_INLINE \ 109290650Shselasky (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 110290650Shselasky sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 111290650Shselasky 112290650ShselaskyMALLOC_DECLARE(M_MLX5EN); 113290650Shselasky 114290650Shselaskystruct mlx5_core_dev; 115290650Shselaskystruct mlx5e_cq; 116290650Shselasky 117290650Shselaskytypedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 118290650Shselasky 119290650Shselasky#define MLX5E_STATS_COUNT(a,b,c,d) a 120290650Shselasky#define MLX5E_STATS_VAR(a,b,c,d) b; 121290650Shselasky#define MLX5E_STATS_DESC(a,b,c,d) c, d, 122290650Shselasky 123290650Shselasky#define MLX5E_VPORT_STATS(m) \ 124290650Shselasky /* HW counters */ \ 125290650Shselasky m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 126290650Shselasky m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 127290650Shselasky m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 128290650Shselasky m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 129290650Shselasky m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 130290650Shselasky m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 131290650Shselasky m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 132290650Shselasky m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 133290650Shselasky m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 134290650Shselasky m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 135290650Shselasky m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 136290650Shselasky m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 137290650Shselasky m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 138290650Shselasky m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 139290650Shselasky m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 140290650Shselasky m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 141290650Shselasky m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 142290650Shselasky m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 143290650Shselasky m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 144290650Shselasky m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 145291069Shselasky m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 146290650Shselasky /* SW counters */ \ 147290650Shselasky m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 148290650Shselasky m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 149290650Shselasky m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 150290650Shselasky m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 151290650Shselasky m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 152290650Shselasky m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 153290650Shselasky m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 154290650Shselasky m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 155290650Shselasky m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 156290650Shselasky m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 157290650Shselasky m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 158290650Shselasky m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") 159290650Shselasky 160290650Shselasky#define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 161290650Shselasky 162290650Shselaskystruct mlx5e_vport_stats { 163291070Shselasky struct sysctl_ctx_list ctx; 164290650Shselasky u64 arg [0]; 165290650Shselasky MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 166291069Shselasky u32 rx_out_of_buffer_prev; 167290650Shselasky}; 168290650Shselasky 169290650Shselasky#define MLX5E_PPORT_IEEE802_3_STATS(m) \ 170290650Shselasky m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 171290650Shselasky m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 172290650Shselasky m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 173290650Shselasky m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 174290650Shselasky m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 175290650Shselasky m(+1, u64 octets_received, "octets_received", "Bytes received") \ 176290650Shselasky m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 177290650Shselasky m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 178290650Shselasky m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 179290650Shselasky m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 180290650Shselasky m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 181290650Shselasky m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 182290650Shselasky m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 183290650Shselasky m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 184290650Shselasky m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 185290650Shselasky m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 186290650Shselasky m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 187290650Shselasky m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 188290650Shselasky m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 189290650Shselasky 190290650Shselasky#define MLX5E_PPORT_RFC2819_STATS(m) \ 191290650Shselasky m(+1, u64 drop_events, "drop_events", "Dropped events") \ 192290650Shselasky m(+1, u64 octets, "octets", "Octets") \ 193290650Shselasky m(+1, u64 pkts, "pkts", "Packets") \ 194290650Shselasky m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 195290650Shselasky m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 196290650Shselasky m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 197290650Shselasky m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 198290650Shselasky m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 199290650Shselasky m(+1, u64 fragments, "fragments", "Fragments") \ 200290650Shselasky m(+1, u64 jabbers, "jabbers", "Jabbers") \ 201290650Shselasky m(+1, u64 collisions, "collisions", "Collisions") 202290650Shselasky 203290650Shselasky#define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 204290650Shselasky m(+1, u64 p64octets, "p64octets", "Bytes") \ 205290650Shselasky m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 206290650Shselasky m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 207290650Shselasky m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 208290650Shselasky m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 209290650Shselasky m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 210290650Shselasky m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 211290650Shselasky m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 212290650Shselasky m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 213290650Shselasky m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 214290650Shselasky 215290650Shselasky#define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 216290650Shselasky m(+1, u64 in_octets, "in_octets", "In octets") \ 217290650Shselasky m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 218290650Shselasky m(+1, u64 in_discards, "in_discards", "In discards") \ 219290650Shselasky m(+1, u64 in_errors, "in_errors", "In errors") \ 220290650Shselasky m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 221290650Shselasky m(+1, u64 out_octets, "out_octets", "Out octets") \ 222290650Shselasky m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 223290650Shselasky m(+1, u64 out_discards, "out_discards", "Out discards") \ 224290650Shselasky m(+1, u64 out_errors, "out_errors", "Out errors") \ 225290650Shselasky m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 226290650Shselasky m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 227290650Shselasky m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 228290650Shselasky m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 229290650Shselasky 230291070Shselasky#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 231290650Shselasky m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 232290650Shselasky "Time since the last counters clear event (msec)") \ 233290650Shselasky m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 234290650Shselasky m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 235290650Shselasky m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 236290650Shselasky "Indicates the number of PRBS errors on lane 0") \ 237290650Shselasky m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 238290650Shselasky "Indicates the number of PRBS errors on lane 1") \ 239290650Shselasky m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 240290650Shselasky "Indicates the number of PRBS errors on lane 2") \ 241290650Shselasky m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 242290650Shselasky "Indicates the number of PRBS errors on lane 3") \ 243290650Shselasky m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 244290650Shselasky "FEC correctable block counter lane 0") \ 245290650Shselasky m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 246290650Shselasky "FEC correctable block counter lane 1") \ 247290650Shselasky m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 248290650Shselasky "FEC correctable block counter lane 2") \ 249290650Shselasky m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 250290650Shselasky "FEC correctable block counter lane 3") \ 251290650Shselasky m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 252290650Shselasky "FEC correcable block counter") \ 253290650Shselasky m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 254290650Shselasky "FEC uncorrecable block counter") \ 255290650Shselasky m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 256290650Shselasky "The number of RS-FEC blocks received that had no errors") \ 257290650Shselasky m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 258290650Shselasky "The number of corrected RS-FEC blocks received that had" \ 259290650Shselasky "exactly 1 error symbol") \ 260290650Shselasky m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 261290650Shselasky "Port FEC corrected symbol counter") \ 262290650Shselasky m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 263290650Shselasky "FEC corrected symbol counter lane 0") \ 264290650Shselasky m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 265290650Shselasky "FEC corrected symbol counter lane 1") \ 266290650Shselasky m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 267290650Shselasky "FEC corrected symbol counter lane 2") \ 268290650Shselasky m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 269290650Shselasky "FEC corrected symbol counter lane 3") \ 270290650Shselasky 271290650Shselasky/* 272290650Shselasky * Make sure to update mlx5e_update_pport_counters() 273290650Shselasky * when adding a new MLX5E_PPORT_STATS block 274290650Shselasky */ 275290650Shselasky#define MLX5E_PPORT_STATS(m) \ 276290650Shselasky MLX5E_PPORT_IEEE802_3_STATS(m) \ 277291069Shselasky MLX5E_PPORT_RFC2819_STATS(m) 278290650Shselasky 279290650Shselasky#define MLX5E_PORT_STATS_DEBUG(m) \ 280290650Shselasky MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 281290650Shselasky MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 282290650Shselasky MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) 283290650Shselasky 284290650Shselasky#define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 285290650Shselasky (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 286290650Shselasky#define MLX5E_PPORT_RFC2819_STATS_NUM \ 287290650Shselasky (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 288290650Shselasky#define MLX5E_PPORT_STATS_NUM \ 289290650Shselasky (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 290290650Shselasky 291290650Shselasky#define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 292290650Shselasky (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 293290650Shselasky#define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 294290650Shselasky (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 295291070Shselasky#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 296290650Shselasky (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 297290650Shselasky#define MLX5E_PORT_STATS_DEBUG_NUM \ 298290650Shselasky (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 299290650Shselasky 300290650Shselaskystruct mlx5e_pport_stats { 301291070Shselasky struct sysctl_ctx_list ctx; 302290650Shselasky u64 arg [0]; 303290650Shselasky MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 304290650Shselasky}; 305290650Shselasky 306290650Shselaskystruct mlx5e_port_stats_debug { 307291070Shselasky struct sysctl_ctx_list ctx; 308290650Shselasky u64 arg [0]; 309290650Shselasky MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 310290650Shselasky}; 311290650Shselasky 312290650Shselasky#define MLX5E_RQ_STATS(m) \ 313290650Shselasky m(+1, u64 packets, "packets", "Received packets") \ 314290650Shselasky m(+1, u64 csum_none, "csum_none", "Received packets") \ 315290650Shselasky m(+1, u64 lro_packets, "lro_packets", "Received packets") \ 316290650Shselasky m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \ 317290650Shselasky m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 318290650Shselasky m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 319290650Shselasky m(+1, u64 wqe_err, "wqe_err", "Received packets") 320290650Shselasky 321290650Shselasky#define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 322290650Shselasky 323290650Shselaskystruct mlx5e_rq_stats { 324291070Shselasky struct sysctl_ctx_list ctx; 325290650Shselasky u64 arg [0]; 326290650Shselasky MLX5E_RQ_STATS(MLX5E_STATS_VAR) 327290650Shselasky}; 328290650Shselasky 329290650Shselasky#define MLX5E_SQ_STATS(m) \ 330290650Shselasky m(+1, u64 packets, "packets", "Transmitted packets") \ 331290650Shselasky m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 332290650Shselasky m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 333290650Shselasky m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 334290650Shselasky m(+1, u64 defragged, "defragged", "Transmitted packets") \ 335290650Shselasky m(+1, u64 dropped, "dropped", "Transmitted packets") \ 336290650Shselasky m(+1, u64 nop, "nop", "Transmitted packets") 337290650Shselasky 338290650Shselasky#define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 339290650Shselasky 340290650Shselaskystruct mlx5e_sq_stats { 341291070Shselasky struct sysctl_ctx_list ctx; 342290650Shselasky u64 arg [0]; 343290650Shselasky MLX5E_SQ_STATS(MLX5E_STATS_VAR) 344290650Shselasky}; 345290650Shselasky 346290650Shselaskystruct mlx5e_stats { 347290650Shselasky struct mlx5e_vport_stats vport; 348290650Shselasky struct mlx5e_pport_stats pport; 349290650Shselasky struct mlx5e_port_stats_debug port_stats_debug; 350290650Shselasky}; 351290650Shselasky 352290650Shselaskystruct mlx5e_params { 353290650Shselasky u8 log_sq_size; 354290650Shselasky u8 log_rq_size; 355290650Shselasky u16 num_channels; 356290650Shselasky u8 default_vlan_prio; 357290650Shselasky u8 num_tc; 358290650Shselasky u8 rx_cq_moderation_mode; 359291932Shselasky u8 tx_cq_moderation_mode; 360290650Shselasky u16 rx_cq_moderation_usec; 361290650Shselasky u16 rx_cq_moderation_pkts; 362290650Shselasky u16 tx_cq_moderation_usec; 363290650Shselasky u16 tx_cq_moderation_pkts; 364290650Shselasky u16 min_rx_wqes; 365291070Shselasky bool hw_lro_en; 366291070Shselasky u32 lro_wqe_sz; 367290650Shselasky u16 rx_hash_log_tbl_sz; 368290650Shselasky}; 369290650Shselasky 370290650Shselasky#define MLX5E_PARAMS(m) \ 371290650Shselasky m(+1, u64 tx_pauseframe_control, "tx_pauseframe_control", "Set to enable TX pause frames. Clear to disable.") \ 372290650Shselasky m(+1, u64 rx_pauseframe_control, "rx_pauseframe_control", "Set to enable RX pause frames. Clear to disable.") \ 373290650Shselasky m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 374290650Shselasky m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 375290650Shselasky m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 376290650Shselasky m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 377290650Shselasky m(+1, u64 channels, "channels", "Default number of channels") \ 378290650Shselasky m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 379290650Shselasky m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 380290650Shselasky m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 381290650Shselasky m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 382290650Shselasky m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 383290650Shselasky m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 384290650Shselasky m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 385291932Shselasky m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 386290650Shselasky m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") 387290650Shselasky 388290650Shselasky#define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 389290650Shselasky 390290650Shselaskystruct mlx5e_params_ethtool { 391290650Shselasky u64 arg [0]; 392290650Shselasky MLX5E_PARAMS(MLX5E_STATS_VAR) 393290650Shselasky}; 394290650Shselasky 395290650Shselasky/* EEPROM Standards for plug in modules */ 396290650Shselasky#ifndef MLX5E_ETH_MODULE_SFF_8472 397291070Shselasky#define MLX5E_ETH_MODULE_SFF_8472 0x1 398291070Shselasky#define MLX5E_ETH_MODULE_SFF_8472_LEN 128 399290650Shselasky#endif 400290650Shselasky 401290650Shselasky#ifndef MLX5E_ETH_MODULE_SFF_8636 402291070Shselasky#define MLX5E_ETH_MODULE_SFF_8636 0x2 403291070Shselasky#define MLX5E_ETH_MODULE_SFF_8636_LEN 256 404290650Shselasky#endif 405290650Shselasky 406290650Shselasky#ifndef MLX5E_ETH_MODULE_SFF_8436 407291070Shselasky#define MLX5E_ETH_MODULE_SFF_8436 0x3 408291070Shselasky#define MLX5E_ETH_MODULE_SFF_8436_LEN 256 409290650Shselasky#endif 410290650Shselasky 411290650Shselasky/* EEPROM I2C Addresses */ 412291070Shselasky#define MLX5E_I2C_ADDR_LOW 0x50 413291070Shselasky#define MLX5E_I2C_ADDR_HIGH 0x51 414290650Shselasky 415291070Shselasky#define MLX5E_EEPROM_LOW_PAGE 0x0 416291070Shselasky#define MLX5E_EEPROM_HIGH_PAGE 0x3 417290650Shselasky 418291070Shselasky#define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 419291070Shselasky#define MLX5E_EEPROM_PAGE_LENGTH 256 420290650Shselasky 421291070Shselasky#define MLX5E_EEPROM_INFO_BYTES 0x3 422290650Shselasky 423290650Shselaskystruct mlx5e_cq { 424290650Shselasky /* data path - accessed per cqe */ 425290650Shselasky struct mlx5_cqwq wq; 426290650Shselasky 427290650Shselasky /* data path - accessed per HW polling */ 428290650Shselasky struct mlx5_core_cq mcq; 429290650Shselasky struct mlx5e_channel *channel; 430290650Shselasky 431290650Shselasky /* control */ 432290650Shselasky struct mlx5_wq_ctrl wq_ctrl; 433290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 434290650Shselasky 435290650Shselaskystruct mlx5e_rq_mbuf { 436291070Shselasky bus_dmamap_t dma_map; 437291070Shselasky caddr_t data; 438291070Shselasky struct mbuf *mbuf; 439290650Shselasky}; 440290650Shselasky 441290650Shselaskystruct mlx5e_rq { 442290650Shselasky /* data path */ 443290650Shselasky struct mlx5_wq_ll wq; 444290650Shselasky struct mtx mtx; 445290650Shselasky bus_dma_tag_t dma_tag; 446290650Shselasky u32 wqe_sz; 447290650Shselasky struct mlx5e_rq_mbuf *mbuf; 448290650Shselasky struct device *pdev; 449290650Shselasky struct ifnet *ifp; 450290650Shselasky struct mlx5e_rq_stats stats; 451290650Shselasky struct mlx5e_cq cq; 452290650Shselasky#ifdef HAVE_TURBO_LRO 453290650Shselasky struct tlro_ctrl lro; 454290650Shselasky#else 455290650Shselasky struct lro_ctrl lro; 456290650Shselasky#endif 457290650Shselasky volatile int enabled; 458290650Shselasky int ix; 459290650Shselasky 460290650Shselasky /* control */ 461290650Shselasky struct mlx5_wq_ctrl wq_ctrl; 462290650Shselasky u32 rqn; 463290650Shselasky struct mlx5e_channel *channel; 464290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 465290650Shselasky 466290650Shselaskystruct mlx5e_sq_mbuf { 467290650Shselasky bus_dmamap_t dma_map; 468290650Shselasky struct mbuf *mbuf; 469290650Shselasky u32 num_bytes; 470290650Shselasky u32 num_wqebbs; 471290650Shselasky}; 472290650Shselasky 473290650Shselaskyenum { 474290650Shselasky MLX5E_SQ_READY, 475290650Shselasky MLX5E_SQ_FULL 476290650Shselasky}; 477290650Shselasky 478290650Shselaskystruct mlx5e_sq { 479290650Shselasky /* data path */ 480291070Shselasky struct mtx lock; 481290650Shselasky bus_dma_tag_t dma_tag; 482291070Shselasky struct mtx comp_lock; 483290650Shselasky 484290650Shselasky /* dirtied @completion */ 485290650Shselasky u16 cc; 486290650Shselasky 487290650Shselasky /* dirtied @xmit */ 488290650Shselasky u16 pc __aligned(MLX5E_CACHELINE_SIZE); 489290650Shselasky u16 bf_offset; 490291070Shselasky struct mlx5e_sq_stats stats; 491290650Shselasky 492291070Shselasky struct mlx5e_cq cq; 493291070Shselasky struct task sq_task; 494291070Shselasky struct taskqueue *sq_tq; 495290650Shselasky 496290650Shselasky /* pointers to per packet info: write@xmit, read@completion */ 497291070Shselasky struct mlx5e_sq_mbuf *mbuf; 498291070Shselasky struct buf_ring *br; 499290650Shselasky 500290650Shselasky /* read only */ 501291070Shselasky struct mlx5_wq_cyc wq; 502291070Shselasky void __iomem *uar_map; 503291070Shselasky void __iomem *uar_bf_map; 504290650Shselasky u32 sqn; 505290650Shselasky u32 bf_buf_size; 506291070Shselasky struct device *pdev; 507290650Shselasky u32 mkey_be; 508290650Shselasky 509290650Shselasky /* control path */ 510291070Shselasky struct mlx5_wq_ctrl wq_ctrl; 511291070Shselasky struct mlx5_uar uar; 512291070Shselasky struct mlx5e_channel *channel; 513290650Shselasky int tc; 514291070Shselasky unsigned int queue_state; 515290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 516290650Shselasky 517290650Shselaskystatic inline bool 518290650Shselaskymlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 519290650Shselasky{ 520290650Shselasky return ((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n || 521290650Shselasky sq->cc == sq->pc); 522290650Shselasky} 523290650Shselasky 524290650Shselaskystruct mlx5e_channel { 525290650Shselasky /* data path */ 526290650Shselasky struct mlx5e_rq rq; 527290650Shselasky struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 528290650Shselasky struct device *pdev; 529290650Shselasky struct ifnet *ifp; 530290650Shselasky u32 mkey_be; 531290650Shselasky u8 num_tc; 532290650Shselasky 533290650Shselasky /* control */ 534290650Shselasky struct mlx5e_priv *priv; 535290650Shselasky int ix; 536290650Shselasky int cpu; 537290650Shselasky} __aligned(MLX5E_CACHELINE_SIZE); 538290650Shselasky 539290650Shselaskyenum mlx5e_traffic_types { 540290650Shselasky MLX5E_TT_IPV4_TCP, 541290650Shselasky MLX5E_TT_IPV6_TCP, 542290650Shselasky MLX5E_TT_IPV4_UDP, 543290650Shselasky MLX5E_TT_IPV6_UDP, 544290650Shselasky MLX5E_TT_IPV4_IPSEC_AH, 545290650Shselasky MLX5E_TT_IPV6_IPSEC_AH, 546290650Shselasky MLX5E_TT_IPV4_IPSEC_ESP, 547290650Shselasky MLX5E_TT_IPV6_IPSEC_ESP, 548290650Shselasky MLX5E_TT_IPV4, 549290650Shselasky MLX5E_TT_IPV6, 550290650Shselasky MLX5E_TT_ANY, 551290650Shselasky MLX5E_NUM_TT, 552290650Shselasky}; 553290650Shselasky 554290650Shselaskyenum { 555290650Shselasky MLX5E_RQT_SPREADING = 0, 556290650Shselasky MLX5E_RQT_DEFAULT_RQ = 1, 557290650Shselasky MLX5E_NUM_RQT = 2, 558290650Shselasky}; 559290650Shselasky 560290650Shselaskystruct mlx5e_eth_addr_info { 561290650Shselasky u8 addr [ETH_ALEN + 2]; 562290650Shselasky u32 tt_vec; 563290650Shselasky u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */ 564290650Shselasky}; 565290650Shselasky 566290650Shselasky#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 567290650Shselasky 568290650Shselaskystruct mlx5e_eth_addr_hash_node; 569290650Shselasky 570290650Shselaskystruct mlx5e_eth_addr_hash_head { 571290650Shselasky struct mlx5e_eth_addr_hash_node *lh_first; 572290650Shselasky}; 573290650Shselasky 574290650Shselaskystruct mlx5e_eth_addr_db { 575290650Shselasky struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 576290650Shselasky struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 577290650Shselasky struct mlx5e_eth_addr_info broadcast; 578290650Shselasky struct mlx5e_eth_addr_info allmulti; 579290650Shselasky struct mlx5e_eth_addr_info promisc; 580290650Shselasky bool broadcast_enabled; 581290650Shselasky bool allmulti_enabled; 582290650Shselasky bool promisc_enabled; 583290650Shselasky}; 584290650Shselasky 585290650Shselaskyenum { 586290650Shselasky MLX5E_STATE_ASYNC_EVENTS_ENABLE, 587290650Shselasky MLX5E_STATE_OPENED, 588290650Shselasky}; 589290650Shselasky 590290650Shselaskystruct mlx5e_vlan_db { 591290650Shselasky unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 592290650Shselasky u32 active_vlans_ft_ix[VLAN_N_VID]; 593290650Shselasky u32 untagged_rule_ft_ix; 594290650Shselasky u32 any_vlan_rule_ft_ix; 595290650Shselasky bool filter_disabled; 596290650Shselasky}; 597290650Shselasky 598290650Shselaskystruct mlx5e_flow_table { 599290650Shselasky void *vlan; 600290650Shselasky void *main; 601290650Shselasky}; 602290650Shselasky 603290650Shselaskystruct mlx5e_priv { 604290650Shselasky /* priv data path fields - start */ 605290650Shselasky int order_base_2_num_channels; 606290650Shselasky int queue_mapping_channel_mask; 607290650Shselasky int num_tc; 608290650Shselasky int default_vlan_prio; 609290650Shselasky /* priv data path fields - end */ 610290650Shselasky 611290650Shselasky unsigned long state; 612290650Shselasky int gone; 613290650Shselasky#define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 614290650Shselasky#define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 615290650Shselasky#define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 616290650Shselasky struct sx state_lock; /* Protects Interface state */ 617290650Shselasky struct mlx5_uar cq_uar; 618290650Shselasky u32 pdn; 619290650Shselasky u32 tdn; 620290650Shselasky struct mlx5_core_mr mr; 621290650Shselasky 622291070Shselasky struct mlx5e_channel *volatile *channel; 623290650Shselasky u32 tisn[MLX5E_MAX_TX_NUM_TC]; 624290650Shselasky u32 rqtn; 625290650Shselasky u32 tirn[MLX5E_NUM_TT]; 626290650Shselasky 627290650Shselasky struct mlx5e_flow_table ft; 628290650Shselasky struct mlx5e_eth_addr_db eth_addr; 629290650Shselasky struct mlx5e_vlan_db vlan; 630290650Shselasky 631290650Shselasky struct mlx5e_params params; 632290650Shselasky struct mlx5e_params_ethtool params_ethtool; 633290650Shselasky struct mtx async_events_mtx; /* sync hw events */ 634290650Shselasky struct work_struct update_stats_work; 635290650Shselasky struct work_struct update_carrier_work; 636290650Shselasky struct work_struct set_rx_mode_work; 637290650Shselasky 638290650Shselasky struct mlx5_core_dev *mdev; 639290650Shselasky struct ifnet *ifp; 640290650Shselasky struct sysctl_ctx_list sysctl_ctx; 641290650Shselasky struct sysctl_oid *sysctl_ifnet; 642290650Shselasky struct sysctl_oid *sysctl_hw; 643290650Shselasky int sysctl_debug; 644290650Shselasky struct mlx5e_stats stats; 645290650Shselasky int counter_set_id; 646290650Shselasky 647290650Shselasky eventhandler_tag vlan_detach; 648290650Shselasky eventhandler_tag vlan_attach; 649290650Shselasky struct ifmedia media; 650290650Shselasky int media_status_last; 651290650Shselasky int media_active_last; 652290650Shselasky 653290650Shselasky struct callout watchdog; 654290650Shselasky}; 655290650Shselasky 656290650Shselasky#define MLX5E_NET_IP_ALIGN 2 657290650Shselasky 658290650Shselaskystruct mlx5e_tx_wqe { 659290650Shselasky struct mlx5_wqe_ctrl_seg ctrl; 660290650Shselasky struct mlx5_wqe_eth_seg eth; 661290650Shselasky}; 662290650Shselasky 663290650Shselaskystruct mlx5e_rx_wqe { 664290650Shselasky struct mlx5_wqe_srq_next_seg next; 665290650Shselasky struct mlx5_wqe_data_seg data; 666290650Shselasky}; 667290650Shselasky 668290650Shselaskystruct mlx5e_eeprom { 669291070Shselasky int lock_bit; 670291070Shselasky int i2c_addr; 671291070Shselasky int page_num; 672291070Shselasky int device_addr; 673291070Shselasky int module_num; 674291070Shselasky int len; 675291070Shselasky int type; 676291070Shselasky int page_valid; 677291070Shselasky u32 *data; 678290650Shselasky}; 679290650Shselasky 680290650Shselaskyenum mlx5e_link_mode { 681290650Shselasky MLX5E_1000BASE_CX_SGMII = 0, 682290650Shselasky MLX5E_1000BASE_KX = 1, 683290650Shselasky MLX5E_10GBASE_CX4 = 2, 684290650Shselasky MLX5E_10GBASE_KX4 = 3, 685290650Shselasky MLX5E_10GBASE_KR = 4, 686290650Shselasky MLX5E_20GBASE_KR2 = 5, 687290650Shselasky MLX5E_40GBASE_CR4 = 6, 688290650Shselasky MLX5E_40GBASE_KR4 = 7, 689290650Shselasky MLX5E_56GBASE_R4 = 8, 690290650Shselasky MLX5E_10GBASE_CR = 12, 691290650Shselasky MLX5E_10GBASE_SR = 13, 692290650Shselasky MLX5E_10GBASE_ER = 14, 693290650Shselasky MLX5E_40GBASE_SR4 = 15, 694290650Shselasky MLX5E_40GBASE_LR4 = 16, 695290650Shselasky MLX5E_100GBASE_CR4 = 20, 696290650Shselasky MLX5E_100GBASE_SR4 = 21, 697290650Shselasky MLX5E_100GBASE_KR4 = 22, 698290650Shselasky MLX5E_100GBASE_LR4 = 23, 699290650Shselasky MLX5E_100BASE_TX = 24, 700290650Shselasky MLX5E_100BASE_T = 25, 701290650Shselasky MLX5E_10GBASE_T = 26, 702290650Shselasky MLX5E_25GBASE_CR = 27, 703290650Shselasky MLX5E_25GBASE_KR = 28, 704290650Shselasky MLX5E_25GBASE_SR = 29, 705290650Shselasky MLX5E_50GBASE_CR2 = 30, 706290650Shselasky MLX5E_50GBASE_KR2 = 31, 707290650Shselasky MLX5E_LINK_MODES_NUMBER, 708290650Shselasky}; 709290650Shselasky 710290650Shselasky#define MLX5E_PROT_MASK(link_mode) (1 << (link_mode)) 711290650Shselasky#define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 712290650Shselasky 713290650Shselaskyint mlx5e_xmit(struct ifnet *, struct mbuf *); 714290650Shselasky 715290650Shselaskyint mlx5e_open_locked(struct ifnet *); 716290650Shselaskyint mlx5e_close_locked(struct ifnet *); 717290650Shselasky 718290650Shselaskyvoid mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 719290650Shselaskyvoid mlx5e_rx_cq_comp(struct mlx5_core_cq *); 720290650Shselaskyvoid mlx5e_tx_cq_comp(struct mlx5_core_cq *); 721291070Shselaskystruct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 722290650Shselaskyvoid mlx5e_tx_que(void *context, int pending); 723290650Shselasky 724290650Shselaskyint mlx5e_open_flow_table(struct mlx5e_priv *priv); 725290650Shselaskyvoid mlx5e_close_flow_table(struct mlx5e_priv *priv); 726290650Shselaskyvoid mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 727290650Shselaskyvoid mlx5e_set_rx_mode_work(struct work_struct *work); 728290650Shselasky 729290650Shselaskyvoid mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 730290650Shselaskyvoid mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 731290650Shselaskyvoid mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 732290650Shselaskyvoid mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 733290650Shselaskyint mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 734290650Shselaskyvoid mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 735290650Shselasky 736290650Shselaskystatic inline void 737290650Shselaskymlx5e_tx_notify_hw(struct mlx5e_sq *sq, 738290650Shselasky struct mlx5e_tx_wqe *wqe, int bf_sz) 739290650Shselasky{ 740290650Shselasky u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 741290650Shselasky 742290650Shselasky /* ensure wqe is visible to device before updating doorbell record */ 743290650Shselasky wmb(); 744290650Shselasky 745290650Shselasky *sq->wq.db = cpu_to_be32(sq->pc); 746290650Shselasky 747290650Shselasky /* 748290650Shselasky * Ensure the doorbell record is visible to device before ringing 749290650Shselasky * the doorbell: 750290650Shselasky */ 751290650Shselasky wmb(); 752290650Shselasky 753290650Shselasky if (bf_sz) { 754290650Shselasky __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); 755290650Shselasky 756290650Shselasky /* flush the write-combining mapped buffer */ 757290650Shselasky wmb(); 758290650Shselasky 759290650Shselasky } else { 760290650Shselasky mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); 761290650Shselasky } 762290650Shselasky 763290650Shselasky sq->bf_offset ^= sq->bf_buf_size; 764290650Shselasky} 765290650Shselasky 766290650Shselaskystatic inline void 767290650Shselaskymlx5e_cq_arm(struct mlx5e_cq *cq) 768290650Shselasky{ 769290650Shselasky struct mlx5_core_cq *mcq; 770290650Shselasky 771290650Shselasky mcq = &cq->mcq; 772290650Shselasky mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); 773290650Shselasky} 774290650Shselasky 775290650Shselaskyextern const struct ethtool_ops mlx5e_ethtool_ops; 776290650Shselaskyvoid mlx5e_create_ethtool(struct mlx5e_priv *); 777290650Shselaskyvoid mlx5e_create_stats(struct sysctl_ctx_list *, 778290650Shselasky struct sysctl_oid_list *, const char *, 779290650Shselasky const char **, unsigned, u64 *); 780290650Shselaskyvoid mlx5e_send_nop(struct mlx5e_sq *, u32, bool); 781290650Shselasky 782290650Shselasky#endif /* _MLX5_EN_H_ */ 783