1290650Shselasky/*- 2290650Shselasky * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: releng/11.0/sys/dev/mlx5/driver.h 301545 2016-06-07 13:58:52Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef MLX5_DRIVER_H 29290650Shselasky#define MLX5_DRIVER_H 30290650Shselasky 31290650Shselasky#include <linux/kernel.h> 32290650Shselasky#include <linux/completion.h> 33290650Shselasky#include <linux/pci.h> 34290650Shselasky#include <linux/cache.h> 35290650Shselasky#include <linux/rbtree.h> 36301545Shselasky#include <linux/if_ether.h> 37290650Shselasky#include <linux/semaphore.h> 38290650Shselasky#include <linux/slab.h> 39290650Shselasky#include <linux/vmalloc.h> 40290650Shselasky#include <linux/radix-tree.h> 41290650Shselasky 42290650Shselasky#include <dev/mlx5/device.h> 43290650Shselasky#include <dev/mlx5/doorbell.h> 44290650Shselasky 45290650Shselaskyenum { 46290650Shselasky MLX5_BOARD_ID_LEN = 64, 47290650Shselasky MLX5_MAX_NAME_LEN = 16, 48290650Shselasky}; 49290650Shselasky 50290650Shselaskyenum { 51290650Shselasky /* one minute for the sake of bringup. Generally, commands must always 52290650Shselasky * complete and we may need to increase this timeout value 53290650Shselasky */ 54290650Shselasky MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, 55290650Shselasky MLX5_CMD_WQ_MAX_NAME = 32, 56290650Shselasky}; 57290650Shselasky 58290650Shselaskyenum { 59290650Shselasky CMD_OWNER_SW = 0x0, 60290650Shselasky CMD_OWNER_HW = 0x1, 61290650Shselasky CMD_STATUS_SUCCESS = 0, 62290650Shselasky}; 63290650Shselasky 64290650Shselaskyenum mlx5_sqp_t { 65290650Shselasky MLX5_SQP_SMI = 0, 66290650Shselasky MLX5_SQP_GSI = 1, 67290650Shselasky MLX5_SQP_IEEE_1588 = 2, 68290650Shselasky MLX5_SQP_SNIFFER = 3, 69290650Shselasky MLX5_SQP_SYNC_UMR = 4, 70290650Shselasky}; 71290650Shselasky 72290650Shselaskyenum { 73290650Shselasky MLX5_MAX_PORTS = 2, 74290650Shselasky}; 75290650Shselasky 76290650Shselaskyenum { 77290650Shselasky MLX5_EQ_VEC_PAGES = 0, 78290650Shselasky MLX5_EQ_VEC_CMD = 1, 79290650Shselasky MLX5_EQ_VEC_ASYNC = 2, 80290650Shselasky MLX5_EQ_VEC_COMP_BASE, 81290650Shselasky}; 82290650Shselasky 83290650Shselaskyenum { 84290650Shselasky MLX5_MAX_IRQ_NAME = 32 85290650Shselasky}; 86290650Shselasky 87290650Shselaskyenum { 88290650Shselasky MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 89290650Shselasky MLX5_ATOMIC_MODE_CX = 2 << 16, 90290650Shselasky MLX5_ATOMIC_MODE_8B = 3 << 16, 91290650Shselasky MLX5_ATOMIC_MODE_16B = 4 << 16, 92290650Shselasky MLX5_ATOMIC_MODE_32B = 5 << 16, 93290650Shselasky MLX5_ATOMIC_MODE_64B = 6 << 16, 94290650Shselasky MLX5_ATOMIC_MODE_128B = 7 << 16, 95290650Shselasky MLX5_ATOMIC_MODE_256B = 8 << 16, 96290650Shselasky}; 97290650Shselasky 98290650Shselaskyenum { 99290650Shselasky MLX5_REG_QETCR = 0x4005, 100290650Shselasky MLX5_REG_QPDP = 0x4007, 101290650Shselasky MLX5_REG_QTCT = 0x400A, 102290650Shselasky MLX5_REG_PCAP = 0x5001, 103290650Shselasky MLX5_REG_PMTU = 0x5003, 104290650Shselasky MLX5_REG_PTYS = 0x5004, 105290650Shselasky MLX5_REG_PAOS = 0x5006, 106290650Shselasky MLX5_REG_PFCC = 0x5007, 107290650Shselasky MLX5_REG_PPCNT = 0x5008, 108290650Shselasky MLX5_REG_PMAOS = 0x5012, 109290650Shselasky MLX5_REG_PUDE = 0x5009, 110290650Shselasky MLX5_REG_PPTB = 0x500B, 111290650Shselasky MLX5_REG_PBMC = 0x500C, 112290650Shselasky MLX5_REG_PMPE = 0x5010, 113290650Shselasky MLX5_REG_PELC = 0x500e, 114290650Shselasky MLX5_REG_PVLC = 0x500f, 115290650Shselasky MLX5_REG_PMLP = 0x5002, 116290650Shselasky MLX5_REG_NODE_DESC = 0x6001, 117290650Shselasky MLX5_REG_HOST_ENDIANNESS = 0x7004, 118290650Shselasky MLX5_REG_MCIA = 0x9014, 119290650Shselasky}; 120290650Shselasky 121290650Shselaskyenum dbg_rsc_type { 122290650Shselasky MLX5_DBG_RSC_QP, 123290650Shselasky MLX5_DBG_RSC_EQ, 124290650Shselasky MLX5_DBG_RSC_CQ, 125290650Shselasky}; 126290650Shselasky 127290650Shselaskystruct mlx5_field_desc { 128290650Shselasky struct dentry *dent; 129290650Shselasky int i; 130290650Shselasky}; 131290650Shselasky 132290650Shselaskystruct mlx5_rsc_debug { 133290650Shselasky struct mlx5_core_dev *dev; 134290650Shselasky void *object; 135290650Shselasky enum dbg_rsc_type type; 136290650Shselasky struct dentry *root; 137290650Shselasky struct mlx5_field_desc fields[0]; 138290650Shselasky}; 139290650Shselasky 140290650Shselaskyenum mlx5_dev_event { 141290650Shselasky MLX5_DEV_EVENT_SYS_ERROR, 142290650Shselasky MLX5_DEV_EVENT_PORT_UP, 143290650Shselasky MLX5_DEV_EVENT_PORT_DOWN, 144290650Shselasky MLX5_DEV_EVENT_PORT_INITIALIZED, 145290650Shselasky MLX5_DEV_EVENT_LID_CHANGE, 146290650Shselasky MLX5_DEV_EVENT_PKEY_CHANGE, 147290650Shselasky MLX5_DEV_EVENT_GUID_CHANGE, 148290650Shselasky MLX5_DEV_EVENT_CLIENT_REREG, 149290650Shselasky MLX5_DEV_EVENT_VPORT_CHANGE, 150290650Shselasky}; 151290650Shselasky 152290650Shselaskyenum mlx5_port_status { 153290650Shselasky MLX5_PORT_UP = 1 << 0, 154290650Shselasky MLX5_PORT_DOWN = 1 << 1, 155290650Shselasky}; 156290650Shselasky 157290650Shselaskyenum mlx5_link_mode { 158290650Shselasky MLX5_1000BASE_CX_SGMII = 0, 159290650Shselasky MLX5_1000BASE_KX = 1, 160290650Shselasky MLX5_10GBASE_CX4 = 2, 161290650Shselasky MLX5_10GBASE_KX4 = 3, 162290650Shselasky MLX5_10GBASE_KR = 4, 163290650Shselasky MLX5_20GBASE_KR2 = 5, 164290650Shselasky MLX5_40GBASE_CR4 = 6, 165290650Shselasky MLX5_40GBASE_KR4 = 7, 166290650Shselasky MLX5_56GBASE_R4 = 8, 167290650Shselasky MLX5_10GBASE_CR = 12, 168290650Shselasky MLX5_10GBASE_SR = 13, 169290650Shselasky MLX5_10GBASE_ER = 14, 170290650Shselasky MLX5_40GBASE_SR4 = 15, 171290650Shselasky MLX5_40GBASE_LR4 = 16, 172290650Shselasky MLX5_100GBASE_CR4 = 20, 173290650Shselasky MLX5_100GBASE_SR4 = 21, 174290650Shselasky MLX5_100GBASE_KR4 = 22, 175290650Shselasky MLX5_100GBASE_LR4 = 23, 176290650Shselasky MLX5_100BASE_TX = 24, 177290650Shselasky MLX5_1000BASE_T = 25, 178290650Shselasky MLX5_10GBASE_T = 26, 179290650Shselasky MLX5_25GBASE_CR = 27, 180290650Shselasky MLX5_25GBASE_KR = 28, 181290650Shselasky MLX5_25GBASE_SR = 29, 182290650Shselasky MLX5_50GBASE_CR2 = 30, 183290650Shselasky MLX5_50GBASE_KR2 = 31, 184290650Shselasky MLX5_LINK_MODES_NUMBER, 185290650Shselasky}; 186290650Shselasky 187290650Shselasky#define MLX5_PROT_MASK(link_mode) (1 << link_mode) 188290650Shselasky 189290650Shselaskystruct mlx5_uuar_info { 190290650Shselasky struct mlx5_uar *uars; 191290650Shselasky int num_uars; 192290650Shselasky int num_low_latency_uuars; 193290650Shselasky unsigned long *bitmap; 194290650Shselasky unsigned int *count; 195290650Shselasky struct mlx5_bf *bfs; 196290650Shselasky 197290650Shselasky /* 198290650Shselasky * protect uuar allocation data structs 199290650Shselasky */ 200290650Shselasky struct mutex lock; 201290650Shselasky u32 ver; 202290650Shselasky}; 203290650Shselasky 204290650Shselaskystruct mlx5_bf { 205290650Shselasky void __iomem *reg; 206290650Shselasky void __iomem *regreg; 207290650Shselasky int buf_size; 208290650Shselasky struct mlx5_uar *uar; 209290650Shselasky unsigned long offset; 210290650Shselasky int need_lock; 211290650Shselasky /* protect blue flame buffer selection when needed 212290650Shselasky */ 213290650Shselasky spinlock_t lock; 214290650Shselasky 215290650Shselasky /* serialize 64 bit writes when done as two 32 bit accesses 216290650Shselasky */ 217290650Shselasky spinlock_t lock32; 218290650Shselasky int uuarn; 219290650Shselasky}; 220290650Shselasky 221290650Shselaskystruct mlx5_cmd_first { 222290650Shselasky __be32 data[4]; 223290650Shselasky}; 224290650Shselasky 225290650Shselaskystruct mlx5_cmd_msg { 226290650Shselasky struct list_head list; 227290650Shselasky struct cache_ent *cache; 228290650Shselasky u32 len; 229290650Shselasky struct mlx5_cmd_first first; 230290650Shselasky struct mlx5_cmd_mailbox *next; 231290650Shselasky}; 232290650Shselasky 233290650Shselaskystruct mlx5_cmd_debug { 234290650Shselasky struct dentry *dbg_root; 235290650Shselasky struct dentry *dbg_in; 236290650Shselasky struct dentry *dbg_out; 237290650Shselasky struct dentry *dbg_outlen; 238290650Shselasky struct dentry *dbg_status; 239290650Shselasky struct dentry *dbg_run; 240290650Shselasky void *in_msg; 241290650Shselasky void *out_msg; 242290650Shselasky u8 status; 243290650Shselasky u16 inlen; 244290650Shselasky u16 outlen; 245290650Shselasky}; 246290650Shselasky 247290650Shselaskystruct cache_ent { 248290650Shselasky /* protect block chain allocations 249290650Shselasky */ 250290650Shselasky spinlock_t lock; 251290650Shselasky struct list_head head; 252290650Shselasky}; 253290650Shselasky 254290650Shselaskystruct cmd_msg_cache { 255290650Shselasky struct cache_ent large; 256290650Shselasky struct cache_ent med; 257290650Shselasky 258290650Shselasky}; 259290650Shselasky 260290650Shselaskystruct mlx5_cmd_stats { 261290650Shselasky u64 sum; 262290650Shselasky u64 n; 263290650Shselasky struct dentry *root; 264290650Shselasky struct dentry *avg; 265290650Shselasky struct dentry *count; 266290650Shselasky /* protect command average calculations */ 267290650Shselasky spinlock_t lock; 268290650Shselasky}; 269290650Shselasky 270290650Shselaskystruct mlx5_cmd { 271290650Shselasky void *cmd_alloc_buf; 272290650Shselasky dma_addr_t alloc_dma; 273290650Shselasky int alloc_size; 274290650Shselasky void *cmd_buf; 275290650Shselasky dma_addr_t dma; 276290650Shselasky u16 cmdif_rev; 277290650Shselasky u8 log_sz; 278290650Shselasky u8 log_stride; 279290650Shselasky int max_reg_cmds; 280290650Shselasky int events; 281290650Shselasky u32 __iomem *vector; 282290650Shselasky 283290650Shselasky /* protect command queue allocations 284290650Shselasky */ 285290650Shselasky spinlock_t alloc_lock; 286290650Shselasky 287290650Shselasky /* protect token allocations 288290650Shselasky */ 289290650Shselasky spinlock_t token_lock; 290290650Shselasky u8 token; 291290650Shselasky unsigned long bitmask; 292290650Shselasky char wq_name[MLX5_CMD_WQ_MAX_NAME]; 293290650Shselasky struct workqueue_struct *wq; 294290650Shselasky struct semaphore sem; 295290650Shselasky struct semaphore pages_sem; 296290650Shselasky int mode; 297290650Shselasky struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 298290650Shselasky struct pci_pool *pool; 299290650Shselasky struct mlx5_cmd_debug dbg; 300290650Shselasky struct cmd_msg_cache cache; 301290650Shselasky int checksum_disabled; 302290650Shselasky struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 303290650Shselasky int moving_to_polling; 304290650Shselasky}; 305290650Shselasky 306290650Shselaskystruct mlx5_port_caps { 307290650Shselasky int gid_table_len; 308290650Shselasky int pkey_table_len; 309290650Shselasky u8 ext_port_cap; 310290650Shselasky}; 311290650Shselasky 312290650Shselaskystruct mlx5_cmd_mailbox { 313290650Shselasky void *buf; 314290650Shselasky dma_addr_t dma; 315290650Shselasky struct mlx5_cmd_mailbox *next; 316290650Shselasky}; 317290650Shselasky 318290650Shselaskystruct mlx5_buf_list { 319290650Shselasky void *buf; 320290650Shselasky dma_addr_t map; 321290650Shselasky}; 322290650Shselasky 323290650Shselaskystruct mlx5_buf { 324290650Shselasky struct mlx5_buf_list direct; 325290650Shselasky struct mlx5_buf_list *page_list; 326290650Shselasky int nbufs; 327290650Shselasky int npages; 328290650Shselasky int size; 329290650Shselasky u8 page_shift; 330290650Shselasky}; 331290650Shselasky 332290650Shselaskystruct mlx5_eq { 333290650Shselasky struct mlx5_core_dev *dev; 334290650Shselasky __be32 __iomem *doorbell; 335290650Shselasky u32 cons_index; 336290650Shselasky struct mlx5_buf buf; 337290650Shselasky int size; 338290650Shselasky u8 irqn; 339290650Shselasky u8 eqn; 340290650Shselasky int nent; 341290650Shselasky u64 mask; 342290650Shselasky struct list_head list; 343290650Shselasky int index; 344290650Shselasky struct mlx5_rsc_debug *dbg; 345290650Shselasky}; 346290650Shselasky 347290650Shselaskystruct mlx5_core_psv { 348290650Shselasky u32 psv_idx; 349290650Shselasky struct psv_layout { 350290650Shselasky u32 pd; 351290650Shselasky u16 syndrome; 352290650Shselasky u16 reserved; 353290650Shselasky u16 bg; 354290650Shselasky u16 app_tag; 355290650Shselasky u32 ref_tag; 356290650Shselasky } psv; 357290650Shselasky}; 358290650Shselasky 359290650Shselaskystruct mlx5_core_sig_ctx { 360290650Shselasky struct mlx5_core_psv psv_memory; 361290650Shselasky struct mlx5_core_psv psv_wire; 362290650Shselasky#if (__FreeBSD_version >= 1100000) 363290650Shselasky struct ib_sig_err err_item; 364290650Shselasky#endif 365290650Shselasky bool sig_status_checked; 366290650Shselasky bool sig_err_exists; 367290650Shselasky u32 sigerr_count; 368290650Shselasky}; 369290650Shselasky 370290650Shselaskystruct mlx5_core_mr { 371290650Shselasky u64 iova; 372290650Shselasky u64 size; 373290650Shselasky u32 key; 374290650Shselasky u32 pd; 375290650Shselasky}; 376290650Shselasky 377290650Shselaskyenum mlx5_res_type { 378290650Shselasky MLX5_RES_QP, 379290650Shselasky MLX5_RES_SRQ, 380290650Shselasky MLX5_RES_XSRQ, 381290650Shselasky}; 382290650Shselasky 383290650Shselaskystruct mlx5_core_rsc_common { 384290650Shselasky enum mlx5_res_type res; 385290650Shselasky atomic_t refcount; 386290650Shselasky struct completion free; 387290650Shselasky}; 388290650Shselasky 389290650Shselaskystruct mlx5_core_srq { 390290650Shselasky struct mlx5_core_rsc_common common; /* must be first */ 391290650Shselasky u32 srqn; 392290650Shselasky int max; 393290650Shselasky int max_gs; 394290650Shselasky int max_avail_gather; 395290650Shselasky int wqe_shift; 396290650Shselasky void (*event)(struct mlx5_core_srq *, int); 397290650Shselasky atomic_t refcount; 398290650Shselasky struct completion free; 399290650Shselasky}; 400290650Shselasky 401290650Shselaskystruct mlx5_eq_table { 402290650Shselasky void __iomem *update_ci; 403290650Shselasky void __iomem *update_arm_ci; 404290650Shselasky struct list_head comp_eqs_list; 405290650Shselasky struct mlx5_eq pages_eq; 406290650Shselasky struct mlx5_eq async_eq; 407290650Shselasky struct mlx5_eq cmd_eq; 408290650Shselasky int num_comp_vectors; 409290650Shselasky /* protect EQs list 410290650Shselasky */ 411290650Shselasky spinlock_t lock; 412290650Shselasky}; 413290650Shselasky 414290650Shselaskystruct mlx5_uar { 415290650Shselasky u32 index; 416290650Shselasky struct list_head bf_list; 417290650Shselasky unsigned free_bf_bmap; 418290650Shselasky void __iomem *bf_map; 419290650Shselasky void __iomem *map; 420290650Shselasky}; 421290650Shselasky 422290650Shselasky 423290650Shselaskystruct mlx5_core_health { 424290650Shselasky struct mlx5_health_buffer __iomem *health; 425290650Shselasky __be32 __iomem *health_counter; 426290650Shselasky struct timer_list timer; 427290650Shselasky struct list_head list; 428290650Shselasky u32 prev; 429290650Shselasky int miss_counter; 430290650Shselasky}; 431290650Shselasky 432290650Shselasky#define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 433290650Shselasky 434290650Shselaskystruct mlx5_cq_linear_array_entry { 435290650Shselasky spinlock_t lock; 436290650Shselasky struct mlx5_core_cq * volatile cq; 437290650Shselasky}; 438290650Shselasky 439290650Shselaskystruct mlx5_cq_table { 440290650Shselasky /* protect radix tree 441290650Shselasky */ 442290650Shselasky spinlock_t lock; 443290650Shselasky struct radix_tree_root tree; 444290650Shselasky struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 445290650Shselasky}; 446290650Shselasky 447290650Shselaskystruct mlx5_qp_table { 448290650Shselasky /* protect radix tree 449290650Shselasky */ 450290650Shselasky spinlock_t lock; 451290650Shselasky struct radix_tree_root tree; 452290650Shselasky}; 453290650Shselasky 454290650Shselaskystruct mlx5_srq_table { 455290650Shselasky /* protect radix tree 456290650Shselasky */ 457290650Shselasky spinlock_t lock; 458290650Shselasky struct radix_tree_root tree; 459290650Shselasky}; 460290650Shselasky 461290650Shselaskystruct mlx5_mr_table { 462290650Shselasky /* protect radix tree 463290650Shselasky */ 464290650Shselasky rwlock_t lock; 465290650Shselasky struct radix_tree_root tree; 466290650Shselasky}; 467290650Shselasky 468290650Shselaskystruct mlx5_irq_info { 469290650Shselasky char name[MLX5_MAX_IRQ_NAME]; 470290650Shselasky}; 471290650Shselasky 472290650Shselaskystruct mlx5_priv { 473290650Shselasky char name[MLX5_MAX_NAME_LEN]; 474290650Shselasky struct mlx5_eq_table eq_table; 475290650Shselasky struct msix_entry *msix_arr; 476290650Shselasky struct mlx5_irq_info *irq_info; 477290650Shselasky struct mlx5_uuar_info uuari; 478290650Shselasky MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 479290650Shselasky 480290650Shselasky struct io_mapping *bf_mapping; 481290650Shselasky 482290650Shselasky /* pages stuff */ 483290650Shselasky struct workqueue_struct *pg_wq; 484290650Shselasky struct rb_root page_root; 485290650Shselasky int fw_pages; 486290650Shselasky int reg_pages; 487290650Shselasky struct list_head free_list; 488290650Shselasky 489290650Shselasky struct mlx5_core_health health; 490290650Shselasky 491290650Shselasky struct mlx5_srq_table srq_table; 492290650Shselasky 493290650Shselasky /* start: qp staff */ 494290650Shselasky struct mlx5_qp_table qp_table; 495290650Shselasky struct dentry *qp_debugfs; 496290650Shselasky struct dentry *eq_debugfs; 497290650Shselasky struct dentry *cq_debugfs; 498290650Shselasky struct dentry *cmdif_debugfs; 499290650Shselasky /* end: qp staff */ 500290650Shselasky 501290650Shselasky /* start: cq staff */ 502290650Shselasky struct mlx5_cq_table cq_table; 503290650Shselasky /* end: cq staff */ 504290650Shselasky 505290650Shselasky /* start: mr staff */ 506290650Shselasky struct mlx5_mr_table mr_table; 507290650Shselasky /* end: mr staff */ 508290650Shselasky 509290650Shselasky /* start: alloc staff */ 510290650Shselasky int numa_node; 511290650Shselasky 512290650Shselasky struct mutex pgdir_mutex; 513290650Shselasky struct list_head pgdir_list; 514290650Shselasky /* end: alloc staff */ 515290650Shselasky struct dentry *dbg_root; 516290650Shselasky 517290650Shselasky /* protect mkey key part */ 518290650Shselasky spinlock_t mkey_lock; 519290650Shselasky u8 mkey_key; 520290650Shselasky 521290650Shselasky struct list_head dev_list; 522290650Shselasky struct list_head ctx_list; 523290650Shselasky spinlock_t ctx_lock; 524290650Shselasky}; 525290650Shselasky 526290650Shselaskystruct mlx5_special_contexts { 527290650Shselasky int resd_lkey; 528290650Shselasky}; 529290650Shselasky 530290650Shselaskystruct mlx5_core_dev { 531290650Shselasky struct pci_dev *pdev; 532290650Shselasky char board_id[MLX5_BOARD_ID_LEN]; 533290650Shselasky struct mlx5_cmd cmd; 534290650Shselasky struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 535290650Shselasky u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 536290650Shselasky u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 537290650Shselasky struct mlx5_init_seg __iomem *iseg; 538290650Shselasky void (*event) (struct mlx5_core_dev *dev, 539290650Shselasky enum mlx5_dev_event event, 540290650Shselasky unsigned long param); 541290650Shselasky struct mlx5_priv priv; 542290650Shselasky struct mlx5_profile *profile; 543290650Shselasky atomic_t num_qps; 544290650Shselasky u32 issi; 545290650Shselasky struct mlx5_special_contexts special_contexts; 546298771Shselasky unsigned int module_status[MLX5_MAX_PORTS]; 547290650Shselasky}; 548290650Shselasky 549290650Shselaskyenum { 550290650Shselasky MLX5_WOL_DISABLE = 0, 551290650Shselasky MLX5_WOL_SECURED_MAGIC = 1 << 1, 552290650Shselasky MLX5_WOL_MAGIC = 1 << 2, 553290650Shselasky MLX5_WOL_ARP = 1 << 3, 554290650Shselasky MLX5_WOL_BROADCAST = 1 << 4, 555290650Shselasky MLX5_WOL_MULTICAST = 1 << 5, 556290650Shselasky MLX5_WOL_UNICAST = 1 << 6, 557290650Shselasky MLX5_WOL_PHY_ACTIVITY = 1 << 7, 558290650Shselasky}; 559290650Shselasky 560290650Shselaskystruct mlx5_db { 561290650Shselasky __be32 *db; 562290650Shselasky union { 563290650Shselasky struct mlx5_db_pgdir *pgdir; 564290650Shselasky struct mlx5_ib_user_db_page *user_page; 565290650Shselasky } u; 566290650Shselasky dma_addr_t dma; 567290650Shselasky int index; 568290650Shselasky}; 569290650Shselasky 570290650Shselaskystruct mlx5_net_counters { 571290650Shselasky u64 packets; 572290650Shselasky u64 octets; 573290650Shselasky}; 574290650Shselasky 575290650Shselaskystruct mlx5_ptys_reg { 576290650Shselasky u8 local_port; 577290650Shselasky u8 proto_mask; 578290650Shselasky u32 eth_proto_cap; 579290650Shselasky u16 ib_link_width_cap; 580290650Shselasky u16 ib_proto_cap; 581290650Shselasky u32 eth_proto_admin; 582290650Shselasky u16 ib_link_width_admin; 583290650Shselasky u16 ib_proto_admin; 584290650Shselasky u32 eth_proto_oper; 585290650Shselasky u16 ib_link_width_oper; 586290650Shselasky u16 ib_proto_oper; 587290650Shselasky u32 eth_proto_lp_advertise; 588290650Shselasky}; 589290650Shselasky 590290650Shselaskystruct mlx5_pvlc_reg { 591290650Shselasky u8 local_port; 592290650Shselasky u8 vl_hw_cap; 593290650Shselasky u8 vl_admin; 594290650Shselasky u8 vl_operational; 595290650Shselasky}; 596290650Shselasky 597290650Shselaskystruct mlx5_pmtu_reg { 598290650Shselasky u8 local_port; 599290650Shselasky u16 max_mtu; 600290650Shselasky u16 admin_mtu; 601290650Shselasky u16 oper_mtu; 602290650Shselasky}; 603290650Shselasky 604290650Shselaskystruct mlx5_vport_counters { 605290650Shselasky struct mlx5_net_counters received_errors; 606290650Shselasky struct mlx5_net_counters transmit_errors; 607290650Shselasky struct mlx5_net_counters received_ib_unicast; 608290650Shselasky struct mlx5_net_counters transmitted_ib_unicast; 609290650Shselasky struct mlx5_net_counters received_ib_multicast; 610290650Shselasky struct mlx5_net_counters transmitted_ib_multicast; 611290650Shselasky struct mlx5_net_counters received_eth_broadcast; 612290650Shselasky struct mlx5_net_counters transmitted_eth_broadcast; 613290650Shselasky struct mlx5_net_counters received_eth_unicast; 614290650Shselasky struct mlx5_net_counters transmitted_eth_unicast; 615290650Shselasky struct mlx5_net_counters received_eth_multicast; 616290650Shselasky struct mlx5_net_counters transmitted_eth_multicast; 617290650Shselasky}; 618290650Shselasky 619290650Shselaskyenum { 620290650Shselasky MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 621290650Shselasky}; 622290650Shselasky 623290650Shselaskyenum { 624290650Shselasky MLX5_COMP_EQ_SIZE = 1024, 625290650Shselasky}; 626290650Shselasky 627290650Shselaskyenum { 628290650Shselasky MLX5_PTYS_IB = 1 << 0, 629290650Shselasky MLX5_PTYS_EN = 1 << 2, 630290650Shselasky}; 631290650Shselasky 632290650Shselaskystruct mlx5_db_pgdir { 633290650Shselasky struct list_head list; 634290650Shselasky DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 635290650Shselasky __be32 *db_page; 636290650Shselasky dma_addr_t db_dma; 637290650Shselasky}; 638290650Shselasky 639290650Shselaskytypedef void (*mlx5_cmd_cbk_t)(int status, void *context); 640290650Shselasky 641290650Shselaskystruct mlx5_cmd_work_ent { 642290650Shselasky struct mlx5_cmd_msg *in; 643290650Shselasky struct mlx5_cmd_msg *out; 644290650Shselasky void *uout; 645290650Shselasky int uout_size; 646290650Shselasky mlx5_cmd_cbk_t callback; 647290650Shselasky void *context; 648290650Shselasky int idx; 649290650Shselasky struct completion done; 650290650Shselasky struct mlx5_cmd *cmd; 651290650Shselasky struct work_struct work; 652290650Shselasky struct mlx5_cmd_layout *lay; 653290650Shselasky int ret; 654290650Shselasky int page_queue; 655290650Shselasky u8 status; 656290650Shselasky u8 token; 657290650Shselasky u64 ts1; 658290650Shselasky u64 ts2; 659290650Shselasky u16 op; 660290650Shselasky}; 661290650Shselasky 662290650Shselaskystruct mlx5_pas { 663290650Shselasky u64 pa; 664290650Shselasky u8 log_sz; 665290650Shselasky}; 666290650Shselasky 667290650Shselaskystatic inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 668290650Shselasky{ 669290650Shselasky if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1)) 670290650Shselasky return buf->direct.buf + offset; 671290650Shselasky else 672290650Shselasky return buf->page_list[offset >> PAGE_SHIFT].buf + 673290650Shselasky (offset & (PAGE_SIZE - 1)); 674290650Shselasky} 675290650Shselasky 676290650Shselasky 677290650Shselaskyextern struct workqueue_struct *mlx5_core_wq; 678290650Shselasky 679290650Shselasky#define STRUCT_FIELD(header, field) \ 680290650Shselasky .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 681290650Shselasky .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 682290650Shselasky 683290650Shselaskystatic inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 684290650Shselasky{ 685290650Shselasky return pci_get_drvdata(pdev); 686290650Shselasky} 687290650Shselasky 688290650Shselaskyextern struct dentry *mlx5_debugfs_root; 689290650Shselasky 690290650Shselaskystatic inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 691290650Shselasky{ 692290650Shselasky return ioread32be(&dev->iseg->fw_rev) & 0xffff; 693290650Shselasky} 694290650Shselasky 695290650Shselaskystatic inline u16 fw_rev_min(struct mlx5_core_dev *dev) 696290650Shselasky{ 697290650Shselasky return ioread32be(&dev->iseg->fw_rev) >> 16; 698290650Shselasky} 699290650Shselasky 700290650Shselaskystatic inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 701290650Shselasky{ 702290650Shselasky return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 703290650Shselasky} 704290650Shselasky 705290650Shselaskystatic inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 706290650Shselasky{ 707290650Shselasky return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 708290650Shselasky} 709290650Shselasky 710290650Shselaskystatic inline int mlx5_get_gid_table_len(u16 param) 711290650Shselasky{ 712290650Shselasky if (param > 4) { 713290650Shselasky printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 714290650Shselasky return 0; 715290650Shselasky } 716290650Shselasky 717290650Shselasky return 8 * (1 << param); 718290650Shselasky} 719290650Shselasky 720290650Shselaskystatic inline void *mlx5_vzalloc(unsigned long size) 721290650Shselasky{ 722290650Shselasky void *rtn; 723290650Shselasky 724290650Shselasky rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 725290650Shselasky return rtn; 726290650Shselasky} 727290650Shselasky 728290650Shselaskystatic inline u32 mlx5_base_mkey(const u32 key) 729290650Shselasky{ 730290650Shselasky return key & 0xffffff00u; 731290650Shselasky} 732290650Shselasky 733290650Shselaskyint mlx5_cmd_init(struct mlx5_core_dev *dev); 734290650Shselaskyvoid mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 735290650Shselaskyvoid mlx5_cmd_use_events(struct mlx5_core_dev *dev); 736290650Shselaskyvoid mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 737290650Shselaskyint mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 738290650Shselaskyint mlx5_cmd_status_to_err_v2(void *ptr); 739290650Shselaskyint mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 740290650Shselasky enum mlx5_cap_mode cap_mode); 741290650Shselaskyint mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 742290650Shselasky int out_size); 743290650Shselaskyint mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 744290650Shselasky void *out, int out_size, mlx5_cmd_cbk_t callback, 745290650Shselasky void *context); 746290650Shselaskyint mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 747290650Shselaskyint mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 748290650Shselaskyint mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 749290650Shselaskyint mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 750290650Shselaskyint mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 751290650Shselaskyvoid mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 752290650Shselaskyvoid mlx5_health_cleanup(void); 753290650Shselaskyvoid __init mlx5_health_init(void); 754290650Shselaskyvoid mlx5_start_health_poll(struct mlx5_core_dev *dev); 755290650Shselaskyvoid mlx5_stop_health_poll(struct mlx5_core_dev *dev); 756290650Shselaskyint mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, int max_direct, 757290650Shselasky struct mlx5_buf *buf, int node); 758290650Shselaskyint mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 759290650Shselasky struct mlx5_buf *buf); 760290650Shselaskyvoid mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 761290650Shselaskyint mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 762290650Shselasky struct mlx5_create_srq_mbox_in *in, int inlen, 763290650Shselasky int is_xrc); 764290650Shselaskyint mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 765290650Shselaskyint mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 766290650Shselasky struct mlx5_query_srq_mbox_out *out); 767290650Shselaskyint mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 768290650Shselaskyint mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 769290650Shselasky u16 lwm, int is_srq); 770290650Shselaskyvoid mlx5_init_mr_table(struct mlx5_core_dev *dev); 771290650Shselaskyvoid mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 772290650Shselaskyint mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 773290650Shselasky struct mlx5_create_mkey_mbox_in *in, int inlen, 774290650Shselasky mlx5_cmd_cbk_t callback, void *context, 775290650Shselasky struct mlx5_create_mkey_mbox_out *out); 776290650Shselaskyint mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 777290650Shselaskyint mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 778290650Shselasky struct mlx5_query_mkey_mbox_out *out, int outlen); 779290650Shselaskyint mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 780290650Shselasky u32 *mkey); 781290650Shselaskyint mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 782290650Shselaskyint mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 783290650Shselaskyint mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, 784290650Shselasky u16 opmod, u8 port); 785290650Shselaskyvoid mlx5_pagealloc_init(struct mlx5_core_dev *dev); 786290650Shselaskyvoid mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 787290650Shselaskyint mlx5_pagealloc_start(struct mlx5_core_dev *dev); 788290650Shselaskyvoid mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 789290650Shselaskyvoid mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 790290650Shselasky s32 npages); 791290650Shselaskyint mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 792290650Shselaskyint mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 793290650Shselaskyvoid mlx5_register_debugfs(void); 794290650Shselaskyvoid mlx5_unregister_debugfs(void); 795290650Shselaskyint mlx5_eq_init(struct mlx5_core_dev *dev); 796290650Shselaskyvoid mlx5_eq_cleanup(struct mlx5_core_dev *dev); 797290650Shselaskyvoid mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 798290650Shselaskyvoid mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 799290650Shselaskyvoid mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 800290650Shselaskyvoid mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 801290650Shselaskystruct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 802290650Shselaskyvoid mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); 803290650Shselaskyvoid mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 804290650Shselaskyint mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 805290650Shselasky int nent, u64 mask, const char *name, struct mlx5_uar *uar); 806290650Shselaskyint mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 807290650Shselaskyint mlx5_start_eqs(struct mlx5_core_dev *dev); 808290650Shselaskyint mlx5_stop_eqs(struct mlx5_core_dev *dev); 809290650Shselaskyint mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 810290650Shselaskyint mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 811290650Shselaskyint mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 812290650Shselasky 813290650Shselaskyint mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 814290650Shselaskyvoid mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 815290650Shselaskyint mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 816290650Shselasky int size_in, void *data_out, int size_out, 817290650Shselasky u16 reg_num, int arg, int write); 818290650Shselasky 819290650Shselaskyint mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 820290650Shselaskyint mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 821290650Shselasky int ptys_size, int proto_mask); 822290650Shselaskyint mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 823290650Shselasky u32 *proto_cap, int proto_mask); 824290650Shselaskyint mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 825290650Shselasky u32 *proto_admin, int proto_mask); 826290650Shselaskyint mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 827290650Shselasky int proto_mask); 828290650Shselaskyint mlx5_set_port_status(struct mlx5_core_dev *dev, 829290650Shselasky enum mlx5_port_status status); 830290650Shselaskyint mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 831290650Shselaskyint mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port, 832290650Shselasky u32 rx_pause, u32 tx_pause); 833290650Shselaskyint mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 834290650Shselasky u32 *rx_pause, u32 *tx_pause); 835290650Shselasky 836290650Shselaskyint mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 837290650Shselaskyint mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 838290650Shselaskyint mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 839290650Shselasky 840298771Shselaskyunsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 841290650Shselaskyint mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 842290650Shselaskyint mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 843290650Shselasky int device_addr, int size, int module_num, u32 *data, 844290650Shselasky int *size_read); 845290650Shselasky 846290650Shselaskyint mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 847290650Shselaskyvoid mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 848290650Shselaskyint mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 849290650Shselasky struct mlx5_query_eq_mbox_out *out, int outlen); 850290650Shselaskyint mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 851290650Shselaskyvoid mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 852290650Shselaskyint mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 853290650Shselaskyvoid mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 854290650Shselaskyint mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 855290650Shselaskyint mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 856290650Shselasky int node); 857290650Shselaskyvoid mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 858290650Shselasky 859290650Shselaskyconst char *mlx5_command_str(int command); 860290650Shselaskyint mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 861290650Shselaskyvoid mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 862290650Shselaskyint mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 863290650Shselasky int npsvs, u32 *sig_index); 864290650Shselaskyint mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 865290650Shselaskyvoid mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 866290650Shselaskyu8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 867290650Shselaskyint mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 868290650Shselaskyint mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 869290650Shselaskyint mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 870290650Shselasky struct mlx5_pvlc_reg *pvlc, int write); 871290650Shselaskyint mlx5_core_access_ptys(struct mlx5_core_dev *dev, 872290650Shselasky struct mlx5_ptys_reg *ptys, int write); 873290650Shselaskyint mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 874290650Shselasky struct mlx5_pmtu_reg *pmtu, int write); 875290650Shselaskyint mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 876290650Shselaskyint mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 877290650Shselaskyint mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 878290650Shselasky int priority, int *is_enable); 879290650Shselaskyint mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 880290650Shselasky int priority, int enable); 881290650Shselaskyint mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 882290650Shselasky void *out, int out_size); 883290650Shselaskyint mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 884290650Shselasky void *in, int in_size); 885290650Shselaskyint mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 886290650Shselasky void *out, int out_size); 887290650Shselaskystatic inline u32 mlx5_mkey_to_idx(u32 mkey) 888290650Shselasky{ 889290650Shselasky return mkey >> 8; 890290650Shselasky} 891290650Shselasky 892290650Shselaskystatic inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 893290650Shselasky{ 894290650Shselasky return mkey_idx << 8; 895290650Shselasky} 896290650Shselasky 897290650Shselaskystatic inline u8 mlx5_mkey_variant(u32 mkey) 898290650Shselasky{ 899290650Shselasky return mkey & 0xff; 900290650Shselasky} 901290650Shselasky 902290650Shselaskyenum { 903290650Shselasky MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 904290650Shselasky MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 905290650Shselasky}; 906290650Shselasky 907290650Shselaskyenum { 908290650Shselasky MAX_MR_CACHE_ENTRIES = 16, 909290650Shselasky}; 910290650Shselasky 911290650Shselaskyenum { 912290650Shselasky MLX5_INTERFACE_PROTOCOL_IB = 0, 913290650Shselasky MLX5_INTERFACE_PROTOCOL_ETH = 1, 914290650Shselasky}; 915290650Shselasky 916290650Shselaskystruct mlx5_interface { 917290650Shselasky void * (*add)(struct mlx5_core_dev *dev); 918290650Shselasky void (*remove)(struct mlx5_core_dev *dev, void *context); 919290650Shselasky void (*event)(struct mlx5_core_dev *dev, void *context, 920290650Shselasky enum mlx5_dev_event event, unsigned long param); 921290650Shselasky void * (*get_dev)(void *context); 922290650Shselasky int protocol; 923290650Shselasky struct list_head list; 924290650Shselasky}; 925290650Shselasky 926290650Shselaskyvoid *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 927290650Shselaskyint mlx5_register_interface(struct mlx5_interface *intf); 928290650Shselaskyvoid mlx5_unregister_interface(struct mlx5_interface *intf); 929290650Shselasky 930290650Shselaskystruct mlx5_profile { 931290650Shselasky u64 mask; 932290650Shselasky u8 log_max_qp; 933290650Shselasky struct { 934290650Shselasky int size; 935290650Shselasky int limit; 936290650Shselasky } mr_cache[MAX_MR_CACHE_ENTRIES]; 937290650Shselasky}; 938290650Shselasky 939290650Shselasky 940291939Shselasky#define MLX5_EEPROM_MAX_BYTES 32 941290650Shselasky#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 942290650Shselasky#define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 943290650Shselasky#define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 944290650Shselasky#endif /* MLX5_DRIVER_H */ 945