ciphyreg.h revision 139749
1139749Simp/*- 2135048Swpaul * Copyright (c) 2004 3135048Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4135048Swpaul * 5135048Swpaul * Redistribution and use in source and binary forms, with or without 6135048Swpaul * modification, are permitted provided that the following conditions 7135048Swpaul * are met: 8135048Swpaul * 1. Redistributions of source code must retain the above copyright 9135048Swpaul * notice, this list of conditions and the following disclaimer. 10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11135048Swpaul * notice, this list of conditions and the following disclaimer in the 12135048Swpaul * documentation and/or other materials provided with the distribution. 13135048Swpaul * 3. All advertising materials mentioning features or use of this software 14135048Swpaul * must display the following acknowledgement: 15135048Swpaul * This product includes software developed by Bill Paul. 16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors 17135048Swpaul * may be used to endorse or promote products derived from this software 18135048Swpaul * without specific prior written permission. 19135048Swpaul * 20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135048Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 31135048Swpaul * 32135048Swpaul * $FreeBSD: head/sys/dev/mii/ciphyreg.h 139749 2005-01-06 01:43:34Z imp $ 33135048Swpaul */ 34135048Swpaul 35135048Swpaul#ifndef _DEV_MII_CIPHYREG_H_ 36135048Swpaul#define _DEV_MII_CIPHYREG_H_ 37135048Swpaul 38135048Swpaul/* 39135048Swpaul * Register definitions for the Cicada CS8201 10/100/1000 gigE copper 40135048Swpaul * PHY, embedded within the VIA Networks VT6122 controller. 41135048Swpaul */ 42135048Swpaul 43135048Swpaul/* Command register */ 44135048Swpaul#define CIPHY_MII_BMCR 0x00 45135048Swpaul#define CIPHY_BMCR_RESET 0x8000 46135048Swpaul#define CIPHY_BMCR_LOOP 0x4000 47135048Swpaul#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */ 48135048Swpaul#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 49135048Swpaul#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */ 50135048Swpaul#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 51135048Swpaul#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */ 52135048Swpaul#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 53135048Swpaul#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 54135048Swpaul 55135048Swpaul#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */ 56135048Swpaul#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */ 57135048Swpaul#define CIPHY_S10 0 /* 10mbps */ 58135048Swpaul 59135048Swpaul/* Status register */ 60135048Swpaul#define CIPHY_MII_BMSR 0x01 61135048Swpaul#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */ 62135048Swpaul#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ 63135048Swpaul#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ 64135048Swpaul#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ 65135048Swpaul#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ 66135048Swpaul#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ 67135048Swpaul#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ 68135048Swpaul#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 69135048Swpaul#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 70135048Swpaul#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 71135048Swpaul#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ 72135048Swpaul#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 73135048Swpaul#define CIPHY_BMSR_LINK 0x0004 /* Link status */ 74135048Swpaul#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 75135048Swpaul#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */ 76135048Swpaul 77135048Swpaul/* PHY ID registers */ 78135048Swpaul#define CIPHY_MII_PHYIDR1 0x02 79135048Swpaul#define CIPHY_MII_PHYIDR2 0x03 80135048Swpaul 81135048Swpaul/* Autoneg advertisement */ 82135048Swpaul#define CIPHY_MII_ANAR 0x04 83135048Swpaul#define CIPHY_ANAR_NP 0x8000 /* Next page */ 84135048Swpaul#define CIPHY_ANAR_RF 0x2000 /* Remote fault */ 85135048Swpaul#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 86135048Swpaul#define CIPHY_ANAR_PC 0x0400 /* Pause capable */ 87135048Swpaul#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */ 88135048Swpaul#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 89135048Swpaul#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */ 90135048Swpaul#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 91135048Swpaul#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */ 92135048Swpaul#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */ 93135048Swpaul 94135048Swpaul/* Autoneg link partner ability */ 95135048Swpaul#define CIPHY_MII_ANLPAR 0x05 96135048Swpaul#define CIPHY_ANLPAR_NP 0x8000 /* Next page */ 97135048Swpaul#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */ 98135048Swpaul#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */ 99135048Swpaul#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 100135048Swpaul#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */ 101135048Swpaul#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ 102135048Swpaul#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ 103135048Swpaul#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */ 104135048Swpaul#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ 105135048Swpaul#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */ 106135048Swpaul#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */ 107135048Swpaul 108135048Swpaul#define CIPHY_SEL_TYPE 0x0001 /* ethernet */ 109135048Swpaul 110135048Swpaul/* Antoneg expansion register */ 111135048Swpaul#define CIPHY_MII_ANER 0x06 112135048Swpaul#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 113135048Swpaul#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 114135048Swpaul#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */ 115135048Swpaul#define CIPHY_ANER_RX 0x0002 /* Next page received */ 116135048Swpaul#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 117135048Swpaul 118135048Swpaul/* Autoneg next page transmit regisyer */ 119135048Swpaul#define CIPHY_MII_NEXTP 0x07 120135048Swpaul#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */ 121135048Swpaul#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */ 122135048Swpaul#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */ 123135048Swpaul#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */ 124135048Swpaul#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */ 125135048Swpaul 126135048Swpaul/* Autoneg link partner next page receive register */ 127135048Swpaul#define CIPHY_MII_NEXTP_LP 0x08 128135048Swpaul#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */ 129135048Swpaul#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */ 130135048Swpaul#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */ 131135048Swpaul#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */ 132135048Swpaul#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */ 133135048Swpaul 134135048Swpaul/* 1000BT control register */ 135135048Swpaul#define CIPHY_MII_1000CTL 0x09 136135048Swpaul#define CIPHY_1000CTL_TST 0xE000 /* test modes */ 137135048Swpaul#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */ 138135048Swpaul#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */ 139135048Swpaul#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 140135048Swpaul#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 141135048Swpaul#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 142135048Swpaul 143135048Swpaul#define CIPHY_TEST_TX_JITTER 0x2000 144135048Swpaul#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000 145135048Swpaul#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000 146135048Swpaul#define CIPHY_TEST_TX_DISTORTION 0x8000 147135048Swpaul 148135048Swpaul/* 1000BT status register */ 149135048Swpaul#define CIPHY_MII_1000STS 0x0A 150135048Swpaul#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 151135048Swpaul#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */ 152135048Swpaul#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */ 153135048Swpaul#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 154135048Swpaul#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 155135048Swpaul#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 156135048Swpaul#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */ 157135048Swpaul 158135048Swpaul#define CIPHY_MII_EXTSTS 0x0F /* Extended status */ 159135048Swpaul#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 160135048Swpaul#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 161135048Swpaul#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 162135048Swpaul#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 163135048Swpaul 164135048Swpaul/* 1000BT status extension register #1 */ 165135048Swpaul#define CIPHY_MII_1000STS1 0x0F 166135048Swpaul#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */ 167135048Swpaul#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */ 168135048Swpaul#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */ 169135048Swpaul#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */ 170135048Swpaul 171135048Swpaul/* Vendor-specific PHY registers */ 172135048Swpaul 173135048Swpaul/* 100baseTX status extention register */ 174135048Swpaul#define CIPHY_MII_100STS 0x10 175135048Swpaul#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */ 176135048Swpaul#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */ 177135048Swpaul#define CIPHY_100STS_DISC 0x2000 /* disconnect state */ 178135048Swpaul#define CIPHY_100STS_LINK 0x1000 /* current link state */ 179135048Swpaul#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */ 180135048Swpaul#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */ 181135048Swpaul#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */ 182135048Swpaul#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */ 183135048Swpaul 184135048Swpaul/* 1000BT status extention register #2 */ 185135048Swpaul#define CIPHY_MII_1000STS2 0x11 186135048Swpaul#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */ 187135048Swpaul#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */ 188135048Swpaul#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */ 189135048Swpaul#define CIPHY_1000STS2_LINK 0x1000 /* current link state */ 190135048Swpaul#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */ 191135048Swpaul#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */ 192135048Swpaul#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */ 193135048Swpaul#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */ 194135048Swpaul#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */ 195135048Swpaul#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */ 196135048Swpaul 197135048Swpaul/* Bypass control register */ 198135048Swpaul#define CIPHY_MII_BYPASS 0x12 199135048Swpaul#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */ 200135048Swpaul#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */ 201135048Swpaul#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */ 202135048Swpaul#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */ 203135048Swpaul#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */ 204135048Swpaul#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */ 205135048Swpaul#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */ 206135048Swpaul#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */ 207135048Swpaul#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */ 208135048Swpaul#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */ 209135048Swpaul#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */ 210135048Swpaul#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */ 211135048Swpaul#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */ 212135048Swpaul#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */ 213135048Swpaul#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */ 214135048Swpaul 215135048Swpaul/* RX error count register */ 216135048Swpaul#define CIPHY_MII_RXERR 0x13 217135048Swpaul 218135048Swpaul/* False carrier sense count register */ 219135048Swpaul#define CIPHY_MII_FCSERR 0x14 220135048Swpaul 221135048Swpaul/* Ddisconnect error counter */ 222135048Swpaul#define CIPHY_MII_DISCERR 0x15 223135048Swpaul 224135048Swpaul/* 10baseT control/status register */ 225135048Swpaul#define CIPHY_MII_10BTCSR 0x16 226135048Swpaul#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */ 227135048Swpaul#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */ 228135048Swpaul#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */ 229135048Swpaul#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */ 230135048Swpaul#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */ 231135048Swpaul#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */ 232135048Swpaul#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */ 233135048Swpaul#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */ 234135048Swpaul#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */ 235135048Swpaul#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */ 236135048Swpaul 237135048Swpaul#define CIPHY_SQUELCH_300MV 0x0000 238135048Swpaul#define CIPHY_SQUELCH_197MV 0x0400 239135048Swpaul#define CIPHY_SQUELCH_450MV 0x0800 240135048Swpaul#define CIPHY_SQUELCH_RSVD 0x0C00 241135048Swpaul 242135048Swpaul#define CIPHY_ITRIM_PLUS2 0x0000 243135048Swpaul#define CIPHY_ITRIM_PLUS4 0x0008 244135048Swpaul#define CIPHY_ITRIM_PLUS6 0x0010 245135048Swpaul#define CIPHY_ITRIM_PLUS6_ 0x0018 246135048Swpaul#define CIPHY_ITRIM_MINUS4 0x0020 247135048Swpaul#define CIPHY_ITRIM_MINUS4_ 0x0028 248135048Swpaul#define CIPHY_ITRIM_MINUS2 0x0030 249135048Swpaul#define CIPHY_ITRIM_ZERO 0x0038 250135048Swpaul 251135048Swpaul/* Extended PHY control register #1 */ 252135048Swpaul#define CIPHY_MII_ECTL1 0x17 253135048Swpaul#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */ 254135048Swpaul 255135048Swpaul/* Extended PHY control register #2 */ 256135048Swpaul#define CIPHY_MII_ECTL2 0x18 257135048Swpaul#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */ 258135048Swpaul#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */ 259135048Swpaul#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */ 260135048Swpaul#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */ 261135048Swpaul 262135048Swpaul#define CIPHY_CABLELEN_0TO10M 0x0000 263135048Swpaul#define CIPHY_CABLELEN_10TO20M 0x0002 264135048Swpaul#define CIPHY_CABLELEN_20TO40M 0x0004 265135048Swpaul#define CIPHY_CABLELEN_40TO80M 0x0006 266135048Swpaul#define CIPHY_CABLELEN_80TO100M 0x0008 267135048Swpaul#define CIPHY_CABLELEN_100TO140M 0x000A 268135048Swpaul#define CIPHY_CABLELEN_140TO180M 0x000C 269135048Swpaul#define CIPHY_CABLELEN_OVER180M 0x000E 270135048Swpaul 271135048Swpaul/* Interrupt mask register */ 272135048Swpaul#define CIPHY_MII_IMR 0x19 273135048Swpaul#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */ 274135048Swpaul#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */ 275135048Swpaul#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */ 276135048Swpaul#define CIPHY_IMR_DPX 0x1000 /* duplex change event */ 277135048Swpaul#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */ 278135048Swpaul#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */ 279135048Swpaul#define CIPHY_IMR_NPRX 0x0200 /* page received event */ 280135048Swpaul#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */ 281135048Swpaul#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */ 282135048Swpaul#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */ 283135048Swpaul#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */ 284135048Swpaul#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */ 285135048Swpaul#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */ 286135048Swpaul#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */ 287135048Swpaul#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ 288135048Swpaul#define CIPHY_IMR_RXERR 0x0001 /* RX error event */ 289135048Swpaul 290135048Swpaul/* Interrupt status register */ 291135048Swpaul#define CIPHY_MII_ISR 0x1A 292135048Swpaul#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */ 293135048Swpaul#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */ 294135048Swpaul#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */ 295135048Swpaul#define CIPHY_ISR_DPX 0x1000 /* duplex change event */ 296135048Swpaul#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */ 297135048Swpaul#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */ 298135048Swpaul#define CIPHY_ISR_NPRX 0x0200 /* page received event */ 299135048Swpaul#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */ 300135048Swpaul#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */ 301135048Swpaul#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */ 302135048Swpaul#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */ 303135048Swpaul#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */ 304135048Swpaul#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */ 305135048Swpaul#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */ 306135048Swpaul#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ 307135048Swpaul#define CIPHY_ISR_RXERR 0x0001 /* RX error event */ 308135048Swpaul 309135048Swpaul/* LED control register */ 310135048Swpaul#define CIPHY_MII_LED 0x1B 311135048Swpaul#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */ 312135048Swpaul#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */ 313135048Swpaul#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */ 314135048Swpaul#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */ 315135048Swpaul#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */ 316135048Swpaul#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */ 317135048Swpaul#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */ 318135048Swpaul#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */ 319135048Swpaul#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */ 320135048Swpaul#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */ 321135048Swpaul#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */ 322135048Swpaul#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */ 323135048Swpaul#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */ 324135048Swpaul 325135048Swpaul/* Auxilliary control and status register */ 326135048Swpaul#define CIPHY_MII_AUXCSR 0x1C 327135048Swpaul#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */ 328135048Swpaul#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */ 329135048Swpaul#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */ 330135048Swpaul#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */ 331135048Swpaul#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */ 332135048Swpaul#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */ 333135048Swpaul#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */ 334135048Swpaul#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */ 335135048Swpaul#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */ 336135048Swpaul#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */ 337135048Swpaul#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */ 338135048Swpaul#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */ 339135048Swpaul 340135048Swpaul#define CIPHY_SPEED10 0x0000 341135048Swpaul#define CIPHY_SPEED100 0x0008 342135048Swpaul#define CIPHY_SPEED1000 0x0010 343135048Swpaul 344135048Swpaul/* Delay skew status register */ 345135048Swpaul#define CIPHY_MII_DSKEW 0x1D 346135048Swpaul#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */ 347135048Swpaul#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */ 348135048Swpaul#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */ 349135048Swpaul#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */ 350135048Swpaul 351135048Swpaul#endif /* _DEV_CIPHY_MIIREG_H_ */ 352