brgphyreg.h revision 83930
159477Swpaul/* 259477Swpaul * Copyright (c) 2000 359477Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 459477Swpaul * 559477Swpaul * Redistribution and use in source and binary forms, with or without 659477Swpaul * modification, are permitted provided that the following conditions 759477Swpaul * are met: 859477Swpaul * 1. Redistributions of source code must retain the above copyright 959477Swpaul * notice, this list of conditions and the following disclaimer. 1059477Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1159477Swpaul * notice, this list of conditions and the following disclaimer in the 1259477Swpaul * documentation and/or other materials provided with the distribution. 1359477Swpaul * 3. All advertising materials mentioning features or use of this software 1459477Swpaul * must display the following acknowledgement: 1559477Swpaul * This product includes software developed by Bill Paul. 1659477Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1759477Swpaul * may be used to endorse or promote products derived from this software 1859477Swpaul * without specific prior written permission. 1959477Swpaul * 2059477Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2159477Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2259477Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2359477Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2459477Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2559477Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2659477Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2759477Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2859477Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2959477Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3059477Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3159477Swpaul * 3259477Swpaul * $FreeBSD: head/sys/dev/mii/brgphyreg.h 83930 2001-09-25 16:41:56Z wpaul $ 3359477Swpaul */ 3459477Swpaul 3559477Swpaul#ifndef _DEV_MII_BRGPHYREG_H_ 3659477Swpaul#define _DEV_MII_BRGPHYREG_H_ 3759477Swpaul 3859477Swpaul/* 3959477Swpaul * Broadcom BCM5400 registers 4059477Swpaul */ 4159477Swpaul 4259477Swpaul#define BRGPHY_MII_BMCR 0x00 4359477Swpaul#define BRGPHY_BMCR_RESET 0x8000 4459477Swpaul#define BRGPHY_BMCR_LOOP 0x4000 4559477Swpaul#define BRGPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */ 4659477Swpaul#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 4759477Swpaul#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 4859477Swpaul#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ 4959477Swpaul#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ 5059477Swpaul#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 5159477Swpaul#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 5259477Swpaul#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ 5359477Swpaul 5459477Swpaul#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 5559477Swpaul#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 5659477Swpaul#define BRGPHY_S10 0 /* 10mbps */ 5759477Swpaul 5859477Swpaul#define BRGPHY_MII_BMSR 0x01 5959477Swpaul#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 6059477Swpaul#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 6159477Swpaul#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 6259477Swpaul#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ 6359477Swpaul#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 6459477Swpaul#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ 6559477Swpaul#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 6659477Swpaul#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ 6759477Swpaul 6859477Swpaul#define BRGPHY_MII_ANAR 0x04 6959477Swpaul#define BRGPHY_ANAR_NP 0x8000 /* Next page */ 7059477Swpaul#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ 7183029Swpaul#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ 7259477Swpaul#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ 7359477Swpaul#define BRGPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */ 7459477Swpaul 7559477Swpaul#define BRGPHY_MII_ANLPAR 0x05 7659477Swpaul#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ 7759477Swpaul#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ 7883029Swpaul#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ 7959477Swpaul#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ 8059477Swpaul#define BRGPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */ 8159477Swpaul 8259477Swpaul#define BRGPHY_SEL_TYPE 0x0001 /* ethernet */ 8359477Swpaul 8459477Swpaul#define BRGPHY_MII_ANER 0x06 8559477Swpaul#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ 8659477Swpaul#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ 8759477Swpaul#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ 8859477Swpaul#define BRGPHY_ANER_RX 0x0002 /* Next page received */ 8959477Swpaul#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ 9059477Swpaul 9159477Swpaul#define BRGPHY_MII_NEXTP 0x07 /* Next page */ 9259477Swpaul 9359477Swpaul#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ 9459477Swpaul 9559477Swpaul#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ 9659477Swpaul#define BRGPHY_1000CTL_TST 0xE000 /* test modes */ 9759477Swpaul#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ 9859477Swpaul#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ 9959477Swpaul#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ 10059477Swpaul#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ 10159477Swpaul#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ 10259477Swpaul 10359477Swpaul#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ 10459477Swpaul#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ 10559477Swpaul#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ 10659477Swpaul#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ 10759477Swpaul#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ 10859477Swpaul#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ 10959477Swpaul#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ 11059477Swpaul#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ 11159477Swpaul 11259477Swpaul#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ 11359477Swpaul#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ 11459477Swpaul#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ 11559477Swpaul#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ 11659477Swpaul#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ 11759477Swpaul 11859477Swpaul#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 11959477Swpaul#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 12059477Swpaul#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 12159477Swpaul#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disable d*/ 12259477Swpaul#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 12359477Swpaul#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 12459477Swpaul#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 12559477Swpaul#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 12659477Swpaul#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 12759477Swpaul#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 12859477Swpaul#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 12959477Swpaul#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 13059477Swpaul#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 13159477Swpaul#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 13259477Swpaul#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 13359477Swpaul#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 13459477Swpaul#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 13559477Swpaul 13659477Swpaul#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 13759477Swpaul#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 13859477Swpaul#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 13959477Swpaul#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 14059477Swpaul#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 14159477Swpaul#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 14259477Swpaul#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 14359477Swpaul#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 14459477Swpaul#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 14559477Swpaul#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 14659477Swpaul#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 14759477Swpaul#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 14859477Swpaul#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 14959477Swpaul#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 15059477Swpaul#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 15159477Swpaul 15259477Swpaul#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 15359477Swpaul 15459477Swpaul#define BRGPHY_MII_FCERRCNT 0x13 /* false carrier sense counter */ 15559477Swpaul#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 15659477Swpaul 15759477Swpaul#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 15859477Swpaul#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 15959477Swpaul#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 16059477Swpaul 16183930Swpaul#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 16283930Swpaul 16383930Swpaul#define BGGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 16483930Swpaul 16583930Swpaul#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 16683930Swpaul#define BRGPHY_DSP_AGC_A 0x00 16783930Swpaul#define BRGPHY_DSP_AGC_B 0x01 16883930Swpaul#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 16983930Swpaul#define BRGPHY_DSP_SOFT_DECISION 0x03 17083930Swpaul#define BRGPHY_DSP_PHASE_REG 0x04 17183930Swpaul#define BRGPHY_DSP_SKEW 0x05 17283930Swpaul#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 17383930Swpaul#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 17483930Swpaul#define BRGPHY_DSP_LAST_ECHO 0x08 17583930Swpaul#define BRGPHY_DSP_FREQUENCY 0x09 17683930Swpaul#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 17783930Swpaul#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 17883930Swpaul 17983930Swpaul#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 18083930Swpaul#define BRGPHY_DSP_FILTER_FEXT3 0x0B00 18183930Swpaul#define BRGPHY_DSP_FILTER_FEXT2 0x0A00 18283930Swpaul#define BRGPHY_DSP_FILTER_FEXT1 0x0900 18383930Swpaul#define BRGPHY_DSP_FILTER_FEXT0 0x0800 18483930Swpaul#define BRGPHY_DSP_FILTER_NEXT3 0x0700 18583930Swpaul#define BRGPHY_DSP_FILTER_NEXT2 0x0600 18683930Swpaul#define BRGPHY_DSP_FILTER_NEXT1 0x0500 18783930Swpaul#define BRGPHY_DSP_FILTER_NEXT0 0x0400 18883930Swpaul#define BRGPHY_DSP_FILTER_ECHO 0x0300 18983930Swpaul#define BRGPHY_DSP_FILTER_DFE 0x0200 19083930Swpaul#define BRGPHY_DSP_FILTER_FFE 0x0100 19183930Swpaul 19283930Swpaul#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 19383930Swpaul 19483930Swpaul#define BRGPHY_DSP_SEL_CH_0 0x0000 19583930Swpaul#define BRGPHY_DSP_SEL_CH_1 0x2000 19683930Swpaul#define BRGPHY_DSP_SEL_CH_2 0x4000 19783930Swpaul#define BRGPHY_DSP_SEL_CH_3 0x6000 19883930Swpaul 19959477Swpaul#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 20059477Swpaul#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 20159477Swpaul#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 20259477Swpaul#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 20359477Swpaul#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 20459477Swpaul#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 20559477Swpaul#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 20659477Swpaul 20759477Swpaul#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 20859477Swpaul#define BRGPHY_AUXSTS_ACOMP 0x8000 /* autoneg complete */ 20959477Swpaul#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* autoneg complete ack */ 21059477Swpaul#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* autoneg complete ack detect */ 21159477Swpaul#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* autoneg next page wait */ 21259477Swpaul#define BRGPHY_AUXSTS_AN_RES 0x0700 /* AN HDC */ 21359477Swpaul#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 21459477Swpaul#define BRGPHY_AUXSTS_RF 0x0040 /* remote fault */ 21559477Swpaul#define BRGPHY_AUXSTS_ANP_R 0x0020 /* AN page received */ 21659477Swpaul#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */ 21759477Swpaul#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */ 21859477Swpaul#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 21959477Swpaul#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 22059477Swpaul#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 22159477Swpaul 22259477Swpaul#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 22359477Swpaul#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 22483029Swpaul#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 22583029Swpaul#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 22683029Swpaul#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 22783029Swpaul#define BRGPHY_RES_10HD 0x0200 /* 10baseT full duplex */ 22883029Swpaul#define BRGPHY_RES_10FD 0x0100 /* 10baseT half duplex */ 22959477Swpaul 23059477Swpaul#define BRGPHY_MII_ISR 0x1A /* interrupt status */ 23159477Swpaul#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 23259477Swpaul#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 23359477Swpaul#define BRGPHY_ISR_HCT 0x1000 /* counter above 32K */ 23459477Swpaul#define BRGPHY_ISR_LCT 0x0800 /* all counter below 128 */ 23559477Swpaul#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 23659477Swpaul#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 23759477Swpaul#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 23859477Swpaul#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 23959477Swpaul#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 24059477Swpaul#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 24159477Swpaul#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 24259477Swpaul#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 24359477Swpaul#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 24459477Swpaul#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 24559477Swpaul#define BRGPHY_ISR_CRCERR 0x0001 /* CEC error */ 24659477Swpaul 24759477Swpaul#define BRGPHY_MII_IMR 0x1B /* interrupt mask */ 24859477Swpaul#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 24959477Swpaul#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 25059477Swpaul#define BRGPHY_IMR_HCT 0x1000 /* counter above 32K */ 25159477Swpaul#define BRGPHY_IMR_LCT 0x0800 /* all counter below 128 */ 25259477Swpaul#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 25359477Swpaul#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 25459477Swpaul#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 25559477Swpaul#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 25659477Swpaul#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 25759477Swpaul#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 25859477Swpaul#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 25959477Swpaul#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 26059477Swpaul#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 26159477Swpaul#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 26259477Swpaul#define BRGPHY_IMR_CRCERR 0x0001 /* CEC error */ 26359477Swpaul 26459477Swpaul#define BRGPHY_INTRS \ 26559477Swpaul ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 26659477Swpaul 26759477Swpaul#endif /* _DEV_BRGPHY_MIIREG_H_ */ 268