atphy.c revision 213364 
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/mii/atphy.c 213364 2010-10-02 18:53:12Z marius $");
30
31/*
32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY.
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/socket.h>
40#include <sys/bus.h>
41
42#include <net/if.h>
43#include <net/if_media.h>
44
45#include <dev/mii/mii.h>
46#include <dev/mii/miivar.h>
47#include "miidevs.h"
48
49#include <dev/mii/atphyreg.h>
50
51#include "miibus_if.h"
52
53static int atphy_probe(device_t);
54static int atphy_attach(device_t);
55
56struct atphy_softc {
57	struct mii_softc mii_sc;
58	int mii_oui;
59	int mii_model;
60	int mii_rev;
61};
62
63static device_method_t atphy_methods[] = {
64	/* Device interface. */
65	DEVMETHOD(device_probe,		atphy_probe),
66	DEVMETHOD(device_attach,	atphy_attach),
67	DEVMETHOD(device_detach,	mii_phy_detach),
68	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
69	{ NULL, NULL }
70};
71
72static devclass_t atphy_devclass;
73static driver_t atphy_driver = {
74	"atphy",
75	atphy_methods,
76	sizeof(struct atphy_softc)
77};
78
79DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
80
81static int	atphy_service(struct mii_softc *, struct mii_data *, int);
82static void	atphy_status(struct mii_softc *);
83static void	atphy_reset(struct mii_softc *);
84static uint16_t	atphy_anar(struct ifmedia_entry *);
85static int	atphy_auto(struct mii_softc *);
86
87static const struct mii_phydesc atphys[] = {
88	MII_PHY_DESC(ATHEROS, F1),
89	MII_PHY_DESC(ATHEROS, F1_7),
90	MII_PHY_DESC(ATHEROS, F2),
91	MII_PHY_END
92};
93
94static int
95atphy_probe(device_t dev)
96{
97
98	return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
99}
100
101static int
102atphy_attach(device_t dev)
103{
104	struct atphy_softc *asc;
105	struct mii_softc *sc;
106	struct mii_attach_args *ma;
107	struct mii_data *mii;
108
109	asc = device_get_softc(dev);
110	sc = &asc->mii_sc;
111	ma = device_get_ivars(dev);
112	sc->mii_dev = device_get_parent(dev);
113	mii = ma->mii_data;
114	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
115
116	sc->mii_inst = mii->mii_instance++;
117	sc->mii_phy = ma->mii_phyno;
118	sc->mii_service = atphy_service;
119	sc->mii_pdata = mii;
120
121	asc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
122	asc->mii_model = MII_MODEL(ma->mii_id2);
123	asc->mii_rev = MII_REV(ma->mii_id2);
124	if (bootverbose)
125		device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
126		    asc->mii_oui, asc->mii_model, asc->mii_rev);
127
128	atphy_reset(sc);
129
130	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
131	if (sc->mii_capabilities & BMSR_EXTSTAT)
132		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
133	device_printf(dev, " ");
134	mii_phy_add_media(sc);
135	printf("\n");
136
137	MIIBUS_MEDIAINIT(sc->mii_dev);
138	return (0);
139}
140
141static int
142atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
143{
144	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
145	uint16_t anar, bmcr, bmsr;
146
147	switch (cmd) {
148	case MII_POLLSTAT:
149		break;
150
151	case MII_MEDIACHG:
152		/*
153		 * If the interface is not up, don't do anything.
154		 */
155		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
156			break;
157
158		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
159		    IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
160			atphy_auto(sc);
161			break;
162		}
163
164		bmcr = 0;
165		switch (IFM_SUBTYPE(ife->ifm_media)) {
166		case IFM_100_TX:
167			bmcr = BMCR_S100;
168			break;
169		case IFM_10_T:
170			bmcr = BMCR_S10;
171			break;
172		case IFM_NONE:
173			bmcr = PHY_READ(sc, MII_BMCR);
174			/*
175			 * XXX
176			 * Due to an unknown reason powering down PHY resulted
177			 * in unexpected results such as inaccessbility of
178			 * hardware of freshly rebooted system. Disable
179			 * powering down PHY until I got more information for
180			 * Attansic/Atheros PHY hardwares.
181			 */
182			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
183			goto done;
184		default:
185			return (EINVAL);
186		}
187
188		anar = atphy_anar(ife);
189		if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
190			bmcr |= BMCR_FDX;
191			/* Enable pause. */
192			anar |= (3 << 10);
193		}
194
195		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
196		    EXTSR_1000THDX)) != 0)
197			PHY_WRITE(sc, MII_100T2CR, 0);
198		PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
199
200		/*
201		 * Reset the PHY so all changes take effect.
202		 */
203		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
204		    BMCR_STARTNEG);
205done:
206		break;
207
208	case MII_TICK:
209		/*
210		 * Is the interface even up?
211		 */
212		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
213			return (0);
214
215		/*
216		 * Only used for autonegotiation.
217		 */
218		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
219			sc->mii_ticks = 0;
220			break;
221		}
222
223		/*
224		 * check for link.
225		 * Read the status register twice; BMSR_LINK is latch-low.
226		 */
227		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
228		if (bmsr & BMSR_LINK) {
229			sc->mii_ticks = 0;
230			break;
231		}
232
233		/* Announce link loss right after it happens. */
234		if (sc->mii_ticks++ == 0)
235			break;
236		if (sc->mii_ticks <= sc->mii_anegticks)
237			return (0);
238
239		sc->mii_ticks = 0;
240		atphy_auto(sc);
241		break;
242	}
243
244	/* Update the media status. */
245	atphy_status(sc);
246
247	/* Callback if something changed. */
248	mii_phy_update(sc, cmd);
249	return (0);
250}
251
252static void
253atphy_status(struct mii_softc *sc)
254{
255	struct mii_data *mii = sc->mii_pdata;
256	uint32_t bmsr, bmcr, ssr;
257
258	mii->mii_media_status = IFM_AVALID;
259	mii->mii_media_active = IFM_ETHER;
260
261	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
262	if ((bmsr & BMSR_LINK) != 0)
263		mii->mii_media_status |= IFM_ACTIVE;
264
265	bmcr = PHY_READ(sc, MII_BMCR);
266	if ((bmcr & BMCR_ISO) != 0) {
267		mii->mii_media_active |= IFM_NONE;
268		mii->mii_media_status = 0;
269		return;
270	}
271
272	if ((bmcr & BMCR_LOOP) != 0)
273		mii->mii_media_active |= IFM_LOOP;
274
275	ssr = PHY_READ(sc, ATPHY_SSR);
276	if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
277		/* Erg, still trying, I guess... */
278		mii->mii_media_active |= IFM_NONE;
279		return;
280	}
281
282	switch (ssr & ATPHY_SSR_SPEED_MASK) {
283	case ATPHY_SSR_1000MBS:
284		mii->mii_media_active |= IFM_1000_T;
285		/*
286		 * atphy(4) got a valid link so reset mii_ticks.
287		 * Resetting mii_ticks is needed in order to
288		 * detect link loss after auto-negotiation.
289		 */
290		sc->mii_ticks = 0;
291		break;
292	case ATPHY_SSR_100MBS:
293		mii->mii_media_active |= IFM_100_TX;
294		sc->mii_ticks = 0;
295		break;
296	case ATPHY_SSR_10MBS:
297		mii->mii_media_active |= IFM_10_T;
298		sc->mii_ticks = 0;
299		break;
300	default:
301		mii->mii_media_active |= IFM_NONE;
302		return;
303	}
304
305	if ((ssr & ATPHY_SSR_DUPLEX) != 0)
306		mii->mii_media_active |= IFM_FDX;
307	else
308		mii->mii_media_active |= IFM_HDX;
309
310	/* XXX Master/Slave, Flow-control */
311}
312
313static void
314atphy_reset(struct mii_softc *sc)
315{
316	struct atphy_softc *asc;
317	uint32_t reg;
318	int i;
319
320	asc = (struct atphy_softc *)sc;
321
322	/* Take PHY out of power down mode. */
323	PHY_WRITE(sc, 29, 0x29);
324	PHY_WRITE(sc, 30, 0);
325
326	reg = PHY_READ(sc, ATPHY_SCR);
327	/* Enable automatic crossover. */
328	reg |= ATPHY_SCR_AUTO_X_MODE;
329	/* Disable power down. */
330	reg &= ~ATPHY_SCR_MAC_PDOWN;
331	/* Enable CRS on Tx. */
332	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
333	/* Auto correction for reversed cable polarity. */
334	reg |= ATPHY_SCR_POLARITY_REVERSAL;
335	PHY_WRITE(sc, ATPHY_SCR, reg);
336
337	/* Workaround F1 bug to reset phy. */
338	atphy_auto(sc);
339
340	for (i = 0; i < 1000; i++) {
341		DELAY(1);
342		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
343			break;
344	}
345}
346
347static uint16_t
348atphy_anar(struct ifmedia_entry *ife)
349{
350	uint16_t anar;
351
352	anar = 0;
353	switch (IFM_SUBTYPE(ife->ifm_media)) {
354	case IFM_AUTO:
355		anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
356		return (anar);
357	case IFM_1000_T:
358		return (anar);
359	case IFM_100_TX:
360		anar |= ANAR_TX;
361		break;
362	case IFM_10_T:
363		anar |= ANAR_10;
364		break;
365	default:
366		return (0);
367	}
368
369	if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
370		if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
371			anar |= ANAR_TX_FD;
372		else
373			anar |= ANAR_10_FD;
374	}
375
376	return (anar);
377}
378
379static int
380atphy_auto(struct mii_softc *sc)
381{
382	uint16_t anar;
383
384	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities);
385	PHY_WRITE(sc, MII_ANAR, anar | (3 << 10) | ANAR_CSMA);
386	if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
387		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
388		    GTCR_ADV_1000THDX);
389	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
390
391	return (EJUSTRETURN);
392}
393