1139749Simp/*- 250983Swpaul * Copyright (c) 1997, 1998, 1999 350983Swpaul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 450983Swpaul * 550983Swpaul * Redistribution and use in source and binary forms, with or without 650983Swpaul * modification, are permitted provided that the following conditions 750983Swpaul * are met: 850983Swpaul * 1. Redistributions of source code must retain the above copyright 950983Swpaul * notice, this list of conditions and the following disclaimer. 1050983Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150983Swpaul * notice, this list of conditions and the following disclaimer in the 1250983Swpaul * documentation and/or other materials provided with the distribution. 1350983Swpaul * 3. All advertising materials mentioning features or use of this software 1450983Swpaul * must display the following acknowledgement: 1550983Swpaul * This product includes software developed by Bill Paul. 1650983Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750983Swpaul * may be used to endorse or promote products derived from this software 1850983Swpaul * without specific prior written permission. 1950983Swpaul * 2050983Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150983Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250983Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350983Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450983Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550983Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650983Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750983Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850983Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950983Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050983Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150983Swpaul * 3250983Swpaul * $FreeBSD: releng/11.0/sys/dev/mii/amphyreg.h 139749 2005-01-06 01:43:34Z imp $ 3350983Swpaul */ 3450983Swpaul 3550983Swpaul#ifndef _DEV_MII_AMTPHYREG_H_ 3650983Swpaul#define _DEV_MII_AMTPHYREG_H_ 3750983Swpaul 3850983Swpaul/* 3950983Swpaul * AMD Am79C873 registers. 4050983Swpaul */ 4150983Swpaul 4250983Swpaul 4350983Swpaul#define MII_AMPHY_DSCR 0x10 /* Specified configuration register */a 4450983Swpaul#define DSCR_BP4B5B 0x8000 /* Bypass 4B5B encoding */ 4550983Swpaul#define DSCR_BPSCR 0x4000 /* Bypass scrambler */ 4650983Swpaul#define DSCR_BPALIGN 0x2000 /* Bypass symbol alignment */ 4750983Swpaul#define DSCR_REPEATER 0x0800 /* Repeater mode */ 4850983Swpaul#define DSCR_TX 0x0400 /* TX/FX mode control */ 4950983Swpaul#define DSCR_UTP 0x0200 /* UTP/STP mode control */ 5050983Swpaul#define DSCR_CLK25MDIS 0x0100 /* CLK25M disable */ 5150983Swpaul#define DSCR_FGLNKTX 0x0080 /* Force good link at 100baseTX */ 5250983Swpaul#define DSCR_LINKLEDCTL 0x0020 /* Link LED control */ 5350983Swpaul#define DSCR_FDXLEDCTL 0x0010 /* FDX LED control */ 5450983Swpaul#define DSCR_SMRTS 0x0008 /* Reset state machine */ 5550983Swpaul#define DSCR_MFPSC 0x0004 /* Preamble surpression control */ 5650983Swpaul#define DSCR_SLEEP 0x0002 /* Sleep mode */ 5750983Swpaul#define DSCR_RLOUT 0x0001 /* Remote loopout control */ 5850983Swpaul 5950983Swpaul#define MII_AMPHY_DSCSR 0x11 /* Specified configuration and status */ 6050983Swpaul#define DSCSR_100FDX 0x8000 /* 100MBps full duplex */ 6150983Swpaul#define DSCSR_100HDX 0x4000 /* 100Mbps half duplex */ 6250983Swpaul#define DSCSR_10FDX 0x2000 /* 10Mbps full duplex */ 6350983Swpaul#define DSCSR_10HDX 0x1000 /* 10Mbps half duplex */ 6450983Swpaul#define DSCSR_PADDR 0x01F0 /* PHY address */ 6550983Swpaul#define DSCSR_ASTAT 0x000F /* Autonegotiation status */ 6650983Swpaul 6750983Swpaul#define ASTAT_COMPLETE 0x8 6850983Swpaul#define ASTAT_PDLINK_READY_FAIL 0x7 6950983Swpaul#define ASTAT_PDLINK_READY 0x6 7050983Swpaul#define ASTAT_CONSTMATCH_FAIL 0x5 7150983Swpaul#define ASTAT_CONSTMATCH 0x4 7250983Swpaul#define ASTAT_ACKMATCH_FAIL 0x3 7350983Swpaul#define ASTAT_ACKMATCH 0x2 7450983Swpaul#define ASTAT_ABILITYMATCH 0x1 7550983Swpaul#define ASTAT_IDLE 0x0 7650983Swpaul 7750983Swpaul#define MII_AMPHY_T10CSRSCR 0x12 /* 10baseT configuration/status */ 7850983Swpaul#define T10CSRSCR_LPEN 0x4000 /* Link pulse enable */ 7950983Swpaul#define T10CSRSCR_HBE 0x2000 /* Heartbeat enable */ 8050983Swpaul#define T10CSRSCR_JABEN 0x0800 /* Jabber enable */ 8150983Swpaul#define T10CSRSCR_SER 0x0400 /* Serial mode enable */ 8250983Swpaul#define T10CSRSCR_POLR 0x0001 /* Polarity reversed */ 8350983Swpaul 8450983Swpaul#endif /* _DEV_MII_AMTPHYREG_H_ */ 85