1177595Sweongyo/*- 2177595Sweongyo * Copyright (c) 2007 Marvell Semiconductor, Inc. 3177595Sweongyo * Copyright (c) 2007 Sam Leffler, Errno Consulting 4177595Sweongyo * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 5177595Sweongyo * All rights reserved. 6177595Sweongyo * 7177595Sweongyo * Redistribution and use in source and binary forms, with or without 8177595Sweongyo * modification, are permitted provided that the following conditions 9177595Sweongyo * are met: 10177595Sweongyo * 1. Redistributions of source code must retain the above copyright 11177595Sweongyo * notice, this list of conditions and the following disclaimer, 12177595Sweongyo * without modification. 13177595Sweongyo * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14177595Sweongyo * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15177595Sweongyo * redistribution must be conditioned upon including a substantially 16177595Sweongyo * similar Disclaimer requirement for further binary redistribution. 17177595Sweongyo * 18177595Sweongyo * NO WARRANTY 19177595Sweongyo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20177595Sweongyo * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21177595Sweongyo * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22177595Sweongyo * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23177595Sweongyo * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24177595Sweongyo * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25177595Sweongyo * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26177595Sweongyo * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27177595Sweongyo * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28177595Sweongyo * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29177595Sweongyo * THE POSSIBILITY OF SUCH DAMAGES. 30177595Sweongyo */ 31177595Sweongyo 32177595Sweongyo#include <sys/cdefs.h> 33177595Sweongyo#ifdef __FreeBSD__ 34177595Sweongyo__FBSDID("$FreeBSD: releng/11.0/sys/dev/malo/if_malohal.c 267340 2014-06-10 20:25:45Z jhb $"); 35177595Sweongyo#endif 36177595Sweongyo 37177595Sweongyo#include <sys/param.h> 38177595Sweongyo#include <sys/systm.h> 39177595Sweongyo#include <sys/endian.h> 40177595Sweongyo#include <sys/kernel.h> 41257176Sglebius#include <sys/malloc.h> 42177595Sweongyo#include <sys/firmware.h> 43177595Sweongyo#include <sys/socket.h> 44177595Sweongyo 45177595Sweongyo#include <machine/bus.h> 46177595Sweongyo#include <sys/bus.h> 47177595Sweongyo 48177595Sweongyo#include <net/if.h> 49257176Sglebius#include <net/if_var.h> 50177595Sweongyo#include <net/if_dl.h> 51177595Sweongyo#include <net/if_media.h> 52257241Sglebius#include <net/ethernet.h> 53177595Sweongyo 54177595Sweongyo#include <net80211/ieee80211_var.h> 55177595Sweongyo 56177595Sweongyo#include <dev/malo/if_malo.h> 57177595Sweongyo 58177595Sweongyo#define MALO_WAITOK 1 59177595Sweongyo#define MALO_NOWAIT 0 60177595Sweongyo 61177595Sweongyo#define _CMD_SETUP(pCmd, _type, _cmd) do { \ 62177595Sweongyo pCmd = (_type *)&mh->mh_cmdbuf[0]; \ 63177595Sweongyo memset(pCmd, 0, sizeof(_type)); \ 64177595Sweongyo pCmd->cmdhdr.cmd = htole16(_cmd); \ 65177595Sweongyo pCmd->cmdhdr.length = htole16(sizeof(_type)); \ 66177595Sweongyo} while (0) 67177595Sweongyo 68177595Sweongyostatic __inline uint32_t 69177595Sweongyomalo_hal_read4(struct malo_hal *mh, bus_size_t off) 70177595Sweongyo{ 71177595Sweongyo return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); 72177595Sweongyo} 73177595Sweongyo 74177595Sweongyostatic __inline void 75177595Sweongyomalo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val) 76177595Sweongyo{ 77177595Sweongyo bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); 78177595Sweongyo} 79177595Sweongyo 80177595Sweongyostatic void 81177595Sweongyomalo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 82177595Sweongyo{ 83177595Sweongyo bus_addr_t *paddr = (bus_addr_t*) arg; 84177595Sweongyo 85177595Sweongyo KASSERT(error == 0, ("error %u on bus_dma callback", error)); 86177595Sweongyo *paddr = segs->ds_addr; 87177595Sweongyo} 88177595Sweongyo 89177595Sweongyo/* 90177595Sweongyo * Setup for communication with the device. We allocate 91177595Sweongyo * a command buffer and map it for bus dma use. The pci 92177595Sweongyo * device id is used to identify whether the device has 93177595Sweongyo * SRAM on it (in which case f/w download must include a 94177595Sweongyo * memory controller reset). All bus i/o operations happen 95177595Sweongyo * in BAR 1; the driver passes in the tag and handle we need. 96177595Sweongyo */ 97177595Sweongyostruct malo_hal * 98177595Sweongyomalo_hal_attach(device_t dev, uint16_t devid, 99177595Sweongyo bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag) 100177595Sweongyo{ 101177595Sweongyo int error; 102177595Sweongyo struct malo_hal *mh; 103177595Sweongyo 104177595Sweongyo mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO); 105177595Sweongyo if (mh == NULL) 106177595Sweongyo return NULL; 107177595Sweongyo 108177595Sweongyo mh->mh_dev = dev; 109177595Sweongyo mh->mh_ioh = ioh; 110177595Sweongyo mh->mh_iot = iot; 111177595Sweongyo 112177595Sweongyo snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname), 113177595Sweongyo "%s_hal", device_get_nameunit(dev)); 114177595Sweongyo mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF); 115177595Sweongyo 116177595Sweongyo /* 117177595Sweongyo * Allocate the command buffer and map into the address 118177595Sweongyo * space of the h/w. We request "coherent" memory which 119177595Sweongyo * will be uncached on some architectures. 120177595Sweongyo */ 121177595Sweongyo error = bus_dma_tag_create(tag, /* parent */ 122177595Sweongyo PAGE_SIZE, 0, /* alignment, bounds */ 123177595Sweongyo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 124177595Sweongyo BUS_SPACE_MAXADDR, /* highaddr */ 125177595Sweongyo NULL, NULL, /* filter, filterarg */ 126177595Sweongyo MALO_CMDBUF_SIZE, /* maxsize */ 127177595Sweongyo 1, /* nsegments */ 128177595Sweongyo MALO_CMDBUF_SIZE, /* maxsegsize */ 129177595Sweongyo BUS_DMA_ALLOCNOW, /* flags */ 130177595Sweongyo NULL, /* lockfunc */ 131177595Sweongyo NULL, /* lockarg */ 132177595Sweongyo &mh->mh_dmat); 133177595Sweongyo if (error != 0) { 134190550Sweongyo device_printf(dev, "unable to allocate memory for cmd tag, " 135177595Sweongyo "error %u\n", error); 136177595Sweongyo goto fail; 137177595Sweongyo } 138177595Sweongyo 139177595Sweongyo /* allocate descriptors */ 140177595Sweongyo error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf, 141177595Sweongyo BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 142177595Sweongyo &mh->mh_dmamap); 143177595Sweongyo if (error != 0) { 144177595Sweongyo device_printf(dev, "unable to allocate memory for cmd buffer, " 145177595Sweongyo "error %u\n", error); 146177595Sweongyo goto fail; 147177595Sweongyo } 148177595Sweongyo 149177595Sweongyo error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap, 150177595Sweongyo mh->mh_cmdbuf, MALO_CMDBUF_SIZE, 151177595Sweongyo malo_hal_load_cb, &mh->mh_cmdaddr, 152177595Sweongyo BUS_DMA_NOWAIT); 153177595Sweongyo if (error != 0) { 154177595Sweongyo device_printf(dev, "unable to load cmd buffer, error %u\n", 155177595Sweongyo error); 156177595Sweongyo goto fail; 157177595Sweongyo } 158177595Sweongyo 159177595Sweongyo return (mh); 160177595Sweongyo 161177595Sweongyofail: 162267340Sjhb if (mh->mh_cmdbuf != NULL) 163267340Sjhb bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, 164267340Sjhb mh->mh_dmamap); 165177595Sweongyo if (mh->mh_dmat) 166177595Sweongyo bus_dma_tag_destroy(mh->mh_dmat); 167190541Sweongyo free(mh, M_DEVBUF); 168177595Sweongyo 169177595Sweongyo return (NULL); 170177595Sweongyo} 171177595Sweongyo 172177595Sweongyo/* 173177595Sweongyo * Low level firmware cmd block handshake support. 174177595Sweongyo */ 175177595Sweongyo 176177595Sweongyostatic void 177177595Sweongyomalo_hal_send_cmd(struct malo_hal *mh) 178177595Sweongyo{ 179177595Sweongyo uint32_t dummy; 180177595Sweongyo 181177595Sweongyo bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 182177595Sweongyo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 183177595Sweongyo 184177595Sweongyo malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 185177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 186177595Sweongyo 187177595Sweongyo malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 188177595Sweongyo MALO_H2ARIC_BIT_DOOR_BELL); 189177595Sweongyo} 190177595Sweongyo 191177595Sweongyostatic int 192177595Sweongyomalo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd) 193177595Sweongyo{ 194177595Sweongyo#define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000 195177595Sweongyo int i; 196177595Sweongyo 197177595Sweongyo for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { 198177595Sweongyo if (mh->mh_cmdbuf[0] == le16toh(cmd)) 199177595Sweongyo return 1; 200177595Sweongyo 201177595Sweongyo DELAY(1 * 1000); 202177595Sweongyo } 203177595Sweongyo 204177595Sweongyo return 0; 205177595Sweongyo#undef MAX_WAIT_FW_COMPLETE_ITERATIONS 206177595Sweongyo} 207177595Sweongyo 208177595Sweongyostatic int 209177595Sweongyomalo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd) 210177595Sweongyo{ 211177595Sweongyo MALO_HAL_LOCK_ASSERT(mh); 212177595Sweongyo 213177595Sweongyo if ((mh->mh_flags & MHF_FWHANG) && 214177595Sweongyo (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) { 215177595Sweongyo device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n", 216177595Sweongyo cmd); 217177595Sweongyo return ENXIO; 218177595Sweongyo } 219177595Sweongyo 220177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 221177595Sweongyo device_printf(mh->mh_dev, "%s: device not present!\n", 222177595Sweongyo __func__); 223177595Sweongyo return EIO; 224177595Sweongyo } 225177595Sweongyo 226177595Sweongyo malo_hal_send_cmd(mh); 227177595Sweongyo if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) { 228177595Sweongyo device_printf(mh->mh_dev, 229177595Sweongyo "timeout waiting for f/w cmd 0x%x\n", cmd); 230177595Sweongyo mh->mh_flags |= MHF_FWHANG; 231177595Sweongyo return ETIMEDOUT; 232177595Sweongyo } 233177595Sweongyo 234177595Sweongyo bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 235177595Sweongyo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 236177595Sweongyo 237177595Sweongyo return 0; 238177595Sweongyo} 239177595Sweongyo 240177595Sweongyostatic int 241177595Sweongyomalo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index) 242177595Sweongyo{ 243177595Sweongyo struct malo_cmd_caltable *cmd; 244177595Sweongyo int ret; 245177595Sweongyo 246177595Sweongyo MALO_HAL_LOCK_ASSERT(mh); 247177595Sweongyo 248177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE); 249177595Sweongyo cmd->annex = annex; 250177595Sweongyo cmd->index = index; 251177595Sweongyo 252177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE); 253177595Sweongyo if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255) 254177595Sweongyo ret = EIO; 255177595Sweongyo return ret; 256177595Sweongyo} 257177595Sweongyo 258177595Sweongyostatic int 259177595Sweongyomalo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal) 260177595Sweongyo{ 261177595Sweongyo const uint8_t *data; 262177595Sweongyo int len; 263177595Sweongyo 264177595Sweongyo MALO_HAL_LOCK(mh); 265177595Sweongyo /* NB: we hold the lock so it's ok to use cmdbuf */ 266177595Sweongyo data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl; 267177595Sweongyo if (malo_hal_get_cal_table(mh, 33, 0) == 0) { 268177595Sweongyo len = (data[2] | (data[3] << 8)) - 12; 269177595Sweongyo /* XXX validate len */ 270177595Sweongyo memcpy(cal->pt_ratetable_20m, &data[12], len); 271177595Sweongyo } 272177595Sweongyo mh->mh_flags |= MHF_CALDATA; 273177595Sweongyo MALO_HAL_UNLOCK(mh); 274177595Sweongyo 275177595Sweongyo return 0; 276177595Sweongyo} 277177595Sweongyo 278177595Sweongyo/* 279177595Sweongyo * Reset internal state after a firmware download. 280177595Sweongyo */ 281177595Sweongyostatic int 282177595Sweongyomalo_hal_resetstate(struct malo_hal *mh) 283177595Sweongyo{ 284177595Sweongyo /* 285177595Sweongyo * Fetch cal data for later use. 286177595Sweongyo * XXX may want to fetch other stuff too. 287177595Sweongyo */ 288177595Sweongyo if ((mh->mh_flags & MHF_CALDATA) == 0) 289177595Sweongyo malo_hal_get_pwrcal_table(mh, &mh->mh_caldata); 290177595Sweongyo return 0; 291177595Sweongyo} 292177595Sweongyo 293177595Sweongyostatic void 294177595Sweongyomalo_hal_fw_reset(struct malo_hal *mh) 295177595Sweongyo{ 296177595Sweongyo 297177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 298177595Sweongyo device_printf(mh->mh_dev, "%s: device not present!\n", 299177595Sweongyo __func__); 300177595Sweongyo return; 301177595Sweongyo } 302177595Sweongyo 303177595Sweongyo malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET); 304177595Sweongyo mh->mh_flags &= ~MHF_FWHANG; 305177595Sweongyo} 306177595Sweongyo 307177595Sweongyostatic void 308177595Sweongyomalo_hal_trigger_pcicmd(struct malo_hal *mh) 309177595Sweongyo{ 310177595Sweongyo uint32_t dummy; 311177595Sweongyo 312177595Sweongyo bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE); 313177595Sweongyo 314177595Sweongyo malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 315177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 316177595Sweongyo 317177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 318177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 319177595Sweongyo 320177595Sweongyo malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 321177595Sweongyo MALO_H2ARIC_BIT_DOOR_BELL); 322177595Sweongyo dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 323177595Sweongyo} 324177595Sweongyo 325177595Sweongyostatic int 326177595Sweongyomalo_hal_waitfor(struct malo_hal *mh, uint32_t val) 327177595Sweongyo{ 328177595Sweongyo int i; 329177595Sweongyo 330177595Sweongyo for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 331177595Sweongyo DELAY(MALO_FW_CHECK_USECS); 332177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val) 333177595Sweongyo return 0; 334177595Sweongyo } 335177595Sweongyo 336177595Sweongyo return -1; 337177595Sweongyo} 338177595Sweongyo 339177595Sweongyo/* 340177595Sweongyo * Firmware block xmit when talking to the boot-rom. 341177595Sweongyo */ 342177595Sweongyostatic int 343177595Sweongyomalo_hal_send_helper(struct malo_hal *mh, int bsize, 344177595Sweongyo const void *data, size_t dsize, int waitfor) 345177595Sweongyo{ 346177595Sweongyo mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 347177595Sweongyo mh->mh_cmdbuf[1] = htole16(bsize); 348177595Sweongyo memcpy(&mh->mh_cmdbuf[4], data , dsize); 349177595Sweongyo 350177595Sweongyo malo_hal_trigger_pcicmd(mh); 351177595Sweongyo 352177595Sweongyo if (waitfor == MALO_NOWAIT) 353177595Sweongyo goto pass; 354177595Sweongyo 355177595Sweongyo /* XXX 2000 vs 200 */ 356177595Sweongyo if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 357177595Sweongyo device_printf(mh->mh_dev, 358177595Sweongyo "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 359177595Sweongyo __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 360177595Sweongyo 361177595Sweongyo return ETIMEDOUT; 362177595Sweongyo } 363177595Sweongyo 364177595Sweongyopass: 365177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 366177595Sweongyo 367177595Sweongyo return (0); 368177595Sweongyo} 369177595Sweongyo 370177595Sweongyostatic int 371177595Sweongyomalo_hal_fwload_helper(struct malo_hal *mh, char *helper) 372177595Sweongyo{ 373177595Sweongyo const struct firmware *fw; 374177595Sweongyo int error; 375177595Sweongyo 376177595Sweongyo fw = firmware_get(helper); 377177595Sweongyo if (fw == NULL) { 378177595Sweongyo device_printf(mh->mh_dev, "could not read microcode %s!\n", 379177595Sweongyo helper); 380177595Sweongyo return (EIO); 381177595Sweongyo } 382177595Sweongyo 383177819Sweongyo device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 384177595Sweongyo helper, fw->datasize); 385177595Sweongyo 386177595Sweongyo error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize, 387177595Sweongyo MALO_WAITOK); 388177595Sweongyo if (error != 0) 389177595Sweongyo goto fail; 390177595Sweongyo 391177595Sweongyo /* tell the card we're done and... */ 392177595Sweongyo error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT); 393177595Sweongyo 394177595Sweongyofail: 395177595Sweongyo firmware_put(fw, FIRMWARE_UNLOAD); 396177595Sweongyo 397177595Sweongyo return (error); 398177595Sweongyo} 399177595Sweongyo 400177595Sweongyo/* 401177595Sweongyo * Firmware block xmit when talking to the 1st-stage loader. 402177595Sweongyo */ 403177595Sweongyostatic int 404177595Sweongyomalo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize, 405177595Sweongyo uint16_t seqnum, int waitfor) 406177595Sweongyo{ 407177595Sweongyo mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 408177595Sweongyo mh->mh_cmdbuf[1] = htole16(dsize); 409177595Sweongyo mh->mh_cmdbuf[2] = htole16(seqnum); 410177595Sweongyo mh->mh_cmdbuf[3] = 0; 411177595Sweongyo memcpy(&mh->mh_cmdbuf[4], data, dsize); 412177595Sweongyo 413177595Sweongyo malo_hal_trigger_pcicmd(mh); 414177595Sweongyo 415177595Sweongyo if (waitfor == MALO_NOWAIT) 416177595Sweongyo goto pass; 417177595Sweongyo 418177595Sweongyo if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 419177595Sweongyo device_printf(mh->mh_dev, 420177595Sweongyo "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 421177595Sweongyo __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 422177595Sweongyo 423177595Sweongyo return ETIMEDOUT; 424177595Sweongyo } 425177595Sweongyo 426177595Sweongyopass: 427177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 428177595Sweongyo 429177595Sweongyo return 0; 430177595Sweongyo} 431177595Sweongyo 432177595Sweongyostatic int 433177595Sweongyomalo_hal_fwload_main(struct malo_hal *mh, char *firmware) 434177595Sweongyo{ 435177595Sweongyo const struct firmware *fw; 436177595Sweongyo const uint8_t *fp; 437177595Sweongyo int error; 438177595Sweongyo size_t count; 439177595Sweongyo uint16_t seqnum; 440177595Sweongyo uint32_t blocksize; 441177595Sweongyo 442177595Sweongyo error = 0; 443177595Sweongyo 444177595Sweongyo fw = firmware_get(firmware); 445177595Sweongyo if (fw == NULL) { 446177595Sweongyo device_printf(mh->mh_dev, "could not read firmware %s!\n", 447177595Sweongyo firmware); 448177595Sweongyo return (EIO); 449177595Sweongyo } 450177595Sweongyo 451177819Sweongyo device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 452177595Sweongyo firmware, fw->datasize); 453177595Sweongyo 454177595Sweongyo seqnum = 1; 455177595Sweongyo for (count = 0; count < fw->datasize; count += blocksize) { 456177595Sweongyo blocksize = MIN(256, fw->datasize - count); 457177595Sweongyo fp = (const uint8_t *)fw->data + count; 458177595Sweongyo 459177595Sweongyo error = malo_hal_send_main(mh, fp, blocksize, seqnum++, 460177595Sweongyo MALO_NOWAIT); 461177595Sweongyo if (error != 0) 462177595Sweongyo goto fail; 463177595Sweongyo DELAY(500); 464177595Sweongyo } 465177595Sweongyo 466177595Sweongyo /* 467177595Sweongyo * send a command with size 0 to tell that the firmware has been 468177595Sweongyo * uploaded 469177595Sweongyo */ 470177595Sweongyo error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT); 471177595Sweongyo DELAY(100); 472177595Sweongyo 473177595Sweongyofail: 474177595Sweongyo firmware_put(fw, FIRMWARE_UNLOAD); 475177595Sweongyo 476177595Sweongyo return (error); 477177595Sweongyo} 478177595Sweongyo 479177595Sweongyoint 480177595Sweongyomalo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware) 481177595Sweongyo{ 482177595Sweongyo int error, i; 483177595Sweongyo uint32_t fwreadysig, opmode; 484177595Sweongyo 485177595Sweongyo /* 486177595Sweongyo * NB: now malo(4) supports only STA mode. It will be better if it 487177595Sweongyo * supports AP mode. 488177595Sweongyo */ 489177595Sweongyo fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE; 490177595Sweongyo opmode = MALO_HOSTCMD_STA_MODE; 491177595Sweongyo 492177595Sweongyo malo_hal_fw_reset(mh); 493177595Sweongyo 494177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL, 495177595Sweongyo MALO_A2HRIC_BIT_MASK); 496177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00); 497177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00); 498177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 499177595Sweongyo MALO_A2HRIC_BIT_MASK); 500177595Sweongyo 501177595Sweongyo error = malo_hal_fwload_helper(mh, helper); 502177595Sweongyo if (error != 0) { 503177595Sweongyo device_printf(mh->mh_dev, "failed to load bootrom loader.\n"); 504177595Sweongyo goto fail; 505177595Sweongyo } 506177595Sweongyo 507177595Sweongyo DELAY(200 * MALO_FW_CHECK_USECS); 508177595Sweongyo 509177595Sweongyo error = malo_hal_fwload_main(mh, firmware); 510177595Sweongyo if (error != 0) { 511177595Sweongyo device_printf(mh->mh_dev, "failed to load firmware.\n"); 512177595Sweongyo goto fail; 513177595Sweongyo } 514177595Sweongyo 515177595Sweongyo /* 516177595Sweongyo * Wait for firmware to startup; we monitor the INT_CODE register 517177595Sweongyo * waiting for a signature to written back indicating it's ready to go. 518177595Sweongyo */ 519177595Sweongyo mh->mh_cmdbuf[1] = 0; 520177595Sweongyo 521177595Sweongyo if (opmode != MALO_HOSTCMD_STA_MODE) 522177595Sweongyo malo_hal_trigger_pcicmd(mh); 523177595Sweongyo 524177595Sweongyo for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 525177595Sweongyo malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode); 526177595Sweongyo DELAY(MALO_FW_CHECK_USECS); 527177595Sweongyo if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) { 528177595Sweongyo malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 529177595Sweongyo return malo_hal_resetstate(mh); 530177595Sweongyo } 531177595Sweongyo } 532177595Sweongyo 533177595Sweongyo return ETIMEDOUT; 534177595Sweongyofail: 535177595Sweongyo malo_hal_fw_reset(mh); 536177595Sweongyo 537177595Sweongyo return (error); 538177595Sweongyo} 539177595Sweongyo 540177595Sweongyo/* 541177595Sweongyo * Return "hw specs". Note this must be the first cmd MUST be done after 542177595Sweongyo * a firmware download or the f/w will lockup. 543177595Sweongyo */ 544177595Sweongyoint 545177595Sweongyomalo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw) 546177595Sweongyo{ 547177595Sweongyo struct malo_cmd_get_hwspec *cmd; 548177595Sweongyo int ret; 549177595Sweongyo 550177595Sweongyo MALO_HAL_LOCK(mh); 551177595Sweongyo 552177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC); 553177595Sweongyo memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN); 554177595Sweongyo cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048); 555177595Sweongyo 556177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC); 557177595Sweongyo if (ret == 0) { 558177595Sweongyo IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr); 559177595Sweongyo hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff; 560177595Sweongyo hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff; 561177595Sweongyo hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff; 562177595Sweongyo hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff; 563177595Sweongyo hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff; 564177595Sweongyo hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff; 565177595Sweongyo hw->regioncode = le16toh(cmd->regioncode) & 0x00ff; 566177595Sweongyo hw->fw_releasenum = le32toh(cmd->fw_releasenum); 567177595Sweongyo hw->maxnum_wcb = le16toh(cmd->num_wcb); 568177595Sweongyo hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr); 569177595Sweongyo hw->num_antenna = le16toh(cmd->num_antenna); 570177595Sweongyo hw->hwversion = cmd->version; 571177595Sweongyo hw->hostinterface = cmd->hostif; 572177595Sweongyo } 573177595Sweongyo 574177595Sweongyo MALO_HAL_UNLOCK(mh); 575177595Sweongyo 576177595Sweongyo return ret; 577177595Sweongyo} 578177595Sweongyo 579177595Sweongyovoid 580177595Sweongyomalo_hal_detach(struct malo_hal *mh) 581177595Sweongyo{ 582177595Sweongyo 583177595Sweongyo bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap); 584177595Sweongyo bus_dma_tag_destroy(mh->mh_dmat); 585177595Sweongyo mtx_destroy(&mh->mh_mtx); 586177595Sweongyo free(mh, M_DEVBUF); 587177595Sweongyo} 588177595Sweongyo 589177595Sweongyo/* 590177595Sweongyo * Configure antenna use. Takes effect immediately. 591177595Sweongyo * 592177595Sweongyo * XXX tx antenna setting ignored 593177595Sweongyo * XXX rx antenna setting should always be 3 (for now) 594177595Sweongyo */ 595177595Sweongyoint 596177595Sweongyomalo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant) 597177595Sweongyo{ 598177595Sweongyo struct malo_cmd_rf_antenna *cmd; 599177595Sweongyo int ret; 600177595Sweongyo 601177595Sweongyo if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX)) 602177595Sweongyo return EINVAL; 603177595Sweongyo 604177595Sweongyo MALO_HAL_LOCK(mh); 605177595Sweongyo 606177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_rf_antenna, 607177595Sweongyo MALO_HOSTCMD_802_11_RF_ANTENNA); 608177595Sweongyo cmd->action = htole16(dirset); 609177595Sweongyo if (ant == 0) { /* default to all/both antennae */ 610177595Sweongyo /* XXX never reach now. */ 611177595Sweongyo ant = 3; 612177595Sweongyo } 613177595Sweongyo cmd->mode = htole16(ant); 614177595Sweongyo 615177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA); 616177595Sweongyo 617177595Sweongyo MALO_HAL_UNLOCK(mh); 618177595Sweongyo 619177595Sweongyo return ret; 620177595Sweongyo} 621177595Sweongyo 622177595Sweongyo/* 623177595Sweongyo * Configure radio. Takes effect immediately. 624177595Sweongyo * 625177595Sweongyo * XXX preamble installed after set fixed rate cmd 626177595Sweongyo */ 627177595Sweongyoint 628177595Sweongyomalo_hal_setradio(struct malo_hal *mh, int onoff, 629177595Sweongyo enum malo_hal_preamble preamble) 630177595Sweongyo{ 631177595Sweongyo struct malo_cmd_radio_control *cmd; 632177595Sweongyo int ret; 633177595Sweongyo 634177595Sweongyo MALO_HAL_LOCK(mh); 635177595Sweongyo 636177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_radio_control, 637177595Sweongyo MALO_HOSTCMD_802_11_RADIO_CONTROL); 638177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 639177595Sweongyo if (onoff == 0) 640177595Sweongyo cmd->control = 0; 641177595Sweongyo else 642177595Sweongyo cmd->control = htole16(preamble); 643177595Sweongyo cmd->radio_on = htole16(onoff); 644177595Sweongyo 645177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL); 646177595Sweongyo 647177595Sweongyo MALO_HAL_UNLOCK(mh); 648177595Sweongyo 649177595Sweongyo return ret; 650177595Sweongyo} 651177595Sweongyo 652177595Sweongyo/* 653177595Sweongyo * Set the interrupt mask. 654177595Sweongyo */ 655177595Sweongyovoid 656177595Sweongyomalo_hal_intrset(struct malo_hal *mh, uint32_t mask) 657177595Sweongyo{ 658177595Sweongyo 659177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0); 660177595Sweongyo (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 661177595Sweongyo 662177595Sweongyo mh->mh_imask = mask; 663177595Sweongyo malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask); 664177595Sweongyo (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 665177595Sweongyo} 666177595Sweongyo 667177595Sweongyoint 668177595Sweongyomalo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan) 669177595Sweongyo{ 670177595Sweongyo struct malo_cmd_fw_set_rf_channel *cmd; 671177595Sweongyo int ret; 672177595Sweongyo 673177595Sweongyo MALO_HAL_LOCK(mh); 674177595Sweongyo 675177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel, 676177595Sweongyo MALO_HOSTCMD_SET_RF_CHANNEL); 677177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 678177595Sweongyo cmd->cur_channel = chan->channel; 679177595Sweongyo 680177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL); 681177595Sweongyo 682177595Sweongyo MALO_HAL_UNLOCK(mh); 683177595Sweongyo 684177595Sweongyo return ret; 685177595Sweongyo} 686177595Sweongyo 687177595Sweongyoint 688177595Sweongyomalo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c) 689177595Sweongyo{ 690177595Sweongyo struct malo_cmd_rf_tx_power *cmd; 691177595Sweongyo const struct malo_hal_caldata *cal = &mh->mh_caldata; 692177595Sweongyo uint8_t chan = c->channel; 693177595Sweongyo uint16_t pow; 694177595Sweongyo int i, idx, ret; 695177595Sweongyo 696177595Sweongyo MALO_HAL_LOCK(mh); 697177595Sweongyo 698177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power, 699177595Sweongyo MALO_HOSTCMD_802_11_RF_TX_POWER); 700177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST); 701177595Sweongyo for (i = 0; i < 4; i++) { 702177595Sweongyo idx = (chan - 1) * 4 + i; 703177595Sweongyo pow = cal->pt_ratetable_20m[idx]; 704177595Sweongyo cmd->power_levellist[i] = htole16(pow); 705177595Sweongyo } 706177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER); 707177595Sweongyo 708177595Sweongyo MALO_HAL_UNLOCK(mh); 709177595Sweongyo 710177595Sweongyo return ret; 711177595Sweongyo} 712177595Sweongyo 713177595Sweongyoint 714177595Sweongyomalo_hal_setpromisc(struct malo_hal *mh, int enable) 715177595Sweongyo{ 716177595Sweongyo /* XXX need host cmd */ 717177595Sweongyo return 0; 718177595Sweongyo} 719177595Sweongyo 720177595Sweongyoint 721177595Sweongyomalo_hal_setassocid(struct malo_hal *mh, 722177595Sweongyo const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd) 723177595Sweongyo{ 724177595Sweongyo struct malo_cmd_fw_set_aid *cmd; 725177595Sweongyo int ret; 726177595Sweongyo 727177595Sweongyo MALO_HAL_LOCK(mh); 728177595Sweongyo 729177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid, 730177595Sweongyo MALO_HOSTCMD_SET_AID); 731177595Sweongyo cmd->cmdhdr.seqnum = 1; 732177595Sweongyo cmd->associd = htole16(associd); 733177595Sweongyo IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid); 734177595Sweongyo 735177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID); 736177595Sweongyo MALO_HAL_UNLOCK(mh); 737177595Sweongyo return ret; 738177595Sweongyo} 739177595Sweongyo 740177595Sweongyo/* 741177595Sweongyo * Kick the firmware to tell it there are new tx descriptors 742177595Sweongyo * for processing. The driver says what h/w q has work in 743177595Sweongyo * case the f/w ever gets smarter. 744177595Sweongyo */ 745177595Sweongyovoid 746177595Sweongyomalo_hal_txstart(struct malo_hal *mh, int qnum) 747177595Sweongyo{ 748177595Sweongyo bus_space_write_4(mh->mh_iot, mh->mh_ioh, 749177595Sweongyo MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY); 750177595Sweongyo (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE); 751177595Sweongyo} 752177595Sweongyo 753177595Sweongyo/* 754177595Sweongyo * Return the current ISR setting and clear the cause. 755177595Sweongyo */ 756177595Sweongyovoid 757177595Sweongyomalo_hal_getisr(struct malo_hal *mh, uint32_t *status) 758177595Sweongyo{ 759177595Sweongyo uint32_t cause; 760177595Sweongyo 761177595Sweongyo cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 762177595Sweongyo MALO_REG_A2H_INTERRUPT_CAUSE); 763177595Sweongyo if (cause == 0xffffffff) { /* card removed */ 764177595Sweongyo cause = 0; 765177595Sweongyo } else if (cause != 0) { 766177595Sweongyo /* clear cause bits */ 767177595Sweongyo bus_space_write_4(mh->mh_iot, mh->mh_ioh, 768177595Sweongyo MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 769177595Sweongyo (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 770177595Sweongyo MALO_REG_INT_CODE); 771177595Sweongyo cause &= mh->mh_imask; 772177595Sweongyo } 773177595Sweongyo 774177595Sweongyo *status = cause; 775177595Sweongyo} 776177595Sweongyo 777177595Sweongyo/* 778177595Sweongyo * Callback from the driver on a cmd done interrupt. Nothing to do right 779177595Sweongyo * now as we spin waiting for cmd completion. 780177595Sweongyo */ 781177595Sweongyovoid 782177595Sweongyomalo_hal_cmddone(struct malo_hal *mh) 783177595Sweongyo{ 784177595Sweongyo /* NB : do nothing. */ 785177595Sweongyo} 786177595Sweongyo 787177595Sweongyoint 788177595Sweongyomalo_hal_prescan(struct malo_hal *mh) 789177595Sweongyo{ 790177595Sweongyo struct malo_cmd_prescan *cmd; 791177595Sweongyo int ret; 792177595Sweongyo 793177595Sweongyo MALO_HAL_LOCK(mh); 794177595Sweongyo 795177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN); 796177595Sweongyo cmd->cmdhdr.seqnum = 1; 797177595Sweongyo 798177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN); 799177595Sweongyo 800177595Sweongyo MALO_HAL_UNLOCK(mh); 801177595Sweongyo 802177595Sweongyo return ret; 803177595Sweongyo} 804177595Sweongyo 805177595Sweongyoint 806177595Sweongyomalo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson) 807177595Sweongyo{ 808177595Sweongyo struct malo_cmd_postscan *cmd; 809177595Sweongyo int ret; 810177595Sweongyo 811177595Sweongyo MALO_HAL_LOCK(mh); 812177595Sweongyo 813177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN); 814177595Sweongyo cmd->cmdhdr.seqnum = 1; 815177595Sweongyo cmd->isibss = htole32(ibsson); 816177595Sweongyo IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr); 817177595Sweongyo 818177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN); 819177595Sweongyo 820177595Sweongyo MALO_HAL_UNLOCK(mh); 821177595Sweongyo 822177595Sweongyo return ret; 823177595Sweongyo} 824177595Sweongyo 825177595Sweongyoint 826177595Sweongyomalo_hal_set_slot(struct malo_hal *mh, int is_short) 827177595Sweongyo{ 828177595Sweongyo int ret; 829177595Sweongyo struct malo_cmd_fw_setslot *cmd; 830177595Sweongyo 831177595Sweongyo MALO_HAL_LOCK(mh); 832177595Sweongyo 833177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT); 834177595Sweongyo cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 835177595Sweongyo cmd->slot = (is_short == 1 ? 1 : 0); 836177595Sweongyo 837177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT); 838177595Sweongyo 839177595Sweongyo MALO_HAL_UNLOCK(mh); 840177595Sweongyo 841177595Sweongyo return ret; 842177595Sweongyo} 843177595Sweongyo 844177595Sweongyoint 845177595Sweongyomalo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate) 846177595Sweongyo{ 847177595Sweongyo int i, ret; 848177595Sweongyo struct malo_cmd_set_rate *cmd; 849177595Sweongyo 850177595Sweongyo MALO_HAL_LOCK(mh); 851177595Sweongyo 852177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE); 853177595Sweongyo cmd->aprates[0] = 2; 854177595Sweongyo cmd->aprates[1] = 4; 855177595Sweongyo cmd->aprates[2] = 11; 856177595Sweongyo cmd->aprates[3] = 22; 857177595Sweongyo if (curmode == IEEE80211_MODE_11G) { 858177595Sweongyo cmd->aprates[4] = 0; /* XXX reserved? */ 859177595Sweongyo cmd->aprates[5] = 12; 860177595Sweongyo cmd->aprates[6] = 18; 861177595Sweongyo cmd->aprates[7] = 24; 862177595Sweongyo cmd->aprates[8] = 36; 863177595Sweongyo cmd->aprates[9] = 48; 864177595Sweongyo cmd->aprates[10] = 72; 865177595Sweongyo cmd->aprates[11] = 96; 866177595Sweongyo cmd->aprates[12] = 108; 867177595Sweongyo } 868177595Sweongyo 869177595Sweongyo if (rate != 0) { 870177595Sweongyo /* fixed rate */ 871177595Sweongyo for (i = 0; i < 13; i++) { 872177595Sweongyo if (cmd->aprates[i] == rate) { 873177595Sweongyo cmd->rateindex = i; 874177595Sweongyo cmd->dataratetype = 1; 875177595Sweongyo break; 876177595Sweongyo } 877177595Sweongyo } 878177595Sweongyo } 879177595Sweongyo 880177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE); 881177595Sweongyo 882177595Sweongyo MALO_HAL_UNLOCK(mh); 883177595Sweongyo 884177595Sweongyo return ret; 885177595Sweongyo} 886177595Sweongyo 887177595Sweongyoint 888177595Sweongyomalo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[]) 889177595Sweongyo{ 890177595Sweongyo struct malo_cmd_mcast *cmd; 891177595Sweongyo int ret; 892177595Sweongyo 893177595Sweongyo if (nmc > MALO_HAL_MCAST_MAX) 894177595Sweongyo return EINVAL; 895177595Sweongyo 896177595Sweongyo MALO_HAL_LOCK(mh); 897177595Sweongyo 898177595Sweongyo _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR); 899177595Sweongyo memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN); 900177595Sweongyo cmd->numaddr = htole16(nmc); 901177595Sweongyo cmd->action = htole16(0xffff); 902177595Sweongyo 903177595Sweongyo ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR); 904177595Sweongyo 905177595Sweongyo MALO_HAL_UNLOCK(mh); 906177595Sweongyo 907177595Sweongyo return ret; 908177595Sweongyo} 909