if_lge.c revision 95673
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/lge/if_lge.c 95673 2002-04-28 20:34:20Z phk $ 34 */ 35 36/* 37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 38 * documentation not available, but ask me nicely. 39 * 40 * Written by Bill Paul <william.paul@windriver.com> 41 * Wind River Systems 42 */ 43 44/* 45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 46 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 48 * are three supported methods for data transfer between host and 49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 50 * Propulsion Technology (tm) DMA. The latter mechanism is a form 51 * of double buffer DMA where the packet data is copied to a 52 * pre-allocated DMA buffer who's physical address has been loaded 53 * into a table at device initialization time. The rationale is that 54 * the virtual to physical address translation needed for normal 55 * scatter/gather DMA is more expensive than the data copy needed 56 * for double buffering. This may be true in Windows NT and the like, 57 * but it isn't true for us, at least on the x86 arch. This driver 58 * uses the scatter/gather I/O method for both TX and RX. 59 * 60 * The LXT1001 only supports TCP/IP checksum offload on receive. 61 * Also, the VLAN tagging is done using a 16-entry table which allows 62 * the chip to perform hardware filtering based on VLAN tags. Sadly, 63 * our vlan support doesn't currently play well with this kind of 64 * hardware support. 65 * 66 * Special thanks to: 67 * - Jeff James at Intel, for arranging to have the LXT1001 manual 68 * released (at long last) 69 * - Beny Chen at D-Link, for actually sending it to me 70 * - Brad Short and Keith Alexis at SMC, for sending me sample 71 * SMC9462SX and SMC9462TX adapters for testing 72 * - Paul Saab at Y!, for not killing me (though it remains to be seen 73 * if in fact he did me much of a favor) 74 */ 75 76#include <sys/param.h> 77#include <sys/systm.h> 78#include <sys/sockio.h> 79#include <sys/mbuf.h> 80#include <sys/malloc.h> 81#include <sys/kernel.h> 82#include <sys/socket.h> 83 84#include <net/if.h> 85#include <net/if_arp.h> 86#include <net/ethernet.h> 87#include <net/if_dl.h> 88#include <net/if_media.h> 89 90#include <net/bpf.h> 91 92#include <vm/vm.h> /* for vtophys */ 93#include <vm/pmap.h> /* for vtophys */ 94#include <machine/clock.h> /* for DELAY */ 95#include <machine/bus_pio.h> 96#include <machine/bus_memio.h> 97#include <machine/bus.h> 98#include <machine/resource.h> 99#include <sys/bus.h> 100#include <sys/rman.h> 101 102#include <dev/mii/mii.h> 103#include <dev/mii/miivar.h> 104 105#include <pci/pcireg.h> 106#include <pci/pcivar.h> 107 108#define LGE_USEIOSPACE 109 110#include <dev/lge/if_lgereg.h> 111 112/* "controller miibus0" required. See GENERIC if you get errors here. */ 113#include "miibus_if.h" 114 115#ifndef lint 116static const char rcsid[] = 117 "$FreeBSD: head/sys/dev/lge/if_lge.c 95673 2002-04-28 20:34:20Z phk $"; 118#endif 119 120/* 121 * Various supported device vendors/types and their names. 122 */ 123static struct lge_type lge_devs[] = { 124 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 125 { 0, 0, NULL } 126}; 127 128static int lge_probe (device_t); 129static int lge_attach (device_t); 130static int lge_detach (device_t); 131 132static int lge_alloc_jumbo_mem (struct lge_softc *); 133static void lge_free_jumbo_mem (struct lge_softc *); 134static void *lge_jalloc (struct lge_softc *); 135static void lge_jfree (caddr_t, void *); 136 137static int lge_newbuf (struct lge_softc *, 138 struct lge_rx_desc *, 139 struct mbuf *); 140static int lge_encap (struct lge_softc *, 141 struct mbuf *, u_int32_t *); 142static void lge_rxeof (struct lge_softc *, int); 143static void lge_rxeoc (struct lge_softc *); 144static void lge_txeof (struct lge_softc *); 145static void lge_intr (void *); 146static void lge_tick (void *); 147static void lge_start (struct ifnet *); 148static int lge_ioctl (struct ifnet *, u_long, caddr_t); 149static void lge_init (void *); 150static void lge_stop (struct lge_softc *); 151static void lge_watchdog (struct ifnet *); 152static void lge_shutdown (device_t); 153static int lge_ifmedia_upd (struct ifnet *); 154static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 155 156static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *); 157static void lge_read_eeprom (struct lge_softc *, caddr_t, int, int, int); 158 159static int lge_miibus_readreg (device_t, int, int); 160static int lge_miibus_writereg (device_t, int, int, int); 161static void lge_miibus_statchg (device_t); 162 163static void lge_setmulti (struct lge_softc *); 164static u_int32_t lge_crc (struct lge_softc *, caddr_t); 165static void lge_reset (struct lge_softc *); 166static int lge_list_rx_init (struct lge_softc *); 167static int lge_list_tx_init (struct lge_softc *); 168 169#ifdef LGE_USEIOSPACE 170#define LGE_RES SYS_RES_IOPORT 171#define LGE_RID LGE_PCI_LOIO 172#else 173#define LGE_RES SYS_RES_MEMORY 174#define LGE_RID LGE_PCI_LOMEM 175#endif 176 177static device_method_t lge_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, lge_probe), 180 DEVMETHOD(device_attach, lge_attach), 181 DEVMETHOD(device_detach, lge_detach), 182 DEVMETHOD(device_shutdown, lge_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 190 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 191 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 192 193 { 0, 0 } 194}; 195 196static driver_t lge_driver = { 197 "lge", 198 lge_methods, 199 sizeof(struct lge_softc) 200}; 201 202static devclass_t lge_devclass; 203 204DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 205DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 206 207#define LGE_SETBIT(sc, reg, x) \ 208 CSR_WRITE_4(sc, reg, \ 209 CSR_READ_4(sc, reg) | (x)) 210 211#define LGE_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_4(sc, reg, \ 213 CSR_READ_4(sc, reg) & ~(x)) 214 215#define SIO_SET(x) \ 216 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 217 218#define SIO_CLR(x) \ 219 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 220 221/* 222 * Read a word of data stored in the EEPROM at address 'addr.' 223 */ 224static void lge_eeprom_getword(sc, addr, dest) 225 struct lge_softc *sc; 226 int addr; 227 u_int16_t *dest; 228{ 229 register int i; 230 u_int32_t val; 231 232 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 233 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 234 235 for (i = 0; i < LGE_TIMEOUT; i++) 236 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 237 break; 238 239 if (i == LGE_TIMEOUT) { 240 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 241 return; 242 } 243 244 val = CSR_READ_4(sc, LGE_EEDATA); 245 246 if (addr & 1) 247 *dest = (val >> 16) & 0xFFFF; 248 else 249 *dest = val & 0xFFFF; 250 251 return; 252} 253 254/* 255 * Read a sequence of words from the EEPROM. 256 */ 257static void lge_read_eeprom(sc, dest, off, cnt, swap) 258 struct lge_softc *sc; 259 caddr_t dest; 260 int off; 261 int cnt; 262 int swap; 263{ 264 int i; 265 u_int16_t word = 0, *ptr; 266 267 for (i = 0; i < cnt; i++) { 268 lge_eeprom_getword(sc, off + i, &word); 269 ptr = (u_int16_t *)(dest + (i * 2)); 270 if (swap) 271 *ptr = ntohs(word); 272 else 273 *ptr = word; 274 } 275 276 return; 277} 278 279static int lge_miibus_readreg(dev, phy, reg) 280 device_t dev; 281 int phy, reg; 282{ 283 struct lge_softc *sc; 284 int i; 285 286 sc = device_get_softc(dev); 287 288 /* 289 * If we have a non-PCS PHY, pretend that the internal 290 * autoneg stuff at PHY address 0 isn't there so that 291 * the miibus code will find only the GMII PHY. 292 */ 293 if (sc->lge_pcs == 0 && phy == 0) 294 return(0); 295 296 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 297 298 for (i = 0; i < LGE_TIMEOUT; i++) 299 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 300 break; 301 302 if (i == LGE_TIMEOUT) { 303 printf("lge%d: PHY read timed out\n", sc->lge_unit); 304 return(0); 305 } 306 307 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 308} 309 310static int lge_miibus_writereg(dev, phy, reg, data) 311 device_t dev; 312 int phy, reg, data; 313{ 314 struct lge_softc *sc; 315 int i; 316 317 sc = device_get_softc(dev); 318 319 CSR_WRITE_4(sc, LGE_GMIICTL, 320 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 321 322 for (i = 0; i < LGE_TIMEOUT; i++) 323 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 324 break; 325 326 if (i == LGE_TIMEOUT) { 327 printf("lge%d: PHY write timed out\n", sc->lge_unit); 328 return(0); 329 } 330 331 return(0); 332} 333 334static void lge_miibus_statchg(dev) 335 device_t dev; 336{ 337 struct lge_softc *sc; 338 struct mii_data *mii; 339 340 sc = device_get_softc(dev); 341 mii = device_get_softc(sc->lge_miibus); 342 343 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 344 switch (IFM_SUBTYPE(mii->mii_media_active)) { 345 case IFM_1000_T: 346 case IFM_1000_SX: 347 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 348 break; 349 case IFM_100_TX: 350 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 351 break; 352 case IFM_10_T: 353 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 354 break; 355 default: 356 /* 357 * Choose something, even if it's wrong. Clearing 358 * all the bits will hose autoneg on the internal 359 * PHY. 360 */ 361 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 362 break; 363 } 364 365 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 366 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 367 } else { 368 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 369 } 370 371 return; 372} 373 374static u_int32_t lge_crc(sc, addr) 375 struct lge_softc *sc; 376 caddr_t addr; 377{ 378 u_int32_t crc, carry; 379 int i, j; 380 u_int8_t c; 381 382 /* Compute CRC for the address value. */ 383 crc = 0xFFFFFFFF; /* initial value */ 384 385 for (i = 0; i < 6; i++) { 386 c = *(addr + i); 387 for (j = 0; j < 8; j++) { 388 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 389 crc <<= 1; 390 c >>= 1; 391 if (carry) 392 crc = (crc ^ 0x04c11db6) | carry; 393 } 394 } 395 396 /* 397 * return the filter bit position 398 */ 399 return((crc >> 26) & 0x0000003F); 400} 401 402static void lge_setmulti(sc) 403 struct lge_softc *sc; 404{ 405 struct ifnet *ifp; 406 struct ifmultiaddr *ifma; 407 u_int32_t h = 0, hashes[2] = { 0, 0 }; 408 409 ifp = &sc->arpcom.ac_if; 410 411 /* Make sure multicast hash table is enabled. */ 412 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 413 414 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 415 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 416 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 417 return; 418 } 419 420 /* first, zot all the existing hash bits */ 421 CSR_WRITE_4(sc, LGE_MAR0, 0); 422 CSR_WRITE_4(sc, LGE_MAR1, 0); 423 424 /* now program new ones */ 425 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 426 if (ifma->ifma_addr->sa_family != AF_LINK) 427 continue; 428 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 429 if (h < 32) 430 hashes[0] |= (1 << h); 431 else 432 hashes[1] |= (1 << (h - 32)); 433 } 434 435 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 436 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 437 438 return; 439} 440 441static void lge_reset(sc) 442 struct lge_softc *sc; 443{ 444 register int i; 445 446 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 447 448 for (i = 0; i < LGE_TIMEOUT; i++) { 449 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 450 break; 451 } 452 453 if (i == LGE_TIMEOUT) 454 printf("lge%d: reset never completed\n", sc->lge_unit); 455 456 /* Wait a little while for the chip to get its brains in order. */ 457 DELAY(1000); 458 459 return; 460} 461 462/* 463 * Probe for a Level 1 chip. Check the PCI vendor and device 464 * IDs against our list and return a device name if we find a match. 465 */ 466static int lge_probe(dev) 467 device_t dev; 468{ 469 struct lge_type *t; 470 471 t = lge_devs; 472 473 while(t->lge_name != NULL) { 474 if ((pci_get_vendor(dev) == t->lge_vid) && 475 (pci_get_device(dev) == t->lge_did)) { 476 device_set_desc(dev, t->lge_name); 477 return(0); 478 } 479 t++; 480 } 481 482 return(ENXIO); 483} 484 485/* 486 * Attach the interface. Allocate softc structures, do ifmedia 487 * setup and ethernet/BPF attach. 488 */ 489static int lge_attach(dev) 490 device_t dev; 491{ 492 int s; 493 u_char eaddr[ETHER_ADDR_LEN]; 494 u_int32_t command; 495 struct lge_softc *sc; 496 struct ifnet *ifp; 497 int unit, error = 0, rid; 498 499 s = splimp(); 500 501 sc = device_get_softc(dev); 502 unit = device_get_unit(dev); 503 bzero(sc, sizeof(struct lge_softc)); 504 505 /* 506 * Handle power management nonsense. 507 */ 508 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 509 u_int32_t iobase, membase, irq; 510 511 /* Save important PCI config data. */ 512 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 513 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 514 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 515 516 /* Reset the power state. */ 517 printf("lge%d: chip is in D%d power mode " 518 "-- setting to D0\n", unit, 519 pci_get_powerstate(dev)); 520 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 521 522 /* Restore PCI config data. */ 523 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 524 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 525 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 526 } 527 528 /* 529 * Map control/status registers. 530 */ 531 pci_enable_busmaster(dev); 532 pci_enable_io(dev, SYS_RES_IOPORT); 533 pci_enable_io(dev, SYS_RES_MEMORY); 534 command = pci_read_config(dev, PCIR_COMMAND, 4); 535 536#ifdef LGE_USEIOSPACE 537 if (!(command & PCIM_CMD_PORTEN)) { 538 printf("lge%d: failed to enable I/O ports!\n", unit); 539 error = ENXIO;; 540 goto fail; 541 } 542#else 543 if (!(command & PCIM_CMD_MEMEN)) { 544 printf("lge%d: failed to enable memory mapping!\n", unit); 545 error = ENXIO;; 546 goto fail; 547 } 548#endif 549 550 rid = LGE_RID; 551 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 552 0, ~0, 1, RF_ACTIVE); 553 554 if (sc->lge_res == NULL) { 555 printf("lge%d: couldn't map ports/memory\n", unit); 556 error = ENXIO; 557 goto fail; 558 } 559 560 sc->lge_btag = rman_get_bustag(sc->lge_res); 561 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 562 563 /* Allocate interrupt */ 564 rid = 0; 565 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 566 RF_SHAREABLE | RF_ACTIVE); 567 568 if (sc->lge_irq == NULL) { 569 printf("lge%d: couldn't map interrupt\n", unit); 570 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 571 error = ENXIO; 572 goto fail; 573 } 574 575 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 576 lge_intr, sc, &sc->lge_intrhand); 577 578 if (error) { 579 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 580 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 581 printf("lge%d: couldn't set up irq\n", unit); 582 goto fail; 583 } 584 585 /* Reset the adapter. */ 586 lge_reset(sc); 587 588 /* 589 * Get station address from the EEPROM. 590 */ 591 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 592 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 593 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 594 595 /* 596 * A Level 1 chip was detected. Inform the world. 597 */ 598 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 599 600 sc->lge_unit = unit; 601 callout_handle_init(&sc->lge_stat_ch); 602 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 603 604 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 606 607 if (sc->lge_ldata == NULL) { 608 printf("lge%d: no memory for list buffers!\n", unit); 609 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 610 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 611 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 612 error = ENXIO; 613 goto fail; 614 } 615 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 616 617 /* Try to allocate memory for jumbo buffers. */ 618 if (lge_alloc_jumbo_mem(sc)) { 619 printf("lge%d: jumbo buffer allocation failed\n", 620 sc->lge_unit); 621 contigfree(sc->lge_ldata, 622 sizeof(struct lge_list_data), M_DEVBUF); 623 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 624 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 625 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 626 error = ENXIO; 627 goto fail; 628 } 629 630 ifp = &sc->arpcom.ac_if; 631 ifp->if_softc = sc; 632 ifp->if_unit = unit; 633 ifp->if_name = "lge"; 634 ifp->if_mtu = ETHERMTU; 635 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 636 ifp->if_ioctl = lge_ioctl; 637 ifp->if_output = ether_output; 638 ifp->if_start = lge_start; 639 ifp->if_watchdog = lge_watchdog; 640 ifp->if_init = lge_init; 641 ifp->if_baudrate = 1000000000; 642 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 643 ifp->if_capabilities = IFCAP_RXCSUM; 644 ifp->if_capenable = ifp->if_capabilities; 645 646 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 647 sc->lge_pcs = 1; 648 else 649 sc->lge_pcs = 0; 650 651 /* 652 * Do MII setup. 653 */ 654 if (mii_phy_probe(dev, &sc->lge_miibus, 655 lge_ifmedia_upd, lge_ifmedia_sts)) { 656 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 657 contigfree(sc->lge_ldata, 658 sizeof(struct lge_list_data), M_DEVBUF); 659 lge_free_jumbo_mem(sc); 660 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 662 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 663 error = ENXIO; 664 goto fail; 665 } 666 667 /* 668 * Call MI attach routine. 669 */ 670 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 671 callout_handle_init(&sc->lge_stat_ch); 672 673fail: 674 splx(s); 675 return(error); 676} 677 678static int lge_detach(dev) 679 device_t dev; 680{ 681 struct lge_softc *sc; 682 struct ifnet *ifp; 683 int s; 684 685 s = splimp(); 686 687 sc = device_get_softc(dev); 688 ifp = &sc->arpcom.ac_if; 689 690 lge_reset(sc); 691 lge_stop(sc); 692 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 693 694 bus_generic_detach(dev); 695 device_delete_child(dev, sc->lge_miibus); 696 697 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 698 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 699 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 700 701 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 702 lge_free_jumbo_mem(sc); 703 704 splx(s); 705 706 return(0); 707} 708 709/* 710 * Initialize the transmit descriptors. 711 */ 712static int lge_list_tx_init(sc) 713 struct lge_softc *sc; 714{ 715 struct lge_list_data *ld; 716 struct lge_ring_data *cd; 717 int i; 718 719 cd = &sc->lge_cdata; 720 ld = sc->lge_ldata; 721 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 722 ld->lge_tx_list[i].lge_mbuf = NULL; 723 ld->lge_tx_list[i].lge_ctl = 0; 724 } 725 726 cd->lge_tx_prod = cd->lge_tx_cons = 0; 727 728 return(0); 729} 730 731 732/* 733 * Initialize the RX descriptors and allocate mbufs for them. Note that 734 * we arralge the descriptors in a closed ring, so that the last descriptor 735 * points back to the first. 736 */ 737static int lge_list_rx_init(sc) 738 struct lge_softc *sc; 739{ 740 struct lge_list_data *ld; 741 struct lge_ring_data *cd; 742 int i; 743 744 ld = sc->lge_ldata; 745 cd = &sc->lge_cdata; 746 747 cd->lge_rx_prod = cd->lge_rx_cons = 0; 748 749 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 750 751 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 752 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 753 break; 754 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 755 return(ENOBUFS); 756 } 757 758 /* Clear possible 'rx command queue empty' interrupt. */ 759 CSR_READ_4(sc, LGE_ISR); 760 761 return(0); 762} 763 764/* 765 * Initialize an RX descriptor and attach an MBUF cluster. 766 */ 767static int lge_newbuf(sc, c, m) 768 struct lge_softc *sc; 769 struct lge_rx_desc *c; 770 struct mbuf *m; 771{ 772 struct mbuf *m_new = NULL; 773 caddr_t *buf = NULL; 774 775 if (m == NULL) { 776 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 777 if (m_new == NULL) { 778 printf("lge%d: no memory for rx list " 779 "-- packet dropped!\n", sc->lge_unit); 780 return(ENOBUFS); 781 } 782 783 /* Allocate the jumbo buffer */ 784 buf = lge_jalloc(sc); 785 if (buf == NULL) { 786#ifdef LGE_VERBOSE 787 printf("lge%d: jumbo allocation failed " 788 "-- packet dropped!\n", sc->lge_unit); 789#endif 790 m_freem(m_new); 791 return(ENOBUFS); 792 } 793 /* Attach the buffer to the mbuf */ 794 m_new->m_data = (void *)buf; 795 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 796 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 797 (struct lge_softc *)sc, 0, EXT_NET_DRV); 798 } else { 799 m_new = m; 800 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 801 m_new->m_data = m_new->m_ext.ext_buf; 802 } 803 804 /* 805 * Adjust alignment so packet payload begins on a 806 * longword boundary. Mandatory for Alpha, useful on 807 * x86 too. 808 */ 809 m_adj(m_new, ETHER_ALIGN); 810 811 c->lge_mbuf = m_new; 812 c->lge_fragptr_hi = 0; 813 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 814 c->lge_fraglen = m_new->m_len; 815 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 816 c->lge_sts = 0; 817 818 /* 819 * Put this buffer in the RX command FIFO. To do this, 820 * we just write the physical address of the descriptor 821 * into the RX descriptor address registers. Note that 822 * there are two registers, one high DWORD and one low 823 * DWORD, which lets us specify a 64-bit address if 824 * desired. We only use a 32-bit address for now. 825 * Writing to the low DWORD register is what actually 826 * causes the command to be issued, so we do that 827 * last. 828 */ 829 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 830 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 831 832 return(0); 833} 834 835static int lge_alloc_jumbo_mem(sc) 836 struct lge_softc *sc; 837{ 838 caddr_t ptr; 839 register int i; 840 struct lge_jpool_entry *entry; 841 842 /* Grab a big chunk o' storage. */ 843 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 844 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 845 846 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 847 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 848 return(ENOBUFS); 849 } 850 851 SLIST_INIT(&sc->lge_jfree_listhead); 852 SLIST_INIT(&sc->lge_jinuse_listhead); 853 854 /* 855 * Now divide it up into 9K pieces and save the addresses 856 * in an array. 857 */ 858 ptr = sc->lge_cdata.lge_jumbo_buf; 859 for (i = 0; i < LGE_JSLOTS; i++) { 860 sc->lge_cdata.lge_jslots[i] = ptr; 861 ptr += LGE_JLEN; 862 entry = malloc(sizeof(struct lge_jpool_entry), 863 M_DEVBUF, M_NOWAIT); 864 if (entry == NULL) { 865 printf("lge%d: no memory for jumbo " 866 "buffer queue!\n", sc->lge_unit); 867 return(ENOBUFS); 868 } 869 entry->slot = i; 870 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 871 entry, jpool_entries); 872 } 873 874 return(0); 875} 876 877static void lge_free_jumbo_mem(sc) 878 struct lge_softc *sc; 879{ 880 int i; 881 struct lge_jpool_entry *entry; 882 883 for (i = 0; i < LGE_JSLOTS; i++) { 884 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 885 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 886 free(entry, M_DEVBUF); 887 } 888 889 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 890 891 return; 892} 893 894/* 895 * Allocate a jumbo buffer. 896 */ 897static void *lge_jalloc(sc) 898 struct lge_softc *sc; 899{ 900 struct lge_jpool_entry *entry; 901 902 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 903 904 if (entry == NULL) { 905#ifdef LGE_VERBOSE 906 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 907#endif 908 return(NULL); 909 } 910 911 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 912 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 913 return(sc->lge_cdata.lge_jslots[entry->slot]); 914} 915 916/* 917 * Release a jumbo buffer. 918 */ 919static void lge_jfree(buf, args) 920 caddr_t buf; 921 void *args; 922{ 923 struct lge_softc *sc; 924 int i; 925 struct lge_jpool_entry *entry; 926 927 /* Extract the softc struct pointer. */ 928 sc = args; 929 930 if (sc == NULL) 931 panic("lge_jfree: can't find softc pointer!"); 932 933 /* calculate the slot this buffer belongs to */ 934 i = ((vm_offset_t)buf 935 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 936 937 if ((i < 0) || (i >= LGE_JSLOTS)) 938 panic("lge_jfree: asked to free buffer that we don't manage!"); 939 940 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 941 if (entry == NULL) 942 panic("lge_jfree: buffer not in use!"); 943 entry->slot = i; 944 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 945 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 946 947 return; 948} 949 950/* 951 * A frame has been uploaded: pass the resulting mbuf chain up to 952 * the higher level protocols. 953 */ 954static void lge_rxeof(sc, cnt) 955 struct lge_softc *sc; 956 int cnt; 957{ 958 struct ether_header *eh; 959 struct mbuf *m; 960 struct ifnet *ifp; 961 struct lge_rx_desc *cur_rx; 962 int c, i, total_len = 0; 963 u_int32_t rxsts, rxctl; 964 965 ifp = &sc->arpcom.ac_if; 966 967 /* Find out how many frames were processed. */ 968 c = cnt; 969 i = sc->lge_cdata.lge_rx_cons; 970 971 /* Suck them in. */ 972 while(c) { 973 struct mbuf *m0 = NULL; 974 975 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 976 rxctl = cur_rx->lge_ctl; 977 rxsts = cur_rx->lge_sts; 978 m = cur_rx->lge_mbuf; 979 cur_rx->lge_mbuf = NULL; 980 total_len = LGE_RXBYTES(cur_rx); 981 LGE_INC(i, LGE_RX_LIST_CNT); 982 c--; 983 984 /* 985 * If an error occurs, update stats, clear the 986 * status word and leave the mbuf cluster in place: 987 * it should simply get re-used next time this descriptor 988 * comes up in the ring. 989 */ 990 if (rxctl & LGE_RXCTL_ERRMASK) { 991 ifp->if_ierrors++; 992 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 993 continue; 994 } 995 996 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 997 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 998 ifp, NULL); 999 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1000 if (m0 == NULL) { 1001 printf("lge%d: no receive buffers " 1002 "available -- packet dropped!\n", 1003 sc->lge_unit); 1004 ifp->if_ierrors++; 1005 continue; 1006 } 1007 m = m0; 1008 } else { 1009 m->m_pkthdr.rcvif = ifp; 1010 m->m_pkthdr.len = m->m_len = total_len; 1011 } 1012 1013 ifp->if_ipackets++; 1014 eh = mtod(m, struct ether_header *); 1015 1016 /* Remove header from mbuf and pass it on. */ 1017 m_adj(m, sizeof(struct ether_header)); 1018 1019 /* Do IP checksum checking. */ 1020 if (rxsts & LGE_RXSTS_ISIP) 1021 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1022 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1023 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1024 if ((rxsts & LGE_RXSTS_ISTCP && 1025 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1026 (rxsts & LGE_RXSTS_ISUDP && 1027 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1028 m->m_pkthdr.csum_flags |= 1029 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1030 m->m_pkthdr.csum_data = 0xffff; 1031 } 1032 1033 ether_input(ifp, eh, m); 1034 } 1035 1036 sc->lge_cdata.lge_rx_cons = i; 1037 1038 return; 1039} 1040 1041void lge_rxeoc(sc) 1042 struct lge_softc *sc; 1043{ 1044 struct ifnet *ifp; 1045 1046 ifp = &sc->arpcom.ac_if; 1047 ifp->if_flags &= ~IFF_RUNNING; 1048 lge_init(sc); 1049 return; 1050} 1051 1052/* 1053 * A frame was downloaded to the chip. It's safe for us to clean up 1054 * the list buffers. 1055 */ 1056 1057static void lge_txeof(sc) 1058 struct lge_softc *sc; 1059{ 1060 struct lge_tx_desc *cur_tx = NULL; 1061 struct ifnet *ifp; 1062 u_int32_t idx, txdone; 1063 1064 ifp = &sc->arpcom.ac_if; 1065 1066 /* Clear the timeout timer. */ 1067 ifp->if_timer = 0; 1068 1069 /* 1070 * Go through our tx list and free mbufs for those 1071 * frames that have been transmitted. 1072 */ 1073 idx = sc->lge_cdata.lge_tx_cons; 1074 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1075 1076 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1077 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1078 1079 ifp->if_opackets++; 1080 if (cur_tx->lge_mbuf != NULL) { 1081 m_freem(cur_tx->lge_mbuf); 1082 cur_tx->lge_mbuf = NULL; 1083 } 1084 cur_tx->lge_ctl = 0; 1085 1086 txdone--; 1087 LGE_INC(idx, LGE_TX_LIST_CNT); 1088 ifp->if_timer = 0; 1089 } 1090 1091 sc->lge_cdata.lge_tx_cons = idx; 1092 1093 if (cur_tx != NULL) 1094 ifp->if_flags &= ~IFF_OACTIVE; 1095 1096 return; 1097} 1098 1099static void lge_tick(xsc) 1100 void *xsc; 1101{ 1102 struct lge_softc *sc; 1103 struct mii_data *mii; 1104 struct ifnet *ifp; 1105 int s; 1106 1107 s = splimp(); 1108 1109 sc = xsc; 1110 ifp = &sc->arpcom.ac_if; 1111 1112 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1113 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1114 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1115 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1116 1117 if (!sc->lge_link) { 1118 mii = device_get_softc(sc->lge_miibus); 1119 mii_tick(mii); 1120 if (mii->mii_media_status & IFM_ACTIVE && 1121 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1122 sc->lge_link++; 1123 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1124 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1125 printf("lge%d: gigabit link up\n", 1126 sc->lge_unit); 1127 if (ifp->if_snd.ifq_head != NULL) 1128 lge_start(ifp); 1129 } 1130 } 1131 1132 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1133 1134 splx(s); 1135 1136 return; 1137} 1138 1139static void lge_intr(arg) 1140 void *arg; 1141{ 1142 struct lge_softc *sc; 1143 struct ifnet *ifp; 1144 u_int32_t status; 1145 1146 sc = arg; 1147 ifp = &sc->arpcom.ac_if; 1148 1149 /* Supress unwanted interrupts */ 1150 if (!(ifp->if_flags & IFF_UP)) { 1151 lge_stop(sc); 1152 return; 1153 } 1154 1155 for (;;) { 1156 /* 1157 * Reading the ISR register clears all interrupts, and 1158 * clears the 'interrupts enabled' bit in the IMR 1159 * register. 1160 */ 1161 status = CSR_READ_4(sc, LGE_ISR); 1162 1163 if ((status & LGE_INTRS) == 0) 1164 break; 1165 1166 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1167 lge_txeof(sc); 1168 1169 if (status & LGE_ISR_RXDMA_DONE) 1170 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1171 1172 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1173 lge_rxeoc(sc); 1174 1175 if (status & LGE_ISR_PHY_INTR) { 1176 sc->lge_link = 0; 1177 untimeout(lge_tick, sc, sc->lge_stat_ch); 1178 lge_tick(sc); 1179 } 1180 } 1181 1182 /* Re-enable interrupts. */ 1183 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1184 1185 if (ifp->if_snd.ifq_head != NULL) 1186 lge_start(ifp); 1187 1188 return; 1189} 1190 1191/* 1192 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1193 * pointers to the fragment pointers. 1194 */ 1195static int lge_encap(sc, m_head, txidx) 1196 struct lge_softc *sc; 1197 struct mbuf *m_head; 1198 u_int32_t *txidx; 1199{ 1200 struct lge_frag *f = NULL; 1201 struct lge_tx_desc *cur_tx; 1202 struct mbuf *m; 1203 int frag = 0, tot_len = 0; 1204 1205 /* 1206 * Start packing the mbufs in this chain into 1207 * the fragment pointers. Stop when we run out 1208 * of fragments or hit the end of the mbuf chain. 1209 */ 1210 m = m_head; 1211 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1212 frag = 0; 1213 1214 for (m = m_head; m != NULL; m = m->m_next) { 1215 if (m->m_len != 0) { 1216 tot_len += m->m_len; 1217 f = &cur_tx->lge_frags[frag]; 1218 f->lge_fraglen = m->m_len; 1219 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1220 f->lge_fragptr_hi = 0; 1221 frag++; 1222 } 1223 } 1224 1225 if (m != NULL) 1226 return(ENOBUFS); 1227 1228 cur_tx->lge_mbuf = m_head; 1229 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1230 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1231 1232 /* Queue for transmit */ 1233 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1234 1235 return(0); 1236} 1237 1238/* 1239 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1240 * to the mbuf data regions directly in the transmit lists. We also save a 1241 * copy of the pointers since the transmit list fragment pointers are 1242 * physical addresses. 1243 */ 1244 1245static void lge_start(ifp) 1246 struct ifnet *ifp; 1247{ 1248 struct lge_softc *sc; 1249 struct mbuf *m_head = NULL; 1250 u_int32_t idx; 1251 1252 sc = ifp->if_softc; 1253 1254 if (!sc->lge_link) 1255 return; 1256 1257 idx = sc->lge_cdata.lge_tx_prod; 1258 1259 if (ifp->if_flags & IFF_OACTIVE) 1260 return; 1261 1262 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1263 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1264 break; 1265 1266 IF_DEQUEUE(&ifp->if_snd, m_head); 1267 if (m_head == NULL) 1268 break; 1269 1270 if (lge_encap(sc, m_head, &idx)) { 1271 IF_PREPEND(&ifp->if_snd, m_head); 1272 ifp->if_flags |= IFF_OACTIVE; 1273 break; 1274 } 1275 1276 /* 1277 * If there's a BPF listener, bounce a copy of this frame 1278 * to him. 1279 */ 1280 if (ifp->if_bpf) 1281 bpf_mtap(ifp, m_head); 1282 } 1283 1284 sc->lge_cdata.lge_tx_prod = idx; 1285 1286 /* 1287 * Set a timeout in case the chip goes out to lunch. 1288 */ 1289 ifp->if_timer = 5; 1290 1291 return; 1292} 1293 1294static void lge_init(xsc) 1295 void *xsc; 1296{ 1297 struct lge_softc *sc = xsc; 1298 struct ifnet *ifp = &sc->arpcom.ac_if; 1299 struct mii_data *mii; 1300 int s; 1301 1302 if (ifp->if_flags & IFF_RUNNING) 1303 return; 1304 1305 s = splimp(); 1306 1307 /* 1308 * Cancel pending I/O and free all RX/TX buffers. 1309 */ 1310 lge_stop(sc); 1311 lge_reset(sc); 1312 1313 mii = device_get_softc(sc->lge_miibus); 1314 1315 /* Set MAC address */ 1316 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1317 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1318 1319 /* Init circular RX list. */ 1320 if (lge_list_rx_init(sc) == ENOBUFS) { 1321 printf("lge%d: initialization failed: no " 1322 "memory for rx buffers\n", sc->lge_unit); 1323 lge_stop(sc); 1324 (void)splx(s); 1325 return; 1326 } 1327 1328 /* 1329 * Init tx descriptors. 1330 */ 1331 lge_list_tx_init(sc); 1332 1333 /* Set initial value for MODE1 register. */ 1334 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1335 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1336 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1337 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1338 1339 /* If we want promiscuous mode, set the allframes bit. */ 1340 if (ifp->if_flags & IFF_PROMISC) { 1341 CSR_WRITE_4(sc, LGE_MODE1, 1342 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1343 } else { 1344 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1345 } 1346 1347 /* 1348 * Set the capture broadcast bit to capture broadcast frames. 1349 */ 1350 if (ifp->if_flags & IFF_BROADCAST) { 1351 CSR_WRITE_4(sc, LGE_MODE1, 1352 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1353 } else { 1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1355 } 1356 1357 /* Packet padding workaround? */ 1358 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1359 1360 /* No error frames */ 1361 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1362 1363 /* Receive large frames */ 1364 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1365 1366 /* Workaround: disable RX/TX flow control */ 1367 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1368 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1369 1370 /* Make sure to strip CRC from received frames */ 1371 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1372 1373 /* Turn off magic packet mode */ 1374 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1375 1376 /* Turn off all VLAN stuff */ 1377 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1378 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1379 1380 /* Workarond: FIFO overflow */ 1381 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1382 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1383 1384 /* 1385 * Load the multicast filter. 1386 */ 1387 lge_setmulti(sc); 1388 1389 /* 1390 * Enable hardware checksum validation for all received IPv4 1391 * packets, do not reject packets with bad checksums. 1392 */ 1393 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1394 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1395 LGE_MODE2_RX_ERRCSUM); 1396 1397 /* 1398 * Enable the delivery of PHY interrupts based on 1399 * link/speed/duplex status chalges. 1400 */ 1401 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1402 1403 /* Enable receiver and transmitter. */ 1404 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1405 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1406 1407 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1408 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1409 1410 /* 1411 * Enable interrupts. 1412 */ 1413 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1414 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1415 1416 lge_ifmedia_upd(ifp); 1417 1418 ifp->if_flags |= IFF_RUNNING; 1419 ifp->if_flags &= ~IFF_OACTIVE; 1420 1421 (void)splx(s); 1422 1423 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1424 1425 return; 1426} 1427 1428/* 1429 * Set media options. 1430 */ 1431static int lge_ifmedia_upd(ifp) 1432 struct ifnet *ifp; 1433{ 1434 struct lge_softc *sc; 1435 struct mii_data *mii; 1436 1437 sc = ifp->if_softc; 1438 1439 mii = device_get_softc(sc->lge_miibus); 1440 sc->lge_link = 0; 1441 if (mii->mii_instance) { 1442 struct mii_softc *miisc; 1443 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1444 miisc = LIST_NEXT(miisc, mii_list)) 1445 mii_phy_reset(miisc); 1446 } 1447 mii_mediachg(mii); 1448 1449 return(0); 1450} 1451 1452/* 1453 * Report current media status. 1454 */ 1455static void lge_ifmedia_sts(ifp, ifmr) 1456 struct ifnet *ifp; 1457 struct ifmediareq *ifmr; 1458{ 1459 struct lge_softc *sc; 1460 struct mii_data *mii; 1461 1462 sc = ifp->if_softc; 1463 1464 mii = device_get_softc(sc->lge_miibus); 1465 mii_pollstat(mii); 1466 ifmr->ifm_active = mii->mii_media_active; 1467 ifmr->ifm_status = mii->mii_media_status; 1468 1469 return; 1470} 1471 1472static int lge_ioctl(ifp, command, data) 1473 struct ifnet *ifp; 1474 u_long command; 1475 caddr_t data; 1476{ 1477 struct lge_softc *sc = ifp->if_softc; 1478 struct ifreq *ifr = (struct ifreq *) data; 1479 struct mii_data *mii; 1480 int s, error = 0; 1481 1482 s = splimp(); 1483 1484 switch(command) { 1485 case SIOCSIFADDR: 1486 case SIOCGIFADDR: 1487 error = ether_ioctl(ifp, command, data); 1488 break; 1489 case SIOCSIFMTU: 1490 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1491 error = EINVAL; 1492 else 1493 ifp->if_mtu = ifr->ifr_mtu; 1494 break; 1495 case SIOCSIFFLAGS: 1496 if (ifp->if_flags & IFF_UP) { 1497 if (ifp->if_flags & IFF_RUNNING && 1498 ifp->if_flags & IFF_PROMISC && 1499 !(sc->lge_if_flags & IFF_PROMISC)) { 1500 CSR_WRITE_4(sc, LGE_MODE1, 1501 LGE_MODE1_SETRST_CTL1| 1502 LGE_MODE1_RX_PROMISC); 1503 } else if (ifp->if_flags & IFF_RUNNING && 1504 !(ifp->if_flags & IFF_PROMISC) && 1505 sc->lge_if_flags & IFF_PROMISC) { 1506 CSR_WRITE_4(sc, LGE_MODE1, 1507 LGE_MODE1_RX_PROMISC); 1508 } else { 1509 ifp->if_flags &= ~IFF_RUNNING; 1510 lge_init(sc); 1511 } 1512 } else { 1513 if (ifp->if_flags & IFF_RUNNING) 1514 lge_stop(sc); 1515 } 1516 sc->lge_if_flags = ifp->if_flags; 1517 error = 0; 1518 break; 1519 case SIOCADDMULTI: 1520 case SIOCDELMULTI: 1521 lge_setmulti(sc); 1522 error = 0; 1523 break; 1524 case SIOCGIFMEDIA: 1525 case SIOCSIFMEDIA: 1526 mii = device_get_softc(sc->lge_miibus); 1527 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1528 break; 1529 default: 1530 error = EINVAL; 1531 break; 1532 } 1533 1534 (void)splx(s); 1535 1536 return(error); 1537} 1538 1539static void lge_watchdog(ifp) 1540 struct ifnet *ifp; 1541{ 1542 struct lge_softc *sc; 1543 1544 sc = ifp->if_softc; 1545 1546 ifp->if_oerrors++; 1547 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1548 1549 lge_stop(sc); 1550 lge_reset(sc); 1551 ifp->if_flags &= ~IFF_RUNNING; 1552 lge_init(sc); 1553 1554 if (ifp->if_snd.ifq_head != NULL) 1555 lge_start(ifp); 1556 1557 return; 1558} 1559 1560/* 1561 * Stop the adapter and free any mbufs allocated to the 1562 * RX and TX lists. 1563 */ 1564static void lge_stop(sc) 1565 struct lge_softc *sc; 1566{ 1567 register int i; 1568 struct ifnet *ifp; 1569 1570 ifp = &sc->arpcom.ac_if; 1571 ifp->if_timer = 0; 1572 untimeout(lge_tick, sc, sc->lge_stat_ch); 1573 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1574 1575 /* Disable receiver and transmitter. */ 1576 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1577 sc->lge_link = 0; 1578 1579 /* 1580 * Free data in the RX lists. 1581 */ 1582 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1583 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1584 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1585 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1586 } 1587 } 1588 bzero((char *)&sc->lge_ldata->lge_rx_list, 1589 sizeof(sc->lge_ldata->lge_rx_list)); 1590 1591 /* 1592 * Free the TX list buffers. 1593 */ 1594 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1595 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1596 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1597 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1598 } 1599 } 1600 1601 bzero((char *)&sc->lge_ldata->lge_tx_list, 1602 sizeof(sc->lge_ldata->lge_tx_list)); 1603 1604 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1605 1606 return; 1607} 1608 1609/* 1610 * Stop all chip I/O so that the kernel's probe routines don't 1611 * get confused by errant DMAs when rebooting. 1612 */ 1613static void lge_shutdown(dev) 1614 device_t dev; 1615{ 1616 struct lge_softc *sc; 1617 1618 sc = device_get_softc(dev); 1619 1620 lge_reset(sc); 1621 lge_stop(sc); 1622 1623 return; 1624} 1625