if_lge.c revision 229767
1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 229767 2012-01-07 09:41:57Z kevlo $"); 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/module.h> 79#include <sys/socket.h> 80 81#include <net/if.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_dl.h> 85#include <net/if_media.h> 86#include <net/if_types.h> 87 88#include <net/bpf.h> 89 90#include <vm/vm.h> /* for vtophys */ 91#include <vm/pmap.h> /* for vtophys */ 92#include <machine/bus.h> 93#include <machine/resource.h> 94#include <sys/bus.h> 95#include <sys/rman.h> 96 97#include <dev/mii/mii.h> 98#include <dev/mii/miivar.h> 99 100#include <dev/pci/pcireg.h> 101#include <dev/pci/pcivar.h> 102 103#define LGE_USEIOSPACE 104 105#include <dev/lge/if_lgereg.h> 106 107/* "device miibus" required. See GENERIC if you get errors here. */ 108#include "miibus_if.h" 109 110/* 111 * Various supported device vendors/types and their names. 112 */ 113static const struct lge_type const lge_devs[] = { 114 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 115 { 0, 0, NULL } 116}; 117 118static int lge_probe(device_t); 119static int lge_attach(device_t); 120static int lge_detach(device_t); 121 122static int lge_alloc_jumbo_mem(struct lge_softc *); 123static void lge_free_jumbo_mem(struct lge_softc *); 124static void *lge_jalloc(struct lge_softc *); 125static void lge_jfree(void *, void *); 126 127static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 128static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 129static void lge_rxeof(struct lge_softc *, int); 130static void lge_rxeoc(struct lge_softc *); 131static void lge_txeof(struct lge_softc *); 132static void lge_intr(void *); 133static void lge_tick(void *); 134static void lge_start(struct ifnet *); 135static void lge_start_locked(struct ifnet *); 136static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137static void lge_init(void *); 138static void lge_init_locked(struct lge_softc *); 139static void lge_stop(struct lge_softc *); 140static void lge_watchdog(struct lge_softc *); 141static int lge_shutdown(device_t); 142static int lge_ifmedia_upd(struct ifnet *); 143static void lge_ifmedia_upd_locked(struct ifnet *); 144static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 145 146static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 147static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 148 149static int lge_miibus_readreg(device_t, int, int); 150static int lge_miibus_writereg(device_t, int, int, int); 151static void lge_miibus_statchg(device_t); 152 153static void lge_setmulti(struct lge_softc *); 154static void lge_reset(struct lge_softc *); 155static int lge_list_rx_init(struct lge_softc *); 156static int lge_list_tx_init(struct lge_softc *); 157 158#ifdef LGE_USEIOSPACE 159#define LGE_RES SYS_RES_IOPORT 160#define LGE_RID LGE_PCI_LOIO 161#else 162#define LGE_RES SYS_RES_MEMORY 163#define LGE_RID LGE_PCI_LOMEM 164#endif 165 166static device_method_t lge_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, lge_probe), 169 DEVMETHOD(device_attach, lge_attach), 170 DEVMETHOD(device_detach, lge_detach), 171 DEVMETHOD(device_shutdown, lge_shutdown), 172 173 /* MII interface */ 174 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 175 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 176 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 177 178 DEVMETHOD_END 179}; 180 181static driver_t lge_driver = { 182 "lge", 183 lge_methods, 184 sizeof(struct lge_softc) 185}; 186 187static devclass_t lge_devclass; 188 189DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 190DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 191MODULE_DEPEND(lge, pci, 1, 1, 1); 192MODULE_DEPEND(lge, ether, 1, 1, 1); 193MODULE_DEPEND(lge, miibus, 1, 1, 1); 194 195#define LGE_SETBIT(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, \ 197 CSR_READ_4(sc, reg) | (x)) 198 199#define LGE_CLRBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, \ 201 CSR_READ_4(sc, reg) & ~(x)) 202 203#define SIO_SET(x) \ 204 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 205 206#define SIO_CLR(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 208 209/* 210 * Read a word of data stored in the EEPROM at address 'addr.' 211 */ 212static void 213lge_eeprom_getword(sc, addr, dest) 214 struct lge_softc *sc; 215 int addr; 216 u_int16_t *dest; 217{ 218 register int i; 219 u_int32_t val; 220 221 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 222 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 223 224 for (i = 0; i < LGE_TIMEOUT; i++) 225 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 226 break; 227 228 if (i == LGE_TIMEOUT) { 229 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 230 return; 231 } 232 233 val = CSR_READ_4(sc, LGE_EEDATA); 234 235 if (addr & 1) 236 *dest = (val >> 16) & 0xFFFF; 237 else 238 *dest = val & 0xFFFF; 239 240 return; 241} 242 243/* 244 * Read a sequence of words from the EEPROM. 245 */ 246static void 247lge_read_eeprom(sc, dest, off, cnt, swap) 248 struct lge_softc *sc; 249 caddr_t dest; 250 int off; 251 int cnt; 252 int swap; 253{ 254 int i; 255 u_int16_t word = 0, *ptr; 256 257 for (i = 0; i < cnt; i++) { 258 lge_eeprom_getword(sc, off + i, &word); 259 ptr = (u_int16_t *)(dest + (i * 2)); 260 if (swap) 261 *ptr = ntohs(word); 262 else 263 *ptr = word; 264 } 265 266 return; 267} 268 269static int 270lge_miibus_readreg(dev, phy, reg) 271 device_t dev; 272 int phy, reg; 273{ 274 struct lge_softc *sc; 275 int i; 276 277 sc = device_get_softc(dev); 278 279 /* 280 * If we have a non-PCS PHY, pretend that the internal 281 * autoneg stuff at PHY address 0 isn't there so that 282 * the miibus code will find only the GMII PHY. 283 */ 284 if (sc->lge_pcs == 0 && phy == 0) 285 return(0); 286 287 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 288 289 for (i = 0; i < LGE_TIMEOUT; i++) 290 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 291 break; 292 293 if (i == LGE_TIMEOUT) { 294 device_printf(sc->lge_dev, "PHY read timed out\n"); 295 return(0); 296 } 297 298 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 299} 300 301static int 302lge_miibus_writereg(dev, phy, reg, data) 303 device_t dev; 304 int phy, reg, data; 305{ 306 struct lge_softc *sc; 307 int i; 308 309 sc = device_get_softc(dev); 310 311 CSR_WRITE_4(sc, LGE_GMIICTL, 312 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 313 314 for (i = 0; i < LGE_TIMEOUT; i++) 315 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 316 break; 317 318 if (i == LGE_TIMEOUT) { 319 device_printf(sc->lge_dev, "PHY write timed out\n"); 320 return(0); 321 } 322 323 return(0); 324} 325 326static void 327lge_miibus_statchg(dev) 328 device_t dev; 329{ 330 struct lge_softc *sc; 331 struct mii_data *mii; 332 333 sc = device_get_softc(dev); 334 mii = device_get_softc(sc->lge_miibus); 335 336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 337 switch (IFM_SUBTYPE(mii->mii_media_active)) { 338 case IFM_1000_T: 339 case IFM_1000_SX: 340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 341 break; 342 case IFM_100_TX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 344 break; 345 case IFM_10_T: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 347 break; 348 default: 349 /* 350 * Choose something, even if it's wrong. Clearing 351 * all the bits will hose autoneg on the internal 352 * PHY. 353 */ 354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 355 break; 356 } 357 358 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 359 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 360 } else { 361 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 362 } 363 364 return; 365} 366 367static void 368lge_setmulti(sc) 369 struct lge_softc *sc; 370{ 371 struct ifnet *ifp; 372 struct ifmultiaddr *ifma; 373 u_int32_t h = 0, hashes[2] = { 0, 0 }; 374 375 ifp = sc->lge_ifp; 376 LGE_LOCK_ASSERT(sc); 377 378 /* Make sure multicast hash table is enabled. */ 379 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 380 381 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 382 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 383 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 384 return; 385 } 386 387 /* first, zot all the existing hash bits */ 388 CSR_WRITE_4(sc, LGE_MAR0, 0); 389 CSR_WRITE_4(sc, LGE_MAR1, 0); 390 391 /* now program new ones */ 392 if_maddr_rlock(ifp); 393 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 394 if (ifma->ifma_addr->sa_family != AF_LINK) 395 continue; 396 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 397 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 398 if (h < 32) 399 hashes[0] |= (1 << h); 400 else 401 hashes[1] |= (1 << (h - 32)); 402 } 403 if_maddr_runlock(ifp); 404 405 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 406 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 407 408 return; 409} 410 411static void 412lge_reset(sc) 413 struct lge_softc *sc; 414{ 415 register int i; 416 417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 418 419 for (i = 0; i < LGE_TIMEOUT; i++) { 420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 421 break; 422 } 423 424 if (i == LGE_TIMEOUT) 425 device_printf(sc->lge_dev, "reset never completed\n"); 426 427 /* Wait a little while for the chip to get its brains in order. */ 428 DELAY(1000); 429 430 return; 431} 432 433/* 434 * Probe for a Level 1 chip. Check the PCI vendor and device 435 * IDs against our list and return a device name if we find a match. 436 */ 437static int 438lge_probe(dev) 439 device_t dev; 440{ 441 const struct lge_type *t; 442 443 t = lge_devs; 444 445 while(t->lge_name != NULL) { 446 if ((pci_get_vendor(dev) == t->lge_vid) && 447 (pci_get_device(dev) == t->lge_did)) { 448 device_set_desc(dev, t->lge_name); 449 return(BUS_PROBE_DEFAULT); 450 } 451 t++; 452 } 453 454 return(ENXIO); 455} 456 457/* 458 * Attach the interface. Allocate softc structures, do ifmedia 459 * setup and ethernet/BPF attach. 460 */ 461static int 462lge_attach(dev) 463 device_t dev; 464{ 465 u_char eaddr[ETHER_ADDR_LEN]; 466 struct lge_softc *sc; 467 struct ifnet *ifp = NULL; 468 int error = 0, rid; 469 470 sc = device_get_softc(dev); 471 sc->lge_dev = dev; 472 473 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 474 MTX_DEF); 475 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 476 477 /* 478 * Map control/status registers. 479 */ 480 pci_enable_busmaster(dev); 481 482 rid = LGE_RID; 483 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 484 485 if (sc->lge_res == NULL) { 486 device_printf(dev, "couldn't map ports/memory\n"); 487 error = ENXIO; 488 goto fail; 489 } 490 491 sc->lge_btag = rman_get_bustag(sc->lge_res); 492 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 493 494 /* Allocate interrupt */ 495 rid = 0; 496 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 497 RF_SHAREABLE | RF_ACTIVE); 498 499 if (sc->lge_irq == NULL) { 500 device_printf(dev, "couldn't map interrupt\n"); 501 error = ENXIO; 502 goto fail; 503 } 504 505 /* Reset the adapter. */ 506 lge_reset(sc); 507 508 /* 509 * Get station address from the EEPROM. 510 */ 511 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 512 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 513 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 514 515 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 516 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 517 518 if (sc->lge_ldata == NULL) { 519 device_printf(dev, "no memory for list buffers!\n"); 520 error = ENXIO; 521 goto fail; 522 } 523 524 /* Try to allocate memory for jumbo buffers. */ 525 if (lge_alloc_jumbo_mem(sc)) { 526 device_printf(dev, "jumbo buffer allocation failed\n"); 527 error = ENXIO; 528 goto fail; 529 } 530 531 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 532 if (ifp == NULL) { 533 device_printf(dev, "can not if_alloc()\n"); 534 error = ENOSPC; 535 goto fail; 536 } 537 ifp->if_softc = sc; 538 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 539 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 540 ifp->if_ioctl = lge_ioctl; 541 ifp->if_start = lge_start; 542 ifp->if_init = lge_init; 543 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 544 ifp->if_capabilities = IFCAP_RXCSUM; 545 ifp->if_capenable = ifp->if_capabilities; 546 547 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 548 sc->lge_pcs = 1; 549 else 550 sc->lge_pcs = 0; 551 552 /* 553 * Do MII setup. 554 */ 555 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 556 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 557 if (error != 0) { 558 device_printf(dev, "attaching PHYs failed\n"); 559 goto fail; 560 } 561 562 /* 563 * Call MI attach routine. 564 */ 565 ether_ifattach(ifp, eaddr); 566 567 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 568 NULL, lge_intr, sc, &sc->lge_intrhand); 569 570 if (error) { 571 ether_ifdetach(ifp); 572 device_printf(dev, "couldn't set up irq\n"); 573 goto fail; 574 } 575 return (0); 576 577fail: 578 lge_free_jumbo_mem(sc); 579 if (sc->lge_ldata) 580 contigfree(sc->lge_ldata, 581 sizeof(struct lge_list_data), M_DEVBUF); 582 if (ifp) 583 if_free(ifp); 584 if (sc->lge_irq) 585 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 586 if (sc->lge_res) 587 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 588 mtx_destroy(&sc->lge_mtx); 589 return(error); 590} 591 592static int 593lge_detach(dev) 594 device_t dev; 595{ 596 struct lge_softc *sc; 597 struct ifnet *ifp; 598 599 sc = device_get_softc(dev); 600 ifp = sc->lge_ifp; 601 602 LGE_LOCK(sc); 603 lge_reset(sc); 604 lge_stop(sc); 605 LGE_UNLOCK(sc); 606 callout_drain(&sc->lge_stat_callout); 607 ether_ifdetach(ifp); 608 609 bus_generic_detach(dev); 610 device_delete_child(dev, sc->lge_miibus); 611 612 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 613 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 614 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 615 616 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 617 if_free(ifp); 618 lge_free_jumbo_mem(sc); 619 mtx_destroy(&sc->lge_mtx); 620 621 return(0); 622} 623 624/* 625 * Initialize the transmit descriptors. 626 */ 627static int 628lge_list_tx_init(sc) 629 struct lge_softc *sc; 630{ 631 struct lge_list_data *ld; 632 struct lge_ring_data *cd; 633 int i; 634 635 cd = &sc->lge_cdata; 636 ld = sc->lge_ldata; 637 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 638 ld->lge_tx_list[i].lge_mbuf = NULL; 639 ld->lge_tx_list[i].lge_ctl = 0; 640 } 641 642 cd->lge_tx_prod = cd->lge_tx_cons = 0; 643 644 return(0); 645} 646 647 648/* 649 * Initialize the RX descriptors and allocate mbufs for them. Note that 650 * we arralge the descriptors in a closed ring, so that the last descriptor 651 * points back to the first. 652 */ 653static int 654lge_list_rx_init(sc) 655 struct lge_softc *sc; 656{ 657 struct lge_list_data *ld; 658 struct lge_ring_data *cd; 659 int i; 660 661 ld = sc->lge_ldata; 662 cd = &sc->lge_cdata; 663 664 cd->lge_rx_prod = cd->lge_rx_cons = 0; 665 666 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 667 668 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 669 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 670 break; 671 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 672 return(ENOBUFS); 673 } 674 675 /* Clear possible 'rx command queue empty' interrupt. */ 676 CSR_READ_4(sc, LGE_ISR); 677 678 return(0); 679} 680 681/* 682 * Initialize an RX descriptor and attach an MBUF cluster. 683 */ 684static int 685lge_newbuf(sc, c, m) 686 struct lge_softc *sc; 687 struct lge_rx_desc *c; 688 struct mbuf *m; 689{ 690 struct mbuf *m_new = NULL; 691 caddr_t *buf = NULL; 692 693 if (m == NULL) { 694 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 695 if (m_new == NULL) { 696 device_printf(sc->lge_dev, "no memory for rx list " 697 "-- packet dropped!\n"); 698 return(ENOBUFS); 699 } 700 701 /* Allocate the jumbo buffer */ 702 buf = lge_jalloc(sc); 703 if (buf == NULL) { 704#ifdef LGE_VERBOSE 705 device_printf(sc->lge_dev, "jumbo allocation failed " 706 "-- packet dropped!\n"); 707#endif 708 m_freem(m_new); 709 return(ENOBUFS); 710 } 711 /* Attach the buffer to the mbuf */ 712 m_new->m_data = (void *)buf; 713 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 714 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 715 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV); 716 } else { 717 m_new = m; 718 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 719 m_new->m_data = m_new->m_ext.ext_buf; 720 } 721 722 /* 723 * Adjust alignment so packet payload begins on a 724 * longword boundary. Mandatory for Alpha, useful on 725 * x86 too. 726 */ 727 m_adj(m_new, ETHER_ALIGN); 728 729 c->lge_mbuf = m_new; 730 c->lge_fragptr_hi = 0; 731 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 732 c->lge_fraglen = m_new->m_len; 733 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 734 c->lge_sts = 0; 735 736 /* 737 * Put this buffer in the RX command FIFO. To do this, 738 * we just write the physical address of the descriptor 739 * into the RX descriptor address registers. Note that 740 * there are two registers, one high DWORD and one low 741 * DWORD, which lets us specify a 64-bit address if 742 * desired. We only use a 32-bit address for now. 743 * Writing to the low DWORD register is what actually 744 * causes the command to be issued, so we do that 745 * last. 746 */ 747 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 748 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 749 750 return(0); 751} 752 753static int 754lge_alloc_jumbo_mem(sc) 755 struct lge_softc *sc; 756{ 757 caddr_t ptr; 758 register int i; 759 struct lge_jpool_entry *entry; 760 761 /* Grab a big chunk o' storage. */ 762 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 763 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 764 765 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 766 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 767 return(ENOBUFS); 768 } 769 770 SLIST_INIT(&sc->lge_jfree_listhead); 771 SLIST_INIT(&sc->lge_jinuse_listhead); 772 773 /* 774 * Now divide it up into 9K pieces and save the addresses 775 * in an array. 776 */ 777 ptr = sc->lge_cdata.lge_jumbo_buf; 778 for (i = 0; i < LGE_JSLOTS; i++) { 779 sc->lge_cdata.lge_jslots[i] = ptr; 780 ptr += LGE_JLEN; 781 entry = malloc(sizeof(struct lge_jpool_entry), 782 M_DEVBUF, M_NOWAIT); 783 if (entry == NULL) { 784 device_printf(sc->lge_dev, "no memory for jumbo " 785 "buffer queue!\n"); 786 return(ENOBUFS); 787 } 788 entry->slot = i; 789 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 790 entry, jpool_entries); 791 } 792 793 return(0); 794} 795 796static void 797lge_free_jumbo_mem(sc) 798 struct lge_softc *sc; 799{ 800 struct lge_jpool_entry *entry; 801 802 if (sc->lge_cdata.lge_jumbo_buf == NULL) 803 return; 804 805 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 806 device_printf(sc->lge_dev, 807 "asked to free buffer that is in use!\n"); 808 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 809 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 810 jpool_entries); 811 } 812 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 813 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 814 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 815 free(entry, M_DEVBUF); 816 } 817 818 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 819 820 return; 821} 822 823/* 824 * Allocate a jumbo buffer. 825 */ 826static void * 827lge_jalloc(sc) 828 struct lge_softc *sc; 829{ 830 struct lge_jpool_entry *entry; 831 832 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 833 834 if (entry == NULL) { 835#ifdef LGE_VERBOSE 836 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 837#endif 838 return(NULL); 839 } 840 841 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 842 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 843 return(sc->lge_cdata.lge_jslots[entry->slot]); 844} 845 846/* 847 * Release a jumbo buffer. 848 */ 849static void 850lge_jfree(buf, args) 851 void *buf; 852 void *args; 853{ 854 struct lge_softc *sc; 855 int i; 856 struct lge_jpool_entry *entry; 857 858 /* Extract the softc struct pointer. */ 859 sc = args; 860 861 if (sc == NULL) 862 panic("lge_jfree: can't find softc pointer!"); 863 864 /* calculate the slot this buffer belongs to */ 865 i = ((vm_offset_t)buf 866 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 867 868 if ((i < 0) || (i >= LGE_JSLOTS)) 869 panic("lge_jfree: asked to free buffer that we don't manage!"); 870 871 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 872 if (entry == NULL) 873 panic("lge_jfree: buffer not in use!"); 874 entry->slot = i; 875 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 876 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 877 878 return; 879} 880 881/* 882 * A frame has been uploaded: pass the resulting mbuf chain up to 883 * the higher level protocols. 884 */ 885static void 886lge_rxeof(sc, cnt) 887 struct lge_softc *sc; 888 int cnt; 889{ 890 struct mbuf *m; 891 struct ifnet *ifp; 892 struct lge_rx_desc *cur_rx; 893 int c, i, total_len = 0; 894 u_int32_t rxsts, rxctl; 895 896 ifp = sc->lge_ifp; 897 898 /* Find out how many frames were processed. */ 899 c = cnt; 900 i = sc->lge_cdata.lge_rx_cons; 901 902 /* Suck them in. */ 903 while(c) { 904 struct mbuf *m0 = NULL; 905 906 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 907 rxctl = cur_rx->lge_ctl; 908 rxsts = cur_rx->lge_sts; 909 m = cur_rx->lge_mbuf; 910 cur_rx->lge_mbuf = NULL; 911 total_len = LGE_RXBYTES(cur_rx); 912 LGE_INC(i, LGE_RX_LIST_CNT); 913 c--; 914 915 /* 916 * If an error occurs, update stats, clear the 917 * status word and leave the mbuf cluster in place: 918 * it should simply get re-used next time this descriptor 919 * comes up in the ring. 920 */ 921 if (rxctl & LGE_RXCTL_ERRMASK) { 922 ifp->if_ierrors++; 923 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 924 continue; 925 } 926 927 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 928 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 929 ifp, NULL); 930 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 931 if (m0 == NULL) { 932 device_printf(sc->lge_dev, "no receive buffers " 933 "available -- packet dropped!\n"); 934 ifp->if_ierrors++; 935 continue; 936 } 937 m = m0; 938 } else { 939 m->m_pkthdr.rcvif = ifp; 940 m->m_pkthdr.len = m->m_len = total_len; 941 } 942 943 ifp->if_ipackets++; 944 945 /* Do IP checksum checking. */ 946 if (rxsts & LGE_RXSTS_ISIP) 947 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 948 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 949 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 950 if ((rxsts & LGE_RXSTS_ISTCP && 951 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 952 (rxsts & LGE_RXSTS_ISUDP && 953 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 954 m->m_pkthdr.csum_flags |= 955 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 956 m->m_pkthdr.csum_data = 0xffff; 957 } 958 959 LGE_UNLOCK(sc); 960 (*ifp->if_input)(ifp, m); 961 LGE_LOCK(sc); 962 } 963 964 sc->lge_cdata.lge_rx_cons = i; 965 966 return; 967} 968 969static void 970lge_rxeoc(sc) 971 struct lge_softc *sc; 972{ 973 struct ifnet *ifp; 974 975 ifp = sc->lge_ifp; 976 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 977 lge_init_locked(sc); 978 return; 979} 980 981/* 982 * A frame was downloaded to the chip. It's safe for us to clean up 983 * the list buffers. 984 */ 985 986static void 987lge_txeof(sc) 988 struct lge_softc *sc; 989{ 990 struct lge_tx_desc *cur_tx = NULL; 991 struct ifnet *ifp; 992 u_int32_t idx, txdone; 993 994 ifp = sc->lge_ifp; 995 996 /* Clear the timeout timer. */ 997 sc->lge_timer = 0; 998 999 /* 1000 * Go through our tx list and free mbufs for those 1001 * frames that have been transmitted. 1002 */ 1003 idx = sc->lge_cdata.lge_tx_cons; 1004 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1005 1006 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1007 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1008 1009 ifp->if_opackets++; 1010 if (cur_tx->lge_mbuf != NULL) { 1011 m_freem(cur_tx->lge_mbuf); 1012 cur_tx->lge_mbuf = NULL; 1013 } 1014 cur_tx->lge_ctl = 0; 1015 1016 txdone--; 1017 LGE_INC(idx, LGE_TX_LIST_CNT); 1018 sc->lge_timer = 0; 1019 } 1020 1021 sc->lge_cdata.lge_tx_cons = idx; 1022 1023 if (cur_tx != NULL) 1024 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1025 1026 return; 1027} 1028 1029static void 1030lge_tick(xsc) 1031 void *xsc; 1032{ 1033 struct lge_softc *sc; 1034 struct mii_data *mii; 1035 struct ifnet *ifp; 1036 1037 sc = xsc; 1038 ifp = sc->lge_ifp; 1039 LGE_LOCK_ASSERT(sc); 1040 1041 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1042 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1043 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1044 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1045 1046 if (!sc->lge_link) { 1047 mii = device_get_softc(sc->lge_miibus); 1048 mii_tick(mii); 1049 if (mii->mii_media_status & IFM_ACTIVE && 1050 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1051 sc->lge_link++; 1052 if (bootverbose && 1053 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1054 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1055 device_printf(sc->lge_dev, "gigabit link up\n"); 1056 if (ifp->if_snd.ifq_head != NULL) 1057 lge_start_locked(ifp); 1058 } 1059 } 1060 1061 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1062 lge_watchdog(sc); 1063 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1064 1065 return; 1066} 1067 1068static void 1069lge_intr(arg) 1070 void *arg; 1071{ 1072 struct lge_softc *sc; 1073 struct ifnet *ifp; 1074 u_int32_t status; 1075 1076 sc = arg; 1077 ifp = sc->lge_ifp; 1078 LGE_LOCK(sc); 1079 1080 /* Supress unwanted interrupts */ 1081 if (!(ifp->if_flags & IFF_UP)) { 1082 lge_stop(sc); 1083 LGE_UNLOCK(sc); 1084 return; 1085 } 1086 1087 for (;;) { 1088 /* 1089 * Reading the ISR register clears all interrupts, and 1090 * clears the 'interrupts enabled' bit in the IMR 1091 * register. 1092 */ 1093 status = CSR_READ_4(sc, LGE_ISR); 1094 1095 if ((status & LGE_INTRS) == 0) 1096 break; 1097 1098 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1099 lge_txeof(sc); 1100 1101 if (status & LGE_ISR_RXDMA_DONE) 1102 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1103 1104 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1105 lge_rxeoc(sc); 1106 1107 if (status & LGE_ISR_PHY_INTR) { 1108 sc->lge_link = 0; 1109 callout_stop(&sc->lge_stat_callout); 1110 lge_tick(sc); 1111 } 1112 } 1113 1114 /* Re-enable interrupts. */ 1115 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1116 1117 if (ifp->if_snd.ifq_head != NULL) 1118 lge_start_locked(ifp); 1119 1120 LGE_UNLOCK(sc); 1121 return; 1122} 1123 1124/* 1125 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1126 * pointers to the fragment pointers. 1127 */ 1128static int 1129lge_encap(sc, m_head, txidx) 1130 struct lge_softc *sc; 1131 struct mbuf *m_head; 1132 u_int32_t *txidx; 1133{ 1134 struct lge_frag *f = NULL; 1135 struct lge_tx_desc *cur_tx; 1136 struct mbuf *m; 1137 int frag = 0, tot_len = 0; 1138 1139 /* 1140 * Start packing the mbufs in this chain into 1141 * the fragment pointers. Stop when we run out 1142 * of fragments or hit the end of the mbuf chain. 1143 */ 1144 m = m_head; 1145 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1146 frag = 0; 1147 1148 for (m = m_head; m != NULL; m = m->m_next) { 1149 if (m->m_len != 0) { 1150 tot_len += m->m_len; 1151 f = &cur_tx->lge_frags[frag]; 1152 f->lge_fraglen = m->m_len; 1153 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1154 f->lge_fragptr_hi = 0; 1155 frag++; 1156 } 1157 } 1158 1159 if (m != NULL) 1160 return(ENOBUFS); 1161 1162 cur_tx->lge_mbuf = m_head; 1163 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1164 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1165 1166 /* Queue for transmit */ 1167 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1168 1169 return(0); 1170} 1171 1172/* 1173 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1174 * to the mbuf data regions directly in the transmit lists. We also save a 1175 * copy of the pointers since the transmit list fragment pointers are 1176 * physical addresses. 1177 */ 1178 1179static void 1180lge_start(ifp) 1181 struct ifnet *ifp; 1182{ 1183 struct lge_softc *sc; 1184 1185 sc = ifp->if_softc; 1186 LGE_LOCK(sc); 1187 lge_start_locked(ifp); 1188 LGE_UNLOCK(sc); 1189} 1190 1191static void 1192lge_start_locked(ifp) 1193 struct ifnet *ifp; 1194{ 1195 struct lge_softc *sc; 1196 struct mbuf *m_head = NULL; 1197 u_int32_t idx; 1198 1199 sc = ifp->if_softc; 1200 1201 if (!sc->lge_link) 1202 return; 1203 1204 idx = sc->lge_cdata.lge_tx_prod; 1205 1206 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1207 return; 1208 1209 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1210 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1211 break; 1212 1213 IF_DEQUEUE(&ifp->if_snd, m_head); 1214 if (m_head == NULL) 1215 break; 1216 1217 if (lge_encap(sc, m_head, &idx)) { 1218 IF_PREPEND(&ifp->if_snd, m_head); 1219 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1220 break; 1221 } 1222 1223 /* 1224 * If there's a BPF listener, bounce a copy of this frame 1225 * to him. 1226 */ 1227 BPF_MTAP(ifp, m_head); 1228 } 1229 1230 sc->lge_cdata.lge_tx_prod = idx; 1231 1232 /* 1233 * Set a timeout in case the chip goes out to lunch. 1234 */ 1235 sc->lge_timer = 5; 1236 1237 return; 1238} 1239 1240static void 1241lge_init(xsc) 1242 void *xsc; 1243{ 1244 struct lge_softc *sc = xsc; 1245 1246 LGE_LOCK(sc); 1247 lge_init_locked(sc); 1248 LGE_UNLOCK(sc); 1249} 1250 1251static void 1252lge_init_locked(sc) 1253 struct lge_softc *sc; 1254{ 1255 struct ifnet *ifp = sc->lge_ifp; 1256 1257 LGE_LOCK_ASSERT(sc); 1258 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1259 return; 1260 1261 /* 1262 * Cancel pending I/O and free all RX/TX buffers. 1263 */ 1264 lge_stop(sc); 1265 lge_reset(sc); 1266 1267 /* Set MAC address */ 1268 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0])); 1269 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4])); 1270 1271 /* Init circular RX list. */ 1272 if (lge_list_rx_init(sc) == ENOBUFS) { 1273 device_printf(sc->lge_dev, "initialization failed: no " 1274 "memory for rx buffers\n"); 1275 lge_stop(sc); 1276 return; 1277 } 1278 1279 /* 1280 * Init tx descriptors. 1281 */ 1282 lge_list_tx_init(sc); 1283 1284 /* Set initial value for MODE1 register. */ 1285 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1286 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1287 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1288 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1289 1290 /* If we want promiscuous mode, set the allframes bit. */ 1291 if (ifp->if_flags & IFF_PROMISC) { 1292 CSR_WRITE_4(sc, LGE_MODE1, 1293 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1294 } else { 1295 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1296 } 1297 1298 /* 1299 * Set the capture broadcast bit to capture broadcast frames. 1300 */ 1301 if (ifp->if_flags & IFF_BROADCAST) { 1302 CSR_WRITE_4(sc, LGE_MODE1, 1303 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1304 } else { 1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1306 } 1307 1308 /* Packet padding workaround? */ 1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1310 1311 /* No error frames */ 1312 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1313 1314 /* Receive large frames */ 1315 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1316 1317 /* Workaround: disable RX/TX flow control */ 1318 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1319 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1320 1321 /* Make sure to strip CRC from received frames */ 1322 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1323 1324 /* Turn off magic packet mode */ 1325 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1326 1327 /* Turn off all VLAN stuff */ 1328 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1329 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1330 1331 /* Workarond: FIFO overflow */ 1332 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1333 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1334 1335 /* 1336 * Load the multicast filter. 1337 */ 1338 lge_setmulti(sc); 1339 1340 /* 1341 * Enable hardware checksum validation for all received IPv4 1342 * packets, do not reject packets with bad checksums. 1343 */ 1344 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1345 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1346 LGE_MODE2_RX_ERRCSUM); 1347 1348 /* 1349 * Enable the delivery of PHY interrupts based on 1350 * link/speed/duplex status chalges. 1351 */ 1352 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1353 1354 /* Enable receiver and transmitter. */ 1355 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1357 1358 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1359 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1360 1361 /* 1362 * Enable interrupts. 1363 */ 1364 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1365 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1366 1367 lge_ifmedia_upd_locked(ifp); 1368 1369 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1370 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1371 1372 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1373 1374 return; 1375} 1376 1377/* 1378 * Set media options. 1379 */ 1380static int 1381lge_ifmedia_upd(ifp) 1382 struct ifnet *ifp; 1383{ 1384 struct lge_softc *sc; 1385 1386 sc = ifp->if_softc; 1387 LGE_LOCK(sc); 1388 lge_ifmedia_upd_locked(ifp); 1389 LGE_UNLOCK(sc); 1390 1391 return(0); 1392} 1393 1394static void 1395lge_ifmedia_upd_locked(ifp) 1396 struct ifnet *ifp; 1397{ 1398 struct lge_softc *sc; 1399 struct mii_data *mii; 1400 struct mii_softc *miisc; 1401 1402 sc = ifp->if_softc; 1403 1404 LGE_LOCK_ASSERT(sc); 1405 mii = device_get_softc(sc->lge_miibus); 1406 sc->lge_link = 0; 1407 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1408 PHY_RESET(miisc); 1409 mii_mediachg(mii); 1410} 1411 1412/* 1413 * Report current media status. 1414 */ 1415static void 1416lge_ifmedia_sts(ifp, ifmr) 1417 struct ifnet *ifp; 1418 struct ifmediareq *ifmr; 1419{ 1420 struct lge_softc *sc; 1421 struct mii_data *mii; 1422 1423 sc = ifp->if_softc; 1424 1425 LGE_LOCK(sc); 1426 mii = device_get_softc(sc->lge_miibus); 1427 mii_pollstat(mii); 1428 ifmr->ifm_active = mii->mii_media_active; 1429 ifmr->ifm_status = mii->mii_media_status; 1430 LGE_UNLOCK(sc); 1431 1432 return; 1433} 1434 1435static int 1436lge_ioctl(ifp, command, data) 1437 struct ifnet *ifp; 1438 u_long command; 1439 caddr_t data; 1440{ 1441 struct lge_softc *sc = ifp->if_softc; 1442 struct ifreq *ifr = (struct ifreq *) data; 1443 struct mii_data *mii; 1444 int error = 0; 1445 1446 switch(command) { 1447 case SIOCSIFMTU: 1448 LGE_LOCK(sc); 1449 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1450 error = EINVAL; 1451 else 1452 ifp->if_mtu = ifr->ifr_mtu; 1453 LGE_UNLOCK(sc); 1454 break; 1455 case SIOCSIFFLAGS: 1456 LGE_LOCK(sc); 1457 if (ifp->if_flags & IFF_UP) { 1458 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1459 ifp->if_flags & IFF_PROMISC && 1460 !(sc->lge_if_flags & IFF_PROMISC)) { 1461 CSR_WRITE_4(sc, LGE_MODE1, 1462 LGE_MODE1_SETRST_CTL1| 1463 LGE_MODE1_RX_PROMISC); 1464 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1465 !(ifp->if_flags & IFF_PROMISC) && 1466 sc->lge_if_flags & IFF_PROMISC) { 1467 CSR_WRITE_4(sc, LGE_MODE1, 1468 LGE_MODE1_RX_PROMISC); 1469 } else { 1470 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1471 lge_init_locked(sc); 1472 } 1473 } else { 1474 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1475 lge_stop(sc); 1476 } 1477 sc->lge_if_flags = ifp->if_flags; 1478 LGE_UNLOCK(sc); 1479 error = 0; 1480 break; 1481 case SIOCADDMULTI: 1482 case SIOCDELMULTI: 1483 LGE_LOCK(sc); 1484 lge_setmulti(sc); 1485 LGE_UNLOCK(sc); 1486 error = 0; 1487 break; 1488 case SIOCGIFMEDIA: 1489 case SIOCSIFMEDIA: 1490 mii = device_get_softc(sc->lge_miibus); 1491 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1492 break; 1493 default: 1494 error = ether_ioctl(ifp, command, data); 1495 break; 1496 } 1497 1498 return(error); 1499} 1500 1501static void 1502lge_watchdog(sc) 1503 struct lge_softc *sc; 1504{ 1505 struct ifnet *ifp; 1506 1507 LGE_LOCK_ASSERT(sc); 1508 ifp = sc->lge_ifp; 1509 1510 ifp->if_oerrors++; 1511 if_printf(ifp, "watchdog timeout\n"); 1512 1513 lge_stop(sc); 1514 lge_reset(sc); 1515 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1516 lge_init_locked(sc); 1517 1518 if (ifp->if_snd.ifq_head != NULL) 1519 lge_start_locked(ifp); 1520} 1521 1522/* 1523 * Stop the adapter and free any mbufs allocated to the 1524 * RX and TX lists. 1525 */ 1526static void 1527lge_stop(sc) 1528 struct lge_softc *sc; 1529{ 1530 register int i; 1531 struct ifnet *ifp; 1532 1533 LGE_LOCK_ASSERT(sc); 1534 ifp = sc->lge_ifp; 1535 sc->lge_timer = 0; 1536 callout_stop(&sc->lge_stat_callout); 1537 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1538 1539 /* Disable receiver and transmitter. */ 1540 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1541 sc->lge_link = 0; 1542 1543 /* 1544 * Free data in the RX lists. 1545 */ 1546 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1547 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1548 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1549 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1550 } 1551 } 1552 bzero((char *)&sc->lge_ldata->lge_rx_list, 1553 sizeof(sc->lge_ldata->lge_rx_list)); 1554 1555 /* 1556 * Free the TX list buffers. 1557 */ 1558 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1559 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1560 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1561 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1562 } 1563 } 1564 1565 bzero((char *)&sc->lge_ldata->lge_tx_list, 1566 sizeof(sc->lge_ldata->lge_tx_list)); 1567 1568 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1569 1570 return; 1571} 1572 1573/* 1574 * Stop all chip I/O so that the kernel's probe routines don't 1575 * get confused by errant DMAs when rebooting. 1576 */ 1577static int 1578lge_shutdown(dev) 1579 device_t dev; 1580{ 1581 struct lge_softc *sc; 1582 1583 sc = device_get_softc(dev); 1584 1585 LGE_LOCK(sc); 1586 lge_reset(sc); 1587 lge_stop(sc); 1588 LGE_UNLOCK(sc); 1589 1590 return (0); 1591} 1592