if_lge.c revision 152315
196914Sgrog/*- 296914Sgrog * Copyright (c) 2001 Wind River Systems 396914Sgrog * Copyright (c) 1997, 1998, 1999, 2000, 2001 496914Sgrog * Bill Paul <william.paul@windriver.com>. All rights reserved. 596914Sgrog * 696914Sgrog * Redistribution and use in source and binary forms, with or without 796914Sgrog * modification, are permitted provided that the following conditions 896914Sgrog * are met: 996914Sgrog * 1. Redistributions of source code must retain the above copyright 1096914Sgrog * notice, this list of conditions and the following disclaimer. 1196914Sgrog * 2. Redistributions in binary form must reproduce the above copyright 1296914Sgrog * notice, this list of conditions and the following disclaimer in the 1396914Sgrog * documentation and/or other materials provided with the distribution. 1496914Sgrog * 3. All advertising materials mentioning features or use of this software 1596914Sgrog * must display the following acknowledgement: 1696914Sgrog * This product includes software developed by Bill Paul. 1796914Sgrog * 4. Neither the name of the author nor the names of any co-contributors 1896914Sgrog * may be used to endorse or promote products derived from this software 1996914Sgrog * without specific prior written permission. 2096914Sgrog * 2196914Sgrog * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2296914Sgrog * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2396914Sgrog * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2496914Sgrog * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2596914Sgrog * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2696914Sgrog * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2796914Sgrog * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2896914Sgrog * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2996914Sgrog * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3096914Sgrog * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3196914Sgrog * THE POSSIBILITY OF SUCH DAMAGE. 3296914Sgrog */ 3396914Sgrog 3496914Sgrog#include <sys/cdefs.h> 3596914Sgrog__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 152315 2005-11-11 16:04:59Z ru $"); 3696914Sgrog 3796914Sgrog/* 3896914Sgrog * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 3996914Sgrog * documentation not available, but ask me nicely. 4096914Sgrog * 4196914Sgrog * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 4296914Sgrog * It's a 64-bit PCI part that supports TCP/IP checksum offload, 4396914Sgrog * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 4496914Sgrog * are three supported methods for data transfer between host and 4596914Sgrog * NIC: programmed I/O, traditional scatter/gather DMA and Packet 4696914Sgrog * Propulsion Technology (tm) DMA. The latter mechanism is a form 4796914Sgrog * of double buffer DMA where the packet data is copied to a 4896914Sgrog * pre-allocated DMA buffer who's physical address has been loaded 4996914Sgrog * into a table at device initialization time. The rationale is that 5096914Sgrog * the virtual to physical address translation needed for normal 5196914Sgrog * scatter/gather DMA is more expensive than the data copy needed 5296914Sgrog * for double buffering. This may be true in Windows NT and the like, 5396914Sgrog * but it isn't true for us, at least on the x86 arch. This driver 5496914Sgrog * uses the scatter/gather I/O method for both TX and RX. 5596914Sgrog * 5696914Sgrog * The LXT1001 only supports TCP/IP checksum offload on receive. 5796914Sgrog * Also, the VLAN tagging is done using a 16-entry table which allows 5896914Sgrog * the chip to perform hardware filtering based on VLAN tags. Sadly, 5996914Sgrog * our vlan support doesn't currently play well with this kind of 6096914Sgrog * hardware support. 6196914Sgrog * 6296914Sgrog * Special thanks to: 6396914Sgrog * - Jeff James at Intel, for arranging to have the LXT1001 manual 6496914Sgrog * released (at long last) 6596914Sgrog * - Beny Chen at D-Link, for actually sending it to me 6696914Sgrog * - Brad Short and Keith Alexis at SMC, for sending me sample 6796914Sgrog * SMC9462SX and SMC9462TX adapters for testing 6896914Sgrog * - Paul Saab at Y!, for not killing me (though it remains to be seen 6996914Sgrog * if in fact he did me much of a favor) 7096914Sgrog */ 7196914Sgrog 7296914Sgrog#include <sys/param.h> 7396914Sgrog#include <sys/systm.h> 7496914Sgrog#include <sys/sockio.h> 7596914Sgrog#include <sys/mbuf.h> 7696914Sgrog#include <sys/malloc.h> 7796914Sgrog#include <sys/kernel.h> 7896914Sgrog#include <sys/module.h> 7996914Sgrog#include <sys/socket.h> 8096914Sgrog 8196914Sgrog#include <net/if.h> 8296914Sgrog#include <net/if_arp.h> 8396914Sgrog#include <net/ethernet.h> 8496914Sgrog#include <net/if_dl.h> 8596914Sgrog#include <net/if_media.h> 8696914Sgrog#include <net/if_types.h> 8796914Sgrog 8896914Sgrog#include <net/bpf.h> 8996914Sgrog 9096914Sgrog#include <vm/vm.h> /* for vtophys */ 9196914Sgrog#include <vm/pmap.h> /* for vtophys */ 9296914Sgrog#include <machine/clock.h> /* for DELAY */ 9396914Sgrog#include <machine/bus.h> 9496914Sgrog#include <machine/resource.h> 9596914Sgrog#include <sys/bus.h> 9696914Sgrog#include <sys/rman.h> 9796914Sgrog 9896914Sgrog#include <dev/mii/mii.h> 9996914Sgrog#include <dev/mii/miivar.h> 10096914Sgrog 10196914Sgrog#include <dev/pci/pcireg.h> 10296914Sgrog#include <dev/pci/pcivar.h> 10396914Sgrog 10496914Sgrog#define LGE_USEIOSPACE 10596914Sgrog 10696914Sgrog#include <dev/lge/if_lgereg.h> 10796914Sgrog 10896914Sgrog/* "device miibus" required. See GENERIC if you get errors here. */ 10996914Sgrog#include "miibus_if.h" 11096914Sgrog 11196914Sgrog/* 11296914Sgrog * Various supported device vendors/types and their names. 11396914Sgrog */ 11496914Sgrogstatic struct lge_type lge_devs[] = { 11596914Sgrog { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 11696914Sgrog { 0, 0, NULL } 11796914Sgrog}; 11896914Sgrog 11996914Sgrogstatic int lge_probe(device_t); 12096914Sgrogstatic int lge_attach(device_t); 12196914Sgrogstatic int lge_detach(device_t); 12296914Sgrog 12396914Sgrogstatic int lge_alloc_jumbo_mem(struct lge_softc *); 12496914Sgrogstatic void lge_free_jumbo_mem(struct lge_softc *); 12596914Sgrogstatic void *lge_jalloc(struct lge_softc *); 12696914Sgrogstatic void lge_jfree(void *, void *); 12796914Sgrog 12896914Sgrogstatic int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 12996914Sgrogstatic int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 13096914Sgrogstatic void lge_rxeof(struct lge_softc *, int); 13196914Sgrogstatic void lge_rxeoc(struct lge_softc *); 13296914Sgrogstatic void lge_txeof(struct lge_softc *); 13396914Sgrogstatic void lge_intr(void *); 13496914Sgrogstatic void lge_tick(void *); 13596914Sgrogstatic void lge_start(struct ifnet *); 13696914Sgrogstatic int lge_ioctl(struct ifnet *, u_long, caddr_t); 13796914Sgrogstatic void lge_init(void *); 13896914Sgrogstatic void lge_stop(struct lge_softc *); 13996914Sgrogstatic void lge_watchdog(struct ifnet *); 14096914Sgrogstatic void lge_shutdown(device_t); 14196914Sgrogstatic int lge_ifmedia_upd(struct ifnet *); 14296914Sgrogstatic void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 14396914Sgrog 14496914Sgrogstatic void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 14596914Sgrogstatic void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 14696914Sgrog 14796914Sgrogstatic int lge_miibus_readreg(device_t, int, int); 14896914Sgrogstatic int lge_miibus_writereg(device_t, int, int, int); 14996914Sgrogstatic void lge_miibus_statchg(device_t); 15096914Sgrog 15196914Sgrogstatic void lge_setmulti(struct lge_softc *); 15296914Sgrogstatic void lge_reset(struct lge_softc *); 15396914Sgrogstatic int lge_list_rx_init(struct lge_softc *); 15496914Sgrogstatic int lge_list_tx_init(struct lge_softc *); 15596914Sgrog 15696914Sgrog#ifdef LGE_USEIOSPACE 15796914Sgrog#define LGE_RES SYS_RES_IOPORT 15896914Sgrog#define LGE_RID LGE_PCI_LOIO 15996914Sgrog#else 16096914Sgrog#define LGE_RES SYS_RES_MEMORY 16196914Sgrog#define LGE_RID LGE_PCI_LOMEM 16296914Sgrog#endif 16396914Sgrog 16496914Sgrogstatic device_method_t lge_methods[] = { 16596914Sgrog /* Device interface */ 16696914Sgrog DEVMETHOD(device_probe, lge_probe), 16796914Sgrog DEVMETHOD(device_attach, lge_attach), 16896914Sgrog DEVMETHOD(device_detach, lge_detach), 16996914Sgrog DEVMETHOD(device_shutdown, lge_shutdown), 17096914Sgrog 17196914Sgrog /* bus interface */ 17296914Sgrog DEVMETHOD(bus_print_child, bus_generic_print_child), 17396914Sgrog DEVMETHOD(bus_driver_added, bus_generic_driver_added), 17496914Sgrog 17596914Sgrog /* MII interface */ 17696914Sgrog DEVMETHOD(miibus_readreg, lge_miibus_readreg), 17796914Sgrog DEVMETHOD(miibus_writereg, lge_miibus_writereg), 17896914Sgrog DEVMETHOD(miibus_statchg, lge_miibus_statchg), 17996914Sgrog 18096914Sgrog { 0, 0 } 18196914Sgrog}; 18296914Sgrog 18396914Sgrogstatic driver_t lge_driver = { 18496914Sgrog "lge", 18596914Sgrog lge_methods, 18696914Sgrog sizeof(struct lge_softc) 18796914Sgrog}; 18896914Sgrog 18996914Sgrogstatic devclass_t lge_devclass; 19096914Sgrog 19196914SgrogDRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 19296914SgrogDRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 19396914SgrogMODULE_DEPEND(lge, pci, 1, 1, 1); 19496914SgrogMODULE_DEPEND(lge, ether, 1, 1, 1); 19596914SgrogMODULE_DEPEND(lge, miibus, 1, 1, 1); 19696914Sgrog 19796914Sgrog#define LGE_SETBIT(sc, reg, x) \ 19896914Sgrog CSR_WRITE_4(sc, reg, \ 19996914Sgrog CSR_READ_4(sc, reg) | (x)) 20096914Sgrog 20196914Sgrog#define LGE_CLRBIT(sc, reg, x) \ 20296914Sgrog CSR_WRITE_4(sc, reg, \ 20396914Sgrog CSR_READ_4(sc, reg) & ~(x)) 20496914Sgrog 20596914Sgrog#define SIO_SET(x) \ 20696914Sgrog CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 20796914Sgrog 20896914Sgrog#define SIO_CLR(x) \ 20996914Sgrog CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 21096914Sgrog 21196914Sgrog/* 21296914Sgrog * Read a word of data stored in the EEPROM at address 'addr.' 21396914Sgrog */ 21496914Sgrogstatic void 21596914Sgroglge_eeprom_getword(sc, addr, dest) 21696914Sgrog struct lge_softc *sc; 21796914Sgrog int addr; 21896914Sgrog u_int16_t *dest; 21996914Sgrog{ 22096914Sgrog register int i; 22196914Sgrog u_int32_t val; 22296914Sgrog 22396914Sgrog CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 22496914Sgrog LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 22596914Sgrog 22696914Sgrog for (i = 0; i < LGE_TIMEOUT; i++) 22796914Sgrog if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 22896914Sgrog break; 22996914Sgrog 23096914Sgrog if (i == LGE_TIMEOUT) { 23196914Sgrog if_printf(sc->lge_ifp, "EEPROM read timed out\n"); 23296914Sgrog return; 23396914Sgrog } 23496914Sgrog 23596914Sgrog val = CSR_READ_4(sc, LGE_EEDATA); 23696914Sgrog 23796914Sgrog if (addr & 1) 23896914Sgrog *dest = (val >> 16) & 0xFFFF; 23996914Sgrog else 24096914Sgrog *dest = val & 0xFFFF; 24196914Sgrog 24296914Sgrog return; 24396914Sgrog} 24496914Sgrog 24596914Sgrog/* 24696914Sgrog * Read a sequence of words from the EEPROM. 24796914Sgrog */ 24896914Sgrogstatic void 24996914Sgroglge_read_eeprom(sc, dest, off, cnt, swap) 25096914Sgrog struct lge_softc *sc; 25196914Sgrog caddr_t dest; 25296914Sgrog int off; 25396914Sgrog int cnt; 25496914Sgrog int swap; 25596914Sgrog{ 25696914Sgrog int i; 25796914Sgrog u_int16_t word = 0, *ptr; 25896914Sgrog 25996914Sgrog for (i = 0; i < cnt; i++) { 26096914Sgrog lge_eeprom_getword(sc, off + i, &word); 26196914Sgrog ptr = (u_int16_t *)(dest + (i * 2)); 26296914Sgrog if (swap) 26396914Sgrog *ptr = ntohs(word); 26496914Sgrog else 26596914Sgrog *ptr = word; 26696914Sgrog } 26796914Sgrog 26896914Sgrog return; 26996914Sgrog} 27096914Sgrog 27196914Sgrogstatic int 27296914Sgroglge_miibus_readreg(dev, phy, reg) 27396914Sgrog device_t dev; 27496914Sgrog int phy, reg; 27596914Sgrog{ 27696914Sgrog struct lge_softc *sc; 27796914Sgrog int i; 27896914Sgrog 27996914Sgrog sc = device_get_softc(dev); 28096914Sgrog 28196914Sgrog /* 28296914Sgrog * If we have a non-PCS PHY, pretend that the internal 28396914Sgrog * autoneg stuff at PHY address 0 isn't there so that 28496914Sgrog * the miibus code will find only the GMII PHY. 28596914Sgrog */ 28696914Sgrog if (sc->lge_pcs == 0 && phy == 0) 28796914Sgrog return(0); 28896914Sgrog 28996914Sgrog CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 29096914Sgrog 29196914Sgrog for (i = 0; i < LGE_TIMEOUT; i++) 29296914Sgrog if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 29396914Sgrog break; 29496914Sgrog 29596914Sgrog if (i == LGE_TIMEOUT) { 29696914Sgrog if_printf(sc->lge_ifp, "PHY read timed out\n"); 29796914Sgrog return(0); 29896914Sgrog } 29996914Sgrog 30096914Sgrog return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 30196914Sgrog} 30296914Sgrog 30396914Sgrogstatic int 30496914Sgroglge_miibus_writereg(dev, phy, reg, data) 30596914Sgrog device_t dev; 30696914Sgrog int phy, reg, data; 30796914Sgrog{ 30896914Sgrog struct lge_softc *sc; 30996914Sgrog int i; 31096914Sgrog 31196914Sgrog sc = device_get_softc(dev); 31296914Sgrog 31396914Sgrog CSR_WRITE_4(sc, LGE_GMIICTL, 31496914Sgrog (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 31596914Sgrog 31696914Sgrog for (i = 0; i < LGE_TIMEOUT; i++) 31796914Sgrog if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 31896914Sgrog break; 31996914Sgrog 32096914Sgrog if (i == LGE_TIMEOUT) { 32196914Sgrog if_printf(sc->lge_ifp, "PHY write timed out\n"); 32296914Sgrog return(0); 32396914Sgrog } 32496914Sgrog 32596914Sgrog return(0); 32696914Sgrog} 32796914Sgrog 32896914Sgrogstatic void 32996914Sgroglge_miibus_statchg(dev) 33096914Sgrog device_t dev; 33196914Sgrog{ 33296914Sgrog struct lge_softc *sc; 33396914Sgrog struct mii_data *mii; 33496914Sgrog 33596914Sgrog sc = device_get_softc(dev); 33696914Sgrog mii = device_get_softc(sc->lge_miibus); 33796914Sgrog 33896914Sgrog LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 33996914Sgrog switch (IFM_SUBTYPE(mii->mii_media_active)) { 34096914Sgrog case IFM_1000_T: 34196914Sgrog case IFM_1000_SX: 34296914Sgrog LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 34396914Sgrog break; 34496914Sgrog case IFM_100_TX: 34596914Sgrog LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 34696914Sgrog break; 34796914Sgrog case IFM_10_T: 34896914Sgrog LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 34996914Sgrog break; 35096914Sgrog default: 35196914Sgrog /* 35296914Sgrog * Choose something, even if it's wrong. Clearing 35396914Sgrog * all the bits will hose autoneg on the internal 35496914Sgrog * PHY. 35596914Sgrog */ 35696914Sgrog LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 35796914Sgrog break; 35896914Sgrog } 35996914Sgrog 36096914Sgrog if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 36196914Sgrog LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 36296914Sgrog } else { 36396914Sgrog LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 36496914Sgrog } 36596914Sgrog 36696914Sgrog return; 36796914Sgrog} 36896914Sgrog 36996914Sgrogstatic void 37096914Sgroglge_setmulti(sc) 37196914Sgrog struct lge_softc *sc; 37296914Sgrog{ 37396914Sgrog struct ifnet *ifp; 37496914Sgrog struct ifmultiaddr *ifma; 37596914Sgrog u_int32_t h = 0, hashes[2] = { 0, 0 }; 37696914Sgrog 37796914Sgrog ifp = sc->lge_ifp; 37896914Sgrog 37996914Sgrog /* Make sure multicast hash table is enabled. */ 38096914Sgrog CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 38196914Sgrog 38296914Sgrog if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 38396914Sgrog CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 38496914Sgrog CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 38596914Sgrog return; 38696914Sgrog } 38796914Sgrog 38896914Sgrog /* first, zot all the existing hash bits */ 38996914Sgrog CSR_WRITE_4(sc, LGE_MAR0, 0); 39096914Sgrog CSR_WRITE_4(sc, LGE_MAR1, 0); 39196914Sgrog 39296914Sgrog /* now program new ones */ 39396914Sgrog IF_ADDR_LOCK(ifp); 39496914Sgrog TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 39596914Sgrog if (ifma->ifma_addr->sa_family != AF_LINK) 39696914Sgrog continue; 39796914Sgrog h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 39896914Sgrog ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 39996914Sgrog if (h < 32) 40096914Sgrog hashes[0] |= (1 << h); 40196914Sgrog else 40296914Sgrog hashes[1] |= (1 << (h - 32)); 40396914Sgrog } 40496914Sgrog IF_ADDR_UNLOCK(ifp); 40596914Sgrog 40696914Sgrog CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 40796914Sgrog CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 40896914Sgrog 40996914Sgrog return; 41096914Sgrog} 41196914Sgrog 41296914Sgrogstatic void 41396914Sgroglge_reset(sc) 41496914Sgrog struct lge_softc *sc; 41596914Sgrog{ 41696914Sgrog register int i; 41796914Sgrog 41896914Sgrog LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 41996914Sgrog 42096914Sgrog for (i = 0; i < LGE_TIMEOUT; i++) { 42196914Sgrog if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 42296914Sgrog break; 42396914Sgrog } 42496914Sgrog 42596914Sgrog if (i == LGE_TIMEOUT) 42696914Sgrog if_printf(sc->lge_ifp, "reset never completed\n"); 42796914Sgrog 42896914Sgrog /* Wait a little while for the chip to get its brains in order. */ 42996914Sgrog DELAY(1000); 43096914Sgrog 43196914Sgrog return; 43296914Sgrog} 43396914Sgrog 43496914Sgrog/* 43596914Sgrog * Probe for a Level 1 chip. Check the PCI vendor and device 43696914Sgrog * IDs against our list and return a device name if we find a match. 43796914Sgrog */ 43896914Sgrogstatic int 43996914Sgroglge_probe(dev) 44096914Sgrog device_t dev; 44196914Sgrog{ 44296914Sgrog struct lge_type *t; 44396914Sgrog 44496914Sgrog t = lge_devs; 44596914Sgrog 44696914Sgrog while(t->lge_name != NULL) { 44796914Sgrog if ((pci_get_vendor(dev) == t->lge_vid) && 44896914Sgrog (pci_get_device(dev) == t->lge_did)) { 449 device_set_desc(dev, t->lge_name); 450 return(BUS_PROBE_DEFAULT); 451 } 452 t++; 453 } 454 455 return(ENXIO); 456} 457 458/* 459 * Attach the interface. Allocate softc structures, do ifmedia 460 * setup and ethernet/BPF attach. 461 */ 462static int 463lge_attach(dev) 464 device_t dev; 465{ 466 int s; 467 u_char eaddr[ETHER_ADDR_LEN]; 468 struct lge_softc *sc; 469 struct ifnet *ifp = NULL; 470 int error = 0, rid; 471 472 s = splimp(); 473 474 sc = device_get_softc(dev); 475 476 /* 477 * Map control/status registers. 478 */ 479 pci_enable_busmaster(dev); 480 481 rid = LGE_RID; 482 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 483 484 if (sc->lge_res == NULL) { 485 device_printf(dev, "couldn't map ports/memory\n"); 486 error = ENXIO; 487 goto fail; 488 } 489 490 sc->lge_btag = rman_get_bustag(sc->lge_res); 491 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 492 493 /* Allocate interrupt */ 494 rid = 0; 495 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 496 RF_SHAREABLE | RF_ACTIVE); 497 498 if (sc->lge_irq == NULL) { 499 device_printf(dev, "couldn't map interrupt\n"); 500 error = ENXIO; 501 goto fail; 502 } 503 504 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 505 lge_intr, sc, &sc->lge_intrhand); 506 507 if (error) { 508 device_printf(dev, "couldn't set up irq\n"); 509 goto fail; 510 } 511 512 /* Reset the adapter. */ 513 lge_reset(sc); 514 515 /* 516 * Get station address from the EEPROM. 517 */ 518 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 519 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 520 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 521 522 callout_handle_init(&sc->lge_stat_ch); 523 524 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 525 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 526 527 if (sc->lge_ldata == NULL) { 528 device_printf(dev, "no memory for list buffers!\n"); 529 error = ENXIO; 530 goto fail; 531 } 532 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 533 534 /* Try to allocate memory for jumbo buffers. */ 535 if (lge_alloc_jumbo_mem(sc)) { 536 device_printf(dev, "jumbo buffer allocation failed\n"); 537 error = ENXIO; 538 goto fail; 539 } 540 541 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 542 if (ifp == NULL) { 543 device_printf(dev, "can not if_alloc()\n"); 544 lge_free_jumbo_mem(sc); 545 error = ENOSPC; 546 goto fail; 547 } 548 ifp->if_softc = sc; 549 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 550 ifp->if_mtu = ETHERMTU; 551 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 552 IFF_NEEDSGIANT; 553 ifp->if_ioctl = lge_ioctl; 554 ifp->if_start = lge_start; 555 ifp->if_watchdog = lge_watchdog; 556 ifp->if_init = lge_init; 557 ifp->if_baudrate = 1000000000; 558 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 559 ifp->if_capabilities = IFCAP_RXCSUM; 560 ifp->if_capenable = ifp->if_capabilities; 561 562 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 563 sc->lge_pcs = 1; 564 else 565 sc->lge_pcs = 0; 566 567 /* 568 * Do MII setup. 569 */ 570 if (mii_phy_probe(dev, &sc->lge_miibus, 571 lge_ifmedia_upd, lge_ifmedia_sts)) { 572 device_printf(dev, "MII without any PHY!\n"); 573 lge_free_jumbo_mem(sc); 574 error = ENXIO; 575 goto fail; 576 } 577 578 /* 579 * Call MI attach routine. 580 */ 581 ether_ifattach(ifp, eaddr); 582 return (0); 583 584fail: 585 if (sc->lge_ldata) 586 contigfree(sc->lge_ldata, 587 sizeof(struct lge_list_data), M_DEVBUF); 588 if (ifp) 589 if_free(ifp); 590 if (sc->lge_intrhand) 591 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 592 if (sc->lge_irq) 593 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 594 if (sc->lge_res) 595 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 596 splx(s); 597 return(error); 598} 599 600static int 601lge_detach(dev) 602 device_t dev; 603{ 604 struct lge_softc *sc; 605 struct ifnet *ifp; 606 int s; 607 608 s = splimp(); 609 610 sc = device_get_softc(dev); 611 ifp = sc->lge_ifp; 612 613 lge_reset(sc); 614 lge_stop(sc); 615 ether_ifdetach(ifp); 616 617 bus_generic_detach(dev); 618 device_delete_child(dev, sc->lge_miibus); 619 620 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 621 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 622 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 623 624 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 625 if_free(ifp); 626 lge_free_jumbo_mem(sc); 627 628 splx(s); 629 630 return(0); 631} 632 633/* 634 * Initialize the transmit descriptors. 635 */ 636static int 637lge_list_tx_init(sc) 638 struct lge_softc *sc; 639{ 640 struct lge_list_data *ld; 641 struct lge_ring_data *cd; 642 int i; 643 644 cd = &sc->lge_cdata; 645 ld = sc->lge_ldata; 646 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 647 ld->lge_tx_list[i].lge_mbuf = NULL; 648 ld->lge_tx_list[i].lge_ctl = 0; 649 } 650 651 cd->lge_tx_prod = cd->lge_tx_cons = 0; 652 653 return(0); 654} 655 656 657/* 658 * Initialize the RX descriptors and allocate mbufs for them. Note that 659 * we arralge the descriptors in a closed ring, so that the last descriptor 660 * points back to the first. 661 */ 662static int 663lge_list_rx_init(sc) 664 struct lge_softc *sc; 665{ 666 struct lge_list_data *ld; 667 struct lge_ring_data *cd; 668 int i; 669 670 ld = sc->lge_ldata; 671 cd = &sc->lge_cdata; 672 673 cd->lge_rx_prod = cd->lge_rx_cons = 0; 674 675 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 676 677 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 678 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 679 break; 680 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 681 return(ENOBUFS); 682 } 683 684 /* Clear possible 'rx command queue empty' interrupt. */ 685 CSR_READ_4(sc, LGE_ISR); 686 687 return(0); 688} 689 690/* 691 * Initialize an RX descriptor and attach an MBUF cluster. 692 */ 693static int 694lge_newbuf(sc, c, m) 695 struct lge_softc *sc; 696 struct lge_rx_desc *c; 697 struct mbuf *m; 698{ 699 struct mbuf *m_new = NULL; 700 caddr_t *buf = NULL; 701 702 if (m == NULL) { 703 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 704 if (m_new == NULL) { 705 if_printf(sc->lge_ifp, "no memory for rx list " 706 "-- packet dropped!\n"); 707 return(ENOBUFS); 708 } 709 710 /* Allocate the jumbo buffer */ 711 buf = lge_jalloc(sc); 712 if (buf == NULL) { 713#ifdef LGE_VERBOSE 714 if_printf(sc->lge_ifp, "jumbo allocation failed " 715 "-- packet dropped!\n"); 716#endif 717 m_freem(m_new); 718 return(ENOBUFS); 719 } 720 /* Attach the buffer to the mbuf */ 721 m_new->m_data = (void *)buf; 722 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 723 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 724 (struct lge_softc *)sc, 0, EXT_NET_DRV); 725 } else { 726 m_new = m; 727 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 728 m_new->m_data = m_new->m_ext.ext_buf; 729 } 730 731 /* 732 * Adjust alignment so packet payload begins on a 733 * longword boundary. Mandatory for Alpha, useful on 734 * x86 too. 735 */ 736 m_adj(m_new, ETHER_ALIGN); 737 738 c->lge_mbuf = m_new; 739 c->lge_fragptr_hi = 0; 740 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 741 c->lge_fraglen = m_new->m_len; 742 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 743 c->lge_sts = 0; 744 745 /* 746 * Put this buffer in the RX command FIFO. To do this, 747 * we just write the physical address of the descriptor 748 * into the RX descriptor address registers. Note that 749 * there are two registers, one high DWORD and one low 750 * DWORD, which lets us specify a 64-bit address if 751 * desired. We only use a 32-bit address for now. 752 * Writing to the low DWORD register is what actually 753 * causes the command to be issued, so we do that 754 * last. 755 */ 756 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 757 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 758 759 return(0); 760} 761 762static int 763lge_alloc_jumbo_mem(sc) 764 struct lge_softc *sc; 765{ 766 caddr_t ptr; 767 register int i; 768 struct lge_jpool_entry *entry; 769 770 /* Grab a big chunk o' storage. */ 771 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 772 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 773 774 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 775 if_printf(sc->lge_ifp, "no memory for jumbo buffers!\n"); 776 return(ENOBUFS); 777 } 778 779 SLIST_INIT(&sc->lge_jfree_listhead); 780 SLIST_INIT(&sc->lge_jinuse_listhead); 781 782 /* 783 * Now divide it up into 9K pieces and save the addresses 784 * in an array. 785 */ 786 ptr = sc->lge_cdata.lge_jumbo_buf; 787 for (i = 0; i < LGE_JSLOTS; i++) { 788 sc->lge_cdata.lge_jslots[i] = ptr; 789 ptr += LGE_JLEN; 790 entry = malloc(sizeof(struct lge_jpool_entry), 791 M_DEVBUF, M_NOWAIT); 792 if (entry == NULL) { 793 if_printf(sc->lge_ifp, "no memory for jumbo " 794 "buffer queue!\n"); 795 return(ENOBUFS); 796 } 797 entry->slot = i; 798 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 799 entry, jpool_entries); 800 } 801 802 return(0); 803} 804 805static void 806lge_free_jumbo_mem(sc) 807 struct lge_softc *sc; 808{ 809 int i; 810 struct lge_jpool_entry *entry; 811 812 for (i = 0; i < LGE_JSLOTS; i++) { 813 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 814 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 815 free(entry, M_DEVBUF); 816 } 817 818 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 819 820 return; 821} 822 823/* 824 * Allocate a jumbo buffer. 825 */ 826static void * 827lge_jalloc(sc) 828 struct lge_softc *sc; 829{ 830 struct lge_jpool_entry *entry; 831 832 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 833 834 if (entry == NULL) { 835#ifdef LGE_VERBOSE 836 if_printf(sc->lge_ifp, "no free jumbo buffers\n"); 837#endif 838 return(NULL); 839 } 840 841 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 842 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 843 return(sc->lge_cdata.lge_jslots[entry->slot]); 844} 845 846/* 847 * Release a jumbo buffer. 848 */ 849static void 850lge_jfree(buf, args) 851 void *buf; 852 void *args; 853{ 854 struct lge_softc *sc; 855 int i; 856 struct lge_jpool_entry *entry; 857 858 /* Extract the softc struct pointer. */ 859 sc = args; 860 861 if (sc == NULL) 862 panic("lge_jfree: can't find softc pointer!"); 863 864 /* calculate the slot this buffer belongs to */ 865 i = ((vm_offset_t)buf 866 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 867 868 if ((i < 0) || (i >= LGE_JSLOTS)) 869 panic("lge_jfree: asked to free buffer that we don't manage!"); 870 871 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 872 if (entry == NULL) 873 panic("lge_jfree: buffer not in use!"); 874 entry->slot = i; 875 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 876 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 877 878 return; 879} 880 881/* 882 * A frame has been uploaded: pass the resulting mbuf chain up to 883 * the higher level protocols. 884 */ 885static void 886lge_rxeof(sc, cnt) 887 struct lge_softc *sc; 888 int cnt; 889{ 890 struct mbuf *m; 891 struct ifnet *ifp; 892 struct lge_rx_desc *cur_rx; 893 int c, i, total_len = 0; 894 u_int32_t rxsts, rxctl; 895 896 ifp = sc->lge_ifp; 897 898 /* Find out how many frames were processed. */ 899 c = cnt; 900 i = sc->lge_cdata.lge_rx_cons; 901 902 /* Suck them in. */ 903 while(c) { 904 struct mbuf *m0 = NULL; 905 906 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 907 rxctl = cur_rx->lge_ctl; 908 rxsts = cur_rx->lge_sts; 909 m = cur_rx->lge_mbuf; 910 cur_rx->lge_mbuf = NULL; 911 total_len = LGE_RXBYTES(cur_rx); 912 LGE_INC(i, LGE_RX_LIST_CNT); 913 c--; 914 915 /* 916 * If an error occurs, update stats, clear the 917 * status word and leave the mbuf cluster in place: 918 * it should simply get re-used next time this descriptor 919 * comes up in the ring. 920 */ 921 if (rxctl & LGE_RXCTL_ERRMASK) { 922 ifp->if_ierrors++; 923 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 924 continue; 925 } 926 927 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 928 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 929 ifp, NULL); 930 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 931 if (m0 == NULL) { 932 if_printf(ifp, "no receive buffers " 933 "available -- packet dropped!\n"); 934 ifp->if_ierrors++; 935 continue; 936 } 937 m = m0; 938 } else { 939 m->m_pkthdr.rcvif = ifp; 940 m->m_pkthdr.len = m->m_len = total_len; 941 } 942 943 ifp->if_ipackets++; 944 945 /* Do IP checksum checking. */ 946 if (rxsts & LGE_RXSTS_ISIP) 947 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 948 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 949 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 950 if ((rxsts & LGE_RXSTS_ISTCP && 951 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 952 (rxsts & LGE_RXSTS_ISUDP && 953 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 954 m->m_pkthdr.csum_flags |= 955 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 956 m->m_pkthdr.csum_data = 0xffff; 957 } 958 959 (*ifp->if_input)(ifp, m); 960 } 961 962 sc->lge_cdata.lge_rx_cons = i; 963 964 return; 965} 966 967static void 968lge_rxeoc(sc) 969 struct lge_softc *sc; 970{ 971 struct ifnet *ifp; 972 973 ifp = sc->lge_ifp; 974 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 975 lge_init(sc); 976 return; 977} 978 979/* 980 * A frame was downloaded to the chip. It's safe for us to clean up 981 * the list buffers. 982 */ 983 984static void 985lge_txeof(sc) 986 struct lge_softc *sc; 987{ 988 struct lge_tx_desc *cur_tx = NULL; 989 struct ifnet *ifp; 990 u_int32_t idx, txdone; 991 992 ifp = sc->lge_ifp; 993 994 /* Clear the timeout timer. */ 995 ifp->if_timer = 0; 996 997 /* 998 * Go through our tx list and free mbufs for those 999 * frames that have been transmitted. 1000 */ 1001 idx = sc->lge_cdata.lge_tx_cons; 1002 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1003 1004 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1005 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1006 1007 ifp->if_opackets++; 1008 if (cur_tx->lge_mbuf != NULL) { 1009 m_freem(cur_tx->lge_mbuf); 1010 cur_tx->lge_mbuf = NULL; 1011 } 1012 cur_tx->lge_ctl = 0; 1013 1014 txdone--; 1015 LGE_INC(idx, LGE_TX_LIST_CNT); 1016 ifp->if_timer = 0; 1017 } 1018 1019 sc->lge_cdata.lge_tx_cons = idx; 1020 1021 if (cur_tx != NULL) 1022 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1023 1024 return; 1025} 1026 1027static void 1028lge_tick(xsc) 1029 void *xsc; 1030{ 1031 struct lge_softc *sc; 1032 struct mii_data *mii; 1033 struct ifnet *ifp; 1034 int s; 1035 1036 s = splimp(); 1037 1038 sc = xsc; 1039 ifp = sc->lge_ifp; 1040 1041 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1042 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1043 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1044 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1045 1046 if (!sc->lge_link) { 1047 mii = device_get_softc(sc->lge_miibus); 1048 mii_tick(mii); 1049 if (mii->mii_media_status & IFM_ACTIVE && 1050 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1051 sc->lge_link++; 1052 if (bootverbose && 1053 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1054 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1055 if_printf(ifp, "gigabit link up\n"); 1056 if (ifp->if_snd.ifq_head != NULL) 1057 lge_start(ifp); 1058 } 1059 } 1060 1061 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1062 1063 splx(s); 1064 1065 return; 1066} 1067 1068static void 1069lge_intr(arg) 1070 void *arg; 1071{ 1072 struct lge_softc *sc; 1073 struct ifnet *ifp; 1074 u_int32_t status; 1075 1076 sc = arg; 1077 ifp = sc->lge_ifp; 1078 1079 /* Supress unwanted interrupts */ 1080 if (!(ifp->if_flags & IFF_UP)) { 1081 lge_stop(sc); 1082 return; 1083 } 1084 1085 for (;;) { 1086 /* 1087 * Reading the ISR register clears all interrupts, and 1088 * clears the 'interrupts enabled' bit in the IMR 1089 * register. 1090 */ 1091 status = CSR_READ_4(sc, LGE_ISR); 1092 1093 if ((status & LGE_INTRS) == 0) 1094 break; 1095 1096 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1097 lge_txeof(sc); 1098 1099 if (status & LGE_ISR_RXDMA_DONE) 1100 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1101 1102 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1103 lge_rxeoc(sc); 1104 1105 if (status & LGE_ISR_PHY_INTR) { 1106 sc->lge_link = 0; 1107 untimeout(lge_tick, sc, sc->lge_stat_ch); 1108 lge_tick(sc); 1109 } 1110 } 1111 1112 /* Re-enable interrupts. */ 1113 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1114 1115 if (ifp->if_snd.ifq_head != NULL) 1116 lge_start(ifp); 1117 1118 return; 1119} 1120 1121/* 1122 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1123 * pointers to the fragment pointers. 1124 */ 1125static int 1126lge_encap(sc, m_head, txidx) 1127 struct lge_softc *sc; 1128 struct mbuf *m_head; 1129 u_int32_t *txidx; 1130{ 1131 struct lge_frag *f = NULL; 1132 struct lge_tx_desc *cur_tx; 1133 struct mbuf *m; 1134 int frag = 0, tot_len = 0; 1135 1136 /* 1137 * Start packing the mbufs in this chain into 1138 * the fragment pointers. Stop when we run out 1139 * of fragments or hit the end of the mbuf chain. 1140 */ 1141 m = m_head; 1142 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1143 frag = 0; 1144 1145 for (m = m_head; m != NULL; m = m->m_next) { 1146 if (m->m_len != 0) { 1147 tot_len += m->m_len; 1148 f = &cur_tx->lge_frags[frag]; 1149 f->lge_fraglen = m->m_len; 1150 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1151 f->lge_fragptr_hi = 0; 1152 frag++; 1153 } 1154 } 1155 1156 if (m != NULL) 1157 return(ENOBUFS); 1158 1159 cur_tx->lge_mbuf = m_head; 1160 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1161 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1162 1163 /* Queue for transmit */ 1164 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1165 1166 return(0); 1167} 1168 1169/* 1170 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1171 * to the mbuf data regions directly in the transmit lists. We also save a 1172 * copy of the pointers since the transmit list fragment pointers are 1173 * physical addresses. 1174 */ 1175 1176static void 1177lge_start(ifp) 1178 struct ifnet *ifp; 1179{ 1180 struct lge_softc *sc; 1181 struct mbuf *m_head = NULL; 1182 u_int32_t idx; 1183 1184 sc = ifp->if_softc; 1185 1186 if (!sc->lge_link) 1187 return; 1188 1189 idx = sc->lge_cdata.lge_tx_prod; 1190 1191 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1192 return; 1193 1194 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1195 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1196 break; 1197 1198 IF_DEQUEUE(&ifp->if_snd, m_head); 1199 if (m_head == NULL) 1200 break; 1201 1202 if (lge_encap(sc, m_head, &idx)) { 1203 IF_PREPEND(&ifp->if_snd, m_head); 1204 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1205 break; 1206 } 1207 1208 /* 1209 * If there's a BPF listener, bounce a copy of this frame 1210 * to him. 1211 */ 1212 BPF_MTAP(ifp, m_head); 1213 } 1214 1215 sc->lge_cdata.lge_tx_prod = idx; 1216 1217 /* 1218 * Set a timeout in case the chip goes out to lunch. 1219 */ 1220 ifp->if_timer = 5; 1221 1222 return; 1223} 1224 1225static void 1226lge_init(xsc) 1227 void *xsc; 1228{ 1229 struct lge_softc *sc = xsc; 1230 struct ifnet *ifp = sc->lge_ifp; 1231 struct mii_data *mii; 1232 int s; 1233 1234 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1235 return; 1236 1237 s = splimp(); 1238 1239 /* 1240 * Cancel pending I/O and free all RX/TX buffers. 1241 */ 1242 lge_stop(sc); 1243 lge_reset(sc); 1244 1245 mii = device_get_softc(sc->lge_miibus); 1246 1247 /* Set MAC address */ 1248 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0])); 1249 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4])); 1250 1251 /* Init circular RX list. */ 1252 if (lge_list_rx_init(sc) == ENOBUFS) { 1253 if_printf(ifp, "initialization failed: no " 1254 "memory for rx buffers\n"); 1255 lge_stop(sc); 1256 (void)splx(s); 1257 return; 1258 } 1259 1260 /* 1261 * Init tx descriptors. 1262 */ 1263 lge_list_tx_init(sc); 1264 1265 /* Set initial value for MODE1 register. */ 1266 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1267 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1268 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1269 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1270 1271 /* If we want promiscuous mode, set the allframes bit. */ 1272 if (ifp->if_flags & IFF_PROMISC) { 1273 CSR_WRITE_4(sc, LGE_MODE1, 1274 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1275 } else { 1276 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1277 } 1278 1279 /* 1280 * Set the capture broadcast bit to capture broadcast frames. 1281 */ 1282 if (ifp->if_flags & IFF_BROADCAST) { 1283 CSR_WRITE_4(sc, LGE_MODE1, 1284 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1285 } else { 1286 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1287 } 1288 1289 /* Packet padding workaround? */ 1290 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1291 1292 /* No error frames */ 1293 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1294 1295 /* Receive large frames */ 1296 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1297 1298 /* Workaround: disable RX/TX flow control */ 1299 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1300 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1301 1302 /* Make sure to strip CRC from received frames */ 1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1304 1305 /* Turn off magic packet mode */ 1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1307 1308 /* Turn off all VLAN stuff */ 1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1310 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1311 1312 /* Workarond: FIFO overflow */ 1313 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1314 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1315 1316 /* 1317 * Load the multicast filter. 1318 */ 1319 lge_setmulti(sc); 1320 1321 /* 1322 * Enable hardware checksum validation for all received IPv4 1323 * packets, do not reject packets with bad checksums. 1324 */ 1325 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1326 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1327 LGE_MODE2_RX_ERRCSUM); 1328 1329 /* 1330 * Enable the delivery of PHY interrupts based on 1331 * link/speed/duplex status chalges. 1332 */ 1333 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1334 1335 /* Enable receiver and transmitter. */ 1336 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1337 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1338 1339 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1340 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1341 1342 /* 1343 * Enable interrupts. 1344 */ 1345 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1346 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1347 1348 lge_ifmedia_upd(ifp); 1349 1350 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1352 1353 (void)splx(s); 1354 1355 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1356 1357 return; 1358} 1359 1360/* 1361 * Set media options. 1362 */ 1363static int 1364lge_ifmedia_upd(ifp) 1365 struct ifnet *ifp; 1366{ 1367 struct lge_softc *sc; 1368 struct mii_data *mii; 1369 1370 sc = ifp->if_softc; 1371 1372 mii = device_get_softc(sc->lge_miibus); 1373 sc->lge_link = 0; 1374 if (mii->mii_instance) { 1375 struct mii_softc *miisc; 1376 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1377 miisc = LIST_NEXT(miisc, mii_list)) 1378 mii_phy_reset(miisc); 1379 } 1380 mii_mediachg(mii); 1381 1382 return(0); 1383} 1384 1385/* 1386 * Report current media status. 1387 */ 1388static void 1389lge_ifmedia_sts(ifp, ifmr) 1390 struct ifnet *ifp; 1391 struct ifmediareq *ifmr; 1392{ 1393 struct lge_softc *sc; 1394 struct mii_data *mii; 1395 1396 sc = ifp->if_softc; 1397 1398 mii = device_get_softc(sc->lge_miibus); 1399 mii_pollstat(mii); 1400 ifmr->ifm_active = mii->mii_media_active; 1401 ifmr->ifm_status = mii->mii_media_status; 1402 1403 return; 1404} 1405 1406static int 1407lge_ioctl(ifp, command, data) 1408 struct ifnet *ifp; 1409 u_long command; 1410 caddr_t data; 1411{ 1412 struct lge_softc *sc = ifp->if_softc; 1413 struct ifreq *ifr = (struct ifreq *) data; 1414 struct mii_data *mii; 1415 int s, error = 0; 1416 1417 s = splimp(); 1418 1419 switch(command) { 1420 case SIOCSIFMTU: 1421 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1422 error = EINVAL; 1423 else 1424 ifp->if_mtu = ifr->ifr_mtu; 1425 break; 1426 case SIOCSIFFLAGS: 1427 if (ifp->if_flags & IFF_UP) { 1428 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1429 ifp->if_flags & IFF_PROMISC && 1430 !(sc->lge_if_flags & IFF_PROMISC)) { 1431 CSR_WRITE_4(sc, LGE_MODE1, 1432 LGE_MODE1_SETRST_CTL1| 1433 LGE_MODE1_RX_PROMISC); 1434 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1435 !(ifp->if_flags & IFF_PROMISC) && 1436 sc->lge_if_flags & IFF_PROMISC) { 1437 CSR_WRITE_4(sc, LGE_MODE1, 1438 LGE_MODE1_RX_PROMISC); 1439 } else { 1440 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1441 lge_init(sc); 1442 } 1443 } else { 1444 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1445 lge_stop(sc); 1446 } 1447 sc->lge_if_flags = ifp->if_flags; 1448 error = 0; 1449 break; 1450 case SIOCADDMULTI: 1451 case SIOCDELMULTI: 1452 lge_setmulti(sc); 1453 error = 0; 1454 break; 1455 case SIOCGIFMEDIA: 1456 case SIOCSIFMEDIA: 1457 mii = device_get_softc(sc->lge_miibus); 1458 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1459 break; 1460 default: 1461 error = ether_ioctl(ifp, command, data); 1462 break; 1463 } 1464 1465 (void)splx(s); 1466 1467 return(error); 1468} 1469 1470static void 1471lge_watchdog(ifp) 1472 struct ifnet *ifp; 1473{ 1474 struct lge_softc *sc; 1475 1476 sc = ifp->if_softc; 1477 1478 ifp->if_oerrors++; 1479 if_printf(ifp, "watchdog timeout\n"); 1480 1481 lge_stop(sc); 1482 lge_reset(sc); 1483 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1484 lge_init(sc); 1485 1486 if (ifp->if_snd.ifq_head != NULL) 1487 lge_start(ifp); 1488 1489 return; 1490} 1491 1492/* 1493 * Stop the adapter and free any mbufs allocated to the 1494 * RX and TX lists. 1495 */ 1496static void 1497lge_stop(sc) 1498 struct lge_softc *sc; 1499{ 1500 register int i; 1501 struct ifnet *ifp; 1502 1503 ifp = sc->lge_ifp; 1504 ifp->if_timer = 0; 1505 untimeout(lge_tick, sc, sc->lge_stat_ch); 1506 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1507 1508 /* Disable receiver and transmitter. */ 1509 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1510 sc->lge_link = 0; 1511 1512 /* 1513 * Free data in the RX lists. 1514 */ 1515 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1516 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1517 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1518 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1519 } 1520 } 1521 bzero((char *)&sc->lge_ldata->lge_rx_list, 1522 sizeof(sc->lge_ldata->lge_rx_list)); 1523 1524 /* 1525 * Free the TX list buffers. 1526 */ 1527 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1528 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1529 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1530 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1531 } 1532 } 1533 1534 bzero((char *)&sc->lge_ldata->lge_tx_list, 1535 sizeof(sc->lge_ldata->lge_tx_list)); 1536 1537 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1538 1539 return; 1540} 1541 1542/* 1543 * Stop all chip I/O so that the kernel's probe routines don't 1544 * get confused by errant DMAs when rebooting. 1545 */ 1546static void 1547lge_shutdown(dev) 1548 device_t dev; 1549{ 1550 struct lge_softc *sc; 1551 1552 sc = device_get_softc(dev); 1553 1554 lge_reset(sc); 1555 lge_stop(sc); 1556 1557 return; 1558} 1559