if_lge.c revision 131255
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 131255 2004-06-28 20:26:21Z imp $"); 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/module.h> 79#include <sys/socket.h> 80 81#include <net/if.h> 82#include <net/if_arp.h> 83#include <net/ethernet.h> 84#include <net/if_dl.h> 85#include <net/if_media.h> 86 87#include <net/bpf.h> 88 89#include <vm/vm.h> /* for vtophys */ 90#include <vm/pmap.h> /* for vtophys */ 91#include <machine/clock.h> /* for DELAY */ 92#include <machine/bus_pio.h> 93#include <machine/bus_memio.h> 94#include <machine/bus.h> 95#include <machine/resource.h> 96#include <sys/bus.h> 97#include <sys/rman.h> 98 99#include <dev/mii/mii.h> 100#include <dev/mii/miivar.h> 101 102#include <dev/pci/pcireg.h> 103#include <dev/pci/pcivar.h> 104 105#define LGE_USEIOSPACE 106 107#include <dev/lge/if_lgereg.h> 108 109/* "controller miibus0" required. See GENERIC if you get errors here. */ 110#include "miibus_if.h" 111 112/* 113 * Various supported device vendors/types and their names. 114 */ 115static struct lge_type lge_devs[] = { 116 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 117 { 0, 0, NULL } 118}; 119 120static int lge_probe(device_t); 121static int lge_attach(device_t); 122static int lge_detach(device_t); 123 124static int lge_alloc_jumbo_mem(struct lge_softc *); 125static void lge_free_jumbo_mem(struct lge_softc *); 126static void *lge_jalloc(struct lge_softc *); 127static void lge_jfree(void *, void *); 128 129static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 130static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 131static void lge_rxeof(struct lge_softc *, int); 132static void lge_rxeoc(struct lge_softc *); 133static void lge_txeof(struct lge_softc *); 134static void lge_intr(void *); 135static void lge_tick(void *); 136static void lge_start(struct ifnet *); 137static int lge_ioctl(struct ifnet *, u_long, caddr_t); 138static void lge_init(void *); 139static void lge_stop(struct lge_softc *); 140static void lge_watchdog(struct ifnet *); 141static void lge_shutdown(device_t); 142static int lge_ifmedia_upd(struct ifnet *); 143static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 144 145static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 146static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 147 148static int lge_miibus_readreg(device_t, int, int); 149static int lge_miibus_writereg(device_t, int, int, int); 150static void lge_miibus_statchg(device_t); 151 152static void lge_setmulti(struct lge_softc *); 153static void lge_reset(struct lge_softc *); 154static int lge_list_rx_init(struct lge_softc *); 155static int lge_list_tx_init(struct lge_softc *); 156 157#ifdef LGE_USEIOSPACE 158#define LGE_RES SYS_RES_IOPORT 159#define LGE_RID LGE_PCI_LOIO 160#else 161#define LGE_RES SYS_RES_MEMORY 162#define LGE_RID LGE_PCI_LOMEM 163#endif 164 165static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182}; 183 184static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188}; 189 190static devclass_t lge_devclass; 191 192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194MODULE_DEPEND(lge, pci, 1, 1, 1); 195MODULE_DEPEND(lge, ether, 1, 1, 1); 196MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198#define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202#define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206#define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209#define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212/* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215static void 216lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220{ 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244} 245 246/* 247 * Read a sequence of words from the EEPROM. 248 */ 249static void 250lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256{ 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270} 271 272static int 273lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276{ 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 printf("lge%d: PHY read timed out\n", sc->lge_unit); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302} 303 304static int 305lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308{ 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 printf("lge%d: PHY write timed out\n", sc->lge_unit); 323 return(0); 324 } 325 326 return(0); 327} 328 329static void 330lge_miibus_statchg(dev) 331 device_t dev; 332{ 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368} 369 370static void 371lge_setmulti(sc) 372 struct lge_softc *sc; 373{ 374 struct ifnet *ifp; 375 struct ifmultiaddr *ifma; 376 u_int32_t h = 0, hashes[2] = { 0, 0 }; 377 378 ifp = &sc->arpcom.ac_if; 379 380 /* Make sure multicast hash table is enabled. */ 381 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 382 383 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 384 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 385 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 386 return; 387 } 388 389 /* first, zot all the existing hash bits */ 390 CSR_WRITE_4(sc, LGE_MAR0, 0); 391 CSR_WRITE_4(sc, LGE_MAR1, 0); 392 393 /* now program new ones */ 394 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 395 if (ifma->ifma_addr->sa_family != AF_LINK) 396 continue; 397 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 398 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 399 if (h < 32) 400 hashes[0] |= (1 << h); 401 else 402 hashes[1] |= (1 << (h - 32)); 403 } 404 405 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 406 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 407 408 return; 409} 410 411static void 412lge_reset(sc) 413 struct lge_softc *sc; 414{ 415 register int i; 416 417 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 418 419 for (i = 0; i < LGE_TIMEOUT; i++) { 420 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 421 break; 422 } 423 424 if (i == LGE_TIMEOUT) 425 printf("lge%d: reset never completed\n", sc->lge_unit); 426 427 /* Wait a little while for the chip to get its brains in order. */ 428 DELAY(1000); 429 430 return; 431} 432 433/* 434 * Probe for a Level 1 chip. Check the PCI vendor and device 435 * IDs against our list and return a device name if we find a match. 436 */ 437static int 438lge_probe(dev) 439 device_t dev; 440{ 441 struct lge_type *t; 442 443 t = lge_devs; 444 445 while(t->lge_name != NULL) { 446 if ((pci_get_vendor(dev) == t->lge_vid) && 447 (pci_get_device(dev) == t->lge_did)) { 448 device_set_desc(dev, t->lge_name); 449 return(0); 450 } 451 t++; 452 } 453 454 return(ENXIO); 455} 456 457/* 458 * Attach the interface. Allocate softc structures, do ifmedia 459 * setup and ethernet/BPF attach. 460 */ 461static int 462lge_attach(dev) 463 device_t dev; 464{ 465 int s; 466 u_char eaddr[ETHER_ADDR_LEN]; 467 struct lge_softc *sc; 468 struct ifnet *ifp; 469 int unit, error = 0, rid; 470 471 s = splimp(); 472 473 sc = device_get_softc(dev); 474 unit = device_get_unit(dev); 475 bzero(sc, sizeof(struct lge_softc)); 476 /* 477 * Map control/status registers. 478 */ 479 pci_enable_busmaster(dev); 480 481 rid = LGE_RID; 482 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 483 484 if (sc->lge_res == NULL) { 485 printf("lge%d: couldn't map ports/memory\n", unit); 486 error = ENXIO; 487 goto fail; 488 } 489 490 sc->lge_btag = rman_get_bustag(sc->lge_res); 491 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 492 493 /* Allocate interrupt */ 494 rid = 0; 495 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 496 RF_SHAREABLE | RF_ACTIVE); 497 498 if (sc->lge_irq == NULL) { 499 printf("lge%d: couldn't map interrupt\n", unit); 500 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 501 error = ENXIO; 502 goto fail; 503 } 504 505 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 506 lge_intr, sc, &sc->lge_intrhand); 507 508 if (error) { 509 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 510 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 511 printf("lge%d: couldn't set up irq\n", unit); 512 goto fail; 513 } 514 515 /* Reset the adapter. */ 516 lge_reset(sc); 517 518 /* 519 * Get station address from the EEPROM. 520 */ 521 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 522 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 523 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 524 525 sc->lge_unit = unit; 526 callout_handle_init(&sc->lge_stat_ch); 527 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 528 529 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 530 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 531 532 if (sc->lge_ldata == NULL) { 533 printf("lge%d: no memory for list buffers!\n", unit); 534 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 535 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 536 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 537 error = ENXIO; 538 goto fail; 539 } 540 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 541 542 /* Try to allocate memory for jumbo buffers. */ 543 if (lge_alloc_jumbo_mem(sc)) { 544 printf("lge%d: jumbo buffer allocation failed\n", 545 sc->lge_unit); 546 contigfree(sc->lge_ldata, 547 sizeof(struct lge_list_data), M_DEVBUF); 548 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 549 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 550 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 551 error = ENXIO; 552 goto fail; 553 } 554 555 ifp = &sc->arpcom.ac_if; 556 ifp->if_softc = sc; 557 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 558 ifp->if_mtu = ETHERMTU; 559 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 560 ifp->if_ioctl = lge_ioctl; 561 ifp->if_start = lge_start; 562 ifp->if_watchdog = lge_watchdog; 563 ifp->if_init = lge_init; 564 ifp->if_baudrate = 1000000000; 565 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 566 ifp->if_capabilities = IFCAP_RXCSUM; 567 ifp->if_capenable = ifp->if_capabilities; 568 569 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 570 sc->lge_pcs = 1; 571 else 572 sc->lge_pcs = 0; 573 574 /* 575 * Do MII setup. 576 */ 577 if (mii_phy_probe(dev, &sc->lge_miibus, 578 lge_ifmedia_upd, lge_ifmedia_sts)) { 579 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 580 contigfree(sc->lge_ldata, 581 sizeof(struct lge_list_data), M_DEVBUF); 582 lge_free_jumbo_mem(sc); 583 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 584 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 585 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 586 error = ENXIO; 587 goto fail; 588 } 589 590 /* 591 * Call MI attach routine. 592 */ 593 ether_ifattach(ifp, eaddr); 594 callout_handle_init(&sc->lge_stat_ch); 595 596fail: 597 splx(s); 598 return(error); 599} 600 601static int 602lge_detach(dev) 603 device_t dev; 604{ 605 struct lge_softc *sc; 606 struct ifnet *ifp; 607 int s; 608 609 s = splimp(); 610 611 sc = device_get_softc(dev); 612 ifp = &sc->arpcom.ac_if; 613 614 lge_reset(sc); 615 lge_stop(sc); 616 ether_ifdetach(ifp); 617 618 bus_generic_detach(dev); 619 device_delete_child(dev, sc->lge_miibus); 620 621 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 622 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 623 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 624 625 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 626 lge_free_jumbo_mem(sc); 627 628 splx(s); 629 630 return(0); 631} 632 633/* 634 * Initialize the transmit descriptors. 635 */ 636static int 637lge_list_tx_init(sc) 638 struct lge_softc *sc; 639{ 640 struct lge_list_data *ld; 641 struct lge_ring_data *cd; 642 int i; 643 644 cd = &sc->lge_cdata; 645 ld = sc->lge_ldata; 646 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 647 ld->lge_tx_list[i].lge_mbuf = NULL; 648 ld->lge_tx_list[i].lge_ctl = 0; 649 } 650 651 cd->lge_tx_prod = cd->lge_tx_cons = 0; 652 653 return(0); 654} 655 656 657/* 658 * Initialize the RX descriptors and allocate mbufs for them. Note that 659 * we arralge the descriptors in a closed ring, so that the last descriptor 660 * points back to the first. 661 */ 662static int 663lge_list_rx_init(sc) 664 struct lge_softc *sc; 665{ 666 struct lge_list_data *ld; 667 struct lge_ring_data *cd; 668 int i; 669 670 ld = sc->lge_ldata; 671 cd = &sc->lge_cdata; 672 673 cd->lge_rx_prod = cd->lge_rx_cons = 0; 674 675 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 676 677 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 678 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 679 break; 680 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 681 return(ENOBUFS); 682 } 683 684 /* Clear possible 'rx command queue empty' interrupt. */ 685 CSR_READ_4(sc, LGE_ISR); 686 687 return(0); 688} 689 690/* 691 * Initialize an RX descriptor and attach an MBUF cluster. 692 */ 693static int 694lge_newbuf(sc, c, m) 695 struct lge_softc *sc; 696 struct lge_rx_desc *c; 697 struct mbuf *m; 698{ 699 struct mbuf *m_new = NULL; 700 caddr_t *buf = NULL; 701 702 if (m == NULL) { 703 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 704 if (m_new == NULL) { 705 printf("lge%d: no memory for rx list " 706 "-- packet dropped!\n", sc->lge_unit); 707 return(ENOBUFS); 708 } 709 710 /* Allocate the jumbo buffer */ 711 buf = lge_jalloc(sc); 712 if (buf == NULL) { 713#ifdef LGE_VERBOSE 714 printf("lge%d: jumbo allocation failed " 715 "-- packet dropped!\n", sc->lge_unit); 716#endif 717 m_freem(m_new); 718 return(ENOBUFS); 719 } 720 /* Attach the buffer to the mbuf */ 721 m_new->m_data = (void *)buf; 722 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 723 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 724 (struct lge_softc *)sc, 0, EXT_NET_DRV); 725 } else { 726 m_new = m; 727 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 728 m_new->m_data = m_new->m_ext.ext_buf; 729 } 730 731 /* 732 * Adjust alignment so packet payload begins on a 733 * longword boundary. Mandatory for Alpha, useful on 734 * x86 too. 735 */ 736 m_adj(m_new, ETHER_ALIGN); 737 738 c->lge_mbuf = m_new; 739 c->lge_fragptr_hi = 0; 740 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 741 c->lge_fraglen = m_new->m_len; 742 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 743 c->lge_sts = 0; 744 745 /* 746 * Put this buffer in the RX command FIFO. To do this, 747 * we just write the physical address of the descriptor 748 * into the RX descriptor address registers. Note that 749 * there are two registers, one high DWORD and one low 750 * DWORD, which lets us specify a 64-bit address if 751 * desired. We only use a 32-bit address for now. 752 * Writing to the low DWORD register is what actually 753 * causes the command to be issued, so we do that 754 * last. 755 */ 756 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 757 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 758 759 return(0); 760} 761 762static int 763lge_alloc_jumbo_mem(sc) 764 struct lge_softc *sc; 765{ 766 caddr_t ptr; 767 register int i; 768 struct lge_jpool_entry *entry; 769 770 /* Grab a big chunk o' storage. */ 771 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 772 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 773 774 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 775 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 776 return(ENOBUFS); 777 } 778 779 SLIST_INIT(&sc->lge_jfree_listhead); 780 SLIST_INIT(&sc->lge_jinuse_listhead); 781 782 /* 783 * Now divide it up into 9K pieces and save the addresses 784 * in an array. 785 */ 786 ptr = sc->lge_cdata.lge_jumbo_buf; 787 for (i = 0; i < LGE_JSLOTS; i++) { 788 sc->lge_cdata.lge_jslots[i] = ptr; 789 ptr += LGE_JLEN; 790 entry = malloc(sizeof(struct lge_jpool_entry), 791 M_DEVBUF, M_NOWAIT); 792 if (entry == NULL) { 793 printf("lge%d: no memory for jumbo " 794 "buffer queue!\n", sc->lge_unit); 795 return(ENOBUFS); 796 } 797 entry->slot = i; 798 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 799 entry, jpool_entries); 800 } 801 802 return(0); 803} 804 805static void 806lge_free_jumbo_mem(sc) 807 struct lge_softc *sc; 808{ 809 int i; 810 struct lge_jpool_entry *entry; 811 812 for (i = 0; i < LGE_JSLOTS; i++) { 813 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 814 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 815 free(entry, M_DEVBUF); 816 } 817 818 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 819 820 return; 821} 822 823/* 824 * Allocate a jumbo buffer. 825 */ 826static void * 827lge_jalloc(sc) 828 struct lge_softc *sc; 829{ 830 struct lge_jpool_entry *entry; 831 832 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 833 834 if (entry == NULL) { 835#ifdef LGE_VERBOSE 836 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 837#endif 838 return(NULL); 839 } 840 841 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 842 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 843 return(sc->lge_cdata.lge_jslots[entry->slot]); 844} 845 846/* 847 * Release a jumbo buffer. 848 */ 849static void 850lge_jfree(buf, args) 851 void *buf; 852 void *args; 853{ 854 struct lge_softc *sc; 855 int i; 856 struct lge_jpool_entry *entry; 857 858 /* Extract the softc struct pointer. */ 859 sc = args; 860 861 if (sc == NULL) 862 panic("lge_jfree: can't find softc pointer!"); 863 864 /* calculate the slot this buffer belongs to */ 865 i = ((vm_offset_t)buf 866 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 867 868 if ((i < 0) || (i >= LGE_JSLOTS)) 869 panic("lge_jfree: asked to free buffer that we don't manage!"); 870 871 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 872 if (entry == NULL) 873 panic("lge_jfree: buffer not in use!"); 874 entry->slot = i; 875 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 876 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 877 878 return; 879} 880 881/* 882 * A frame has been uploaded: pass the resulting mbuf chain up to 883 * the higher level protocols. 884 */ 885static void 886lge_rxeof(sc, cnt) 887 struct lge_softc *sc; 888 int cnt; 889{ 890 struct mbuf *m; 891 struct ifnet *ifp; 892 struct lge_rx_desc *cur_rx; 893 int c, i, total_len = 0; 894 u_int32_t rxsts, rxctl; 895 896 ifp = &sc->arpcom.ac_if; 897 898 /* Find out how many frames were processed. */ 899 c = cnt; 900 i = sc->lge_cdata.lge_rx_cons; 901 902 /* Suck them in. */ 903 while(c) { 904 struct mbuf *m0 = NULL; 905 906 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 907 rxctl = cur_rx->lge_ctl; 908 rxsts = cur_rx->lge_sts; 909 m = cur_rx->lge_mbuf; 910 cur_rx->lge_mbuf = NULL; 911 total_len = LGE_RXBYTES(cur_rx); 912 LGE_INC(i, LGE_RX_LIST_CNT); 913 c--; 914 915 /* 916 * If an error occurs, update stats, clear the 917 * status word and leave the mbuf cluster in place: 918 * it should simply get re-used next time this descriptor 919 * comes up in the ring. 920 */ 921 if (rxctl & LGE_RXCTL_ERRMASK) { 922 ifp->if_ierrors++; 923 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 924 continue; 925 } 926 927 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 928 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 929 ifp, NULL); 930 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 931 if (m0 == NULL) { 932 printf("lge%d: no receive buffers " 933 "available -- packet dropped!\n", 934 sc->lge_unit); 935 ifp->if_ierrors++; 936 continue; 937 } 938 m = m0; 939 } else { 940 m->m_pkthdr.rcvif = ifp; 941 m->m_pkthdr.len = m->m_len = total_len; 942 } 943 944 ifp->if_ipackets++; 945 946 /* Do IP checksum checking. */ 947 if (rxsts & LGE_RXSTS_ISIP) 948 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 949 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 950 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 951 if ((rxsts & LGE_RXSTS_ISTCP && 952 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 953 (rxsts & LGE_RXSTS_ISUDP && 954 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 955 m->m_pkthdr.csum_flags |= 956 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 957 m->m_pkthdr.csum_data = 0xffff; 958 } 959 960 (*ifp->if_input)(ifp, m); 961 } 962 963 sc->lge_cdata.lge_rx_cons = i; 964 965 return; 966} 967 968static void 969lge_rxeoc(sc) 970 struct lge_softc *sc; 971{ 972 struct ifnet *ifp; 973 974 ifp = &sc->arpcom.ac_if; 975 ifp->if_flags &= ~IFF_RUNNING; 976 lge_init(sc); 977 return; 978} 979 980/* 981 * A frame was downloaded to the chip. It's safe for us to clean up 982 * the list buffers. 983 */ 984 985static void 986lge_txeof(sc) 987 struct lge_softc *sc; 988{ 989 struct lge_tx_desc *cur_tx = NULL; 990 struct ifnet *ifp; 991 u_int32_t idx, txdone; 992 993 ifp = &sc->arpcom.ac_if; 994 995 /* Clear the timeout timer. */ 996 ifp->if_timer = 0; 997 998 /* 999 * Go through our tx list and free mbufs for those 1000 * frames that have been transmitted. 1001 */ 1002 idx = sc->lge_cdata.lge_tx_cons; 1003 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1004 1005 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1006 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1007 1008 ifp->if_opackets++; 1009 if (cur_tx->lge_mbuf != NULL) { 1010 m_freem(cur_tx->lge_mbuf); 1011 cur_tx->lge_mbuf = NULL; 1012 } 1013 cur_tx->lge_ctl = 0; 1014 1015 txdone--; 1016 LGE_INC(idx, LGE_TX_LIST_CNT); 1017 ifp->if_timer = 0; 1018 } 1019 1020 sc->lge_cdata.lge_tx_cons = idx; 1021 1022 if (cur_tx != NULL) 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 1025 return; 1026} 1027 1028static void 1029lge_tick(xsc) 1030 void *xsc; 1031{ 1032 struct lge_softc *sc; 1033 struct mii_data *mii; 1034 struct ifnet *ifp; 1035 int s; 1036 1037 s = splimp(); 1038 1039 sc = xsc; 1040 ifp = &sc->arpcom.ac_if; 1041 1042 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1043 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1044 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1045 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1046 1047 if (!sc->lge_link) { 1048 mii = device_get_softc(sc->lge_miibus); 1049 mii_tick(mii); 1050 if (mii->mii_media_status & IFM_ACTIVE && 1051 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1052 sc->lge_link++; 1053 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1054 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1055 printf("lge%d: gigabit link up\n", 1056 sc->lge_unit); 1057 if (ifp->if_snd.ifq_head != NULL) 1058 lge_start(ifp); 1059 } 1060 } 1061 1062 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1063 1064 splx(s); 1065 1066 return; 1067} 1068 1069static void 1070lge_intr(arg) 1071 void *arg; 1072{ 1073 struct lge_softc *sc; 1074 struct ifnet *ifp; 1075 u_int32_t status; 1076 1077 sc = arg; 1078 ifp = &sc->arpcom.ac_if; 1079 1080 /* Supress unwanted interrupts */ 1081 if (!(ifp->if_flags & IFF_UP)) { 1082 lge_stop(sc); 1083 return; 1084 } 1085 1086 for (;;) { 1087 /* 1088 * Reading the ISR register clears all interrupts, and 1089 * clears the 'interrupts enabled' bit in the IMR 1090 * register. 1091 */ 1092 status = CSR_READ_4(sc, LGE_ISR); 1093 1094 if ((status & LGE_INTRS) == 0) 1095 break; 1096 1097 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1098 lge_txeof(sc); 1099 1100 if (status & LGE_ISR_RXDMA_DONE) 1101 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1102 1103 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1104 lge_rxeoc(sc); 1105 1106 if (status & LGE_ISR_PHY_INTR) { 1107 sc->lge_link = 0; 1108 untimeout(lge_tick, sc, sc->lge_stat_ch); 1109 lge_tick(sc); 1110 } 1111 } 1112 1113 /* Re-enable interrupts. */ 1114 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1115 1116 if (ifp->if_snd.ifq_head != NULL) 1117 lge_start(ifp); 1118 1119 return; 1120} 1121 1122/* 1123 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1124 * pointers to the fragment pointers. 1125 */ 1126static int 1127lge_encap(sc, m_head, txidx) 1128 struct lge_softc *sc; 1129 struct mbuf *m_head; 1130 u_int32_t *txidx; 1131{ 1132 struct lge_frag *f = NULL; 1133 struct lge_tx_desc *cur_tx; 1134 struct mbuf *m; 1135 int frag = 0, tot_len = 0; 1136 1137 /* 1138 * Start packing the mbufs in this chain into 1139 * the fragment pointers. Stop when we run out 1140 * of fragments or hit the end of the mbuf chain. 1141 */ 1142 m = m_head; 1143 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1144 frag = 0; 1145 1146 for (m = m_head; m != NULL; m = m->m_next) { 1147 if (m->m_len != 0) { 1148 tot_len += m->m_len; 1149 f = &cur_tx->lge_frags[frag]; 1150 f->lge_fraglen = m->m_len; 1151 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1152 f->lge_fragptr_hi = 0; 1153 frag++; 1154 } 1155 } 1156 1157 if (m != NULL) 1158 return(ENOBUFS); 1159 1160 cur_tx->lge_mbuf = m_head; 1161 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1162 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1163 1164 /* Queue for transmit */ 1165 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1166 1167 return(0); 1168} 1169 1170/* 1171 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1172 * to the mbuf data regions directly in the transmit lists. We also save a 1173 * copy of the pointers since the transmit list fragment pointers are 1174 * physical addresses. 1175 */ 1176 1177static void 1178lge_start(ifp) 1179 struct ifnet *ifp; 1180{ 1181 struct lge_softc *sc; 1182 struct mbuf *m_head = NULL; 1183 u_int32_t idx; 1184 1185 sc = ifp->if_softc; 1186 1187 if (!sc->lge_link) 1188 return; 1189 1190 idx = sc->lge_cdata.lge_tx_prod; 1191 1192 if (ifp->if_flags & IFF_OACTIVE) 1193 return; 1194 1195 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1196 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1197 break; 1198 1199 IF_DEQUEUE(&ifp->if_snd, m_head); 1200 if (m_head == NULL) 1201 break; 1202 1203 if (lge_encap(sc, m_head, &idx)) { 1204 IF_PREPEND(&ifp->if_snd, m_head); 1205 ifp->if_flags |= IFF_OACTIVE; 1206 break; 1207 } 1208 1209 /* 1210 * If there's a BPF listener, bounce a copy of this frame 1211 * to him. 1212 */ 1213 BPF_MTAP(ifp, m_head); 1214 } 1215 1216 sc->lge_cdata.lge_tx_prod = idx; 1217 1218 /* 1219 * Set a timeout in case the chip goes out to lunch. 1220 */ 1221 ifp->if_timer = 5; 1222 1223 return; 1224} 1225 1226static void 1227lge_init(xsc) 1228 void *xsc; 1229{ 1230 struct lge_softc *sc = xsc; 1231 struct ifnet *ifp = &sc->arpcom.ac_if; 1232 struct mii_data *mii; 1233 int s; 1234 1235 if (ifp->if_flags & IFF_RUNNING) 1236 return; 1237 1238 s = splimp(); 1239 1240 /* 1241 * Cancel pending I/O and free all RX/TX buffers. 1242 */ 1243 lge_stop(sc); 1244 lge_reset(sc); 1245 1246 mii = device_get_softc(sc->lge_miibus); 1247 1248 /* Set MAC address */ 1249 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1250 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1251 1252 /* Init circular RX list. */ 1253 if (lge_list_rx_init(sc) == ENOBUFS) { 1254 printf("lge%d: initialization failed: no " 1255 "memory for rx buffers\n", sc->lge_unit); 1256 lge_stop(sc); 1257 (void)splx(s); 1258 return; 1259 } 1260 1261 /* 1262 * Init tx descriptors. 1263 */ 1264 lge_list_tx_init(sc); 1265 1266 /* Set initial value for MODE1 register. */ 1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1268 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1269 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1270 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1271 1272 /* If we want promiscuous mode, set the allframes bit. */ 1273 if (ifp->if_flags & IFF_PROMISC) { 1274 CSR_WRITE_4(sc, LGE_MODE1, 1275 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1276 } else { 1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1278 } 1279 1280 /* 1281 * Set the capture broadcast bit to capture broadcast frames. 1282 */ 1283 if (ifp->if_flags & IFF_BROADCAST) { 1284 CSR_WRITE_4(sc, LGE_MODE1, 1285 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1286 } else { 1287 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1288 } 1289 1290 /* Packet padding workaround? */ 1291 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1292 1293 /* No error frames */ 1294 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1295 1296 /* Receive large frames */ 1297 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1298 1299 /* Workaround: disable RX/TX flow control */ 1300 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1302 1303 /* Make sure to strip CRC from received frames */ 1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1305 1306 /* Turn off magic packet mode */ 1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1308 1309 /* Turn off all VLAN stuff */ 1310 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1311 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1312 1313 /* Workarond: FIFO overflow */ 1314 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1315 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1316 1317 /* 1318 * Load the multicast filter. 1319 */ 1320 lge_setmulti(sc); 1321 1322 /* 1323 * Enable hardware checksum validation for all received IPv4 1324 * packets, do not reject packets with bad checksums. 1325 */ 1326 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1327 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1328 LGE_MODE2_RX_ERRCSUM); 1329 1330 /* 1331 * Enable the delivery of PHY interrupts based on 1332 * link/speed/duplex status chalges. 1333 */ 1334 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1335 1336 /* Enable receiver and transmitter. */ 1337 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1338 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1339 1340 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1341 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1342 1343 /* 1344 * Enable interrupts. 1345 */ 1346 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1347 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1348 1349 lge_ifmedia_upd(ifp); 1350 1351 ifp->if_flags |= IFF_RUNNING; 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 1354 (void)splx(s); 1355 1356 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1357 1358 return; 1359} 1360 1361/* 1362 * Set media options. 1363 */ 1364static int 1365lge_ifmedia_upd(ifp) 1366 struct ifnet *ifp; 1367{ 1368 struct lge_softc *sc; 1369 struct mii_data *mii; 1370 1371 sc = ifp->if_softc; 1372 1373 mii = device_get_softc(sc->lge_miibus); 1374 sc->lge_link = 0; 1375 if (mii->mii_instance) { 1376 struct mii_softc *miisc; 1377 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1378 miisc = LIST_NEXT(miisc, mii_list)) 1379 mii_phy_reset(miisc); 1380 } 1381 mii_mediachg(mii); 1382 1383 return(0); 1384} 1385 1386/* 1387 * Report current media status. 1388 */ 1389static void 1390lge_ifmedia_sts(ifp, ifmr) 1391 struct ifnet *ifp; 1392 struct ifmediareq *ifmr; 1393{ 1394 struct lge_softc *sc; 1395 struct mii_data *mii; 1396 1397 sc = ifp->if_softc; 1398 1399 mii = device_get_softc(sc->lge_miibus); 1400 mii_pollstat(mii); 1401 ifmr->ifm_active = mii->mii_media_active; 1402 ifmr->ifm_status = mii->mii_media_status; 1403 1404 return; 1405} 1406 1407static int 1408lge_ioctl(ifp, command, data) 1409 struct ifnet *ifp; 1410 u_long command; 1411 caddr_t data; 1412{ 1413 struct lge_softc *sc = ifp->if_softc; 1414 struct ifreq *ifr = (struct ifreq *) data; 1415 struct mii_data *mii; 1416 int s, error = 0; 1417 1418 s = splimp(); 1419 1420 switch(command) { 1421 case SIOCSIFMTU: 1422 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1423 error = EINVAL; 1424 else 1425 ifp->if_mtu = ifr->ifr_mtu; 1426 break; 1427 case SIOCSIFFLAGS: 1428 if (ifp->if_flags & IFF_UP) { 1429 if (ifp->if_flags & IFF_RUNNING && 1430 ifp->if_flags & IFF_PROMISC && 1431 !(sc->lge_if_flags & IFF_PROMISC)) { 1432 CSR_WRITE_4(sc, LGE_MODE1, 1433 LGE_MODE1_SETRST_CTL1| 1434 LGE_MODE1_RX_PROMISC); 1435 } else if (ifp->if_flags & IFF_RUNNING && 1436 !(ifp->if_flags & IFF_PROMISC) && 1437 sc->lge_if_flags & IFF_PROMISC) { 1438 CSR_WRITE_4(sc, LGE_MODE1, 1439 LGE_MODE1_RX_PROMISC); 1440 } else { 1441 ifp->if_flags &= ~IFF_RUNNING; 1442 lge_init(sc); 1443 } 1444 } else { 1445 if (ifp->if_flags & IFF_RUNNING) 1446 lge_stop(sc); 1447 } 1448 sc->lge_if_flags = ifp->if_flags; 1449 error = 0; 1450 break; 1451 case SIOCADDMULTI: 1452 case SIOCDELMULTI: 1453 lge_setmulti(sc); 1454 error = 0; 1455 break; 1456 case SIOCGIFMEDIA: 1457 case SIOCSIFMEDIA: 1458 mii = device_get_softc(sc->lge_miibus); 1459 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1460 break; 1461 default: 1462 error = ether_ioctl(ifp, command, data); 1463 break; 1464 } 1465 1466 (void)splx(s); 1467 1468 return(error); 1469} 1470 1471static void 1472lge_watchdog(ifp) 1473 struct ifnet *ifp; 1474{ 1475 struct lge_softc *sc; 1476 1477 sc = ifp->if_softc; 1478 1479 ifp->if_oerrors++; 1480 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1481 1482 lge_stop(sc); 1483 lge_reset(sc); 1484 ifp->if_flags &= ~IFF_RUNNING; 1485 lge_init(sc); 1486 1487 if (ifp->if_snd.ifq_head != NULL) 1488 lge_start(ifp); 1489 1490 return; 1491} 1492 1493/* 1494 * Stop the adapter and free any mbufs allocated to the 1495 * RX and TX lists. 1496 */ 1497static void 1498lge_stop(sc) 1499 struct lge_softc *sc; 1500{ 1501 register int i; 1502 struct ifnet *ifp; 1503 1504 ifp = &sc->arpcom.ac_if; 1505 ifp->if_timer = 0; 1506 untimeout(lge_tick, sc, sc->lge_stat_ch); 1507 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1508 1509 /* Disable receiver and transmitter. */ 1510 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1511 sc->lge_link = 0; 1512 1513 /* 1514 * Free data in the RX lists. 1515 */ 1516 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1517 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1518 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1519 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1520 } 1521 } 1522 bzero((char *)&sc->lge_ldata->lge_rx_list, 1523 sizeof(sc->lge_ldata->lge_rx_list)); 1524 1525 /* 1526 * Free the TX list buffers. 1527 */ 1528 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1529 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1530 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1531 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1532 } 1533 } 1534 1535 bzero((char *)&sc->lge_ldata->lge_tx_list, 1536 sizeof(sc->lge_ldata->lge_tx_list)); 1537 1538 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1539 1540 return; 1541} 1542 1543/* 1544 * Stop all chip I/O so that the kernel's probe routines don't 1545 * get confused by errant DMAs when rebooting. 1546 */ 1547static void 1548lge_shutdown(dev) 1549 device_t dev; 1550{ 1551 struct lge_softc *sc; 1552 1553 sc = device_get_softc(dev); 1554 1555 lge_reset(sc); 1556 lge_stop(sc); 1557 1558 return; 1559} 1560