if_lge.c revision 129616
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 129616 2004-05-23 16:11:53Z mux $"); 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/socket.h> 79 80#include <net/if.h> 81#include <net/if_arp.h> 82#include <net/ethernet.h> 83#include <net/if_dl.h> 84#include <net/if_media.h> 85 86#include <net/bpf.h> 87 88#include <vm/vm.h> /* for vtophys */ 89#include <vm/pmap.h> /* for vtophys */ 90#include <machine/clock.h> /* for DELAY */ 91#include <machine/bus_pio.h> 92#include <machine/bus_memio.h> 93#include <machine/bus.h> 94#include <machine/resource.h> 95#include <sys/bus.h> 96#include <sys/rman.h> 97 98#include <dev/mii/mii.h> 99#include <dev/mii/miivar.h> 100 101#include <dev/pci/pcireg.h> 102#include <dev/pci/pcivar.h> 103 104#define LGE_USEIOSPACE 105 106#include <dev/lge/if_lgereg.h> 107 108/* "controller miibus0" required. See GENERIC if you get errors here. */ 109#include "miibus_if.h" 110 111/* 112 * Various supported device vendors/types and their names. 113 */ 114static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117}; 118 119static int lge_probe(device_t); 120static int lge_attach(device_t); 121static int lge_detach(device_t); 122 123static int lge_alloc_jumbo_mem(struct lge_softc *); 124static void lge_free_jumbo_mem(struct lge_softc *); 125static void *lge_jalloc(struct lge_softc *); 126static void lge_jfree(void *, void *); 127 128static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130static void lge_rxeof(struct lge_softc *, int); 131static void lge_rxeoc(struct lge_softc *); 132static void lge_txeof(struct lge_softc *); 133static void lge_intr(void *); 134static void lge_tick(void *); 135static void lge_start(struct ifnet *); 136static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137static void lge_init(void *); 138static void lge_stop(struct lge_softc *); 139static void lge_watchdog(struct ifnet *); 140static void lge_shutdown(device_t); 141static int lge_ifmedia_upd(struct ifnet *); 142static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147static int lge_miibus_readreg(device_t, int, int); 148static int lge_miibus_writereg(device_t, int, int, int); 149static void lge_miibus_statchg(device_t); 150 151static void lge_setmulti(struct lge_softc *); 152static uint32_t lge_mchash(const uint8_t *); 153static void lge_reset(struct lge_softc *); 154static int lge_list_rx_init(struct lge_softc *); 155static int lge_list_tx_init(struct lge_softc *); 156 157#ifdef LGE_USEIOSPACE 158#define LGE_RES SYS_RES_IOPORT 159#define LGE_RID LGE_PCI_LOIO 160#else 161#define LGE_RES SYS_RES_MEMORY 162#define LGE_RID LGE_PCI_LOMEM 163#endif 164 165static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182}; 183 184static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188}; 189 190static devclass_t lge_devclass; 191 192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194MODULE_DEPEND(lge, pci, 1, 1, 1); 195MODULE_DEPEND(lge, ether, 1, 1, 1); 196MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198#define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202#define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206#define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209#define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212/* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215static void 216lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220{ 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244} 245 246/* 247 * Read a sequence of words from the EEPROM. 248 */ 249static void 250lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256{ 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270} 271 272static int 273lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276{ 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 printf("lge%d: PHY read timed out\n", sc->lge_unit); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302} 303 304static int 305lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308{ 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 printf("lge%d: PHY write timed out\n", sc->lge_unit); 323 return(0); 324 } 325 326 return(0); 327} 328 329static void 330lge_miibus_statchg(dev) 331 device_t dev; 332{ 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368} 369 370static uint32_t 371lge_mchash(addr) 372 const uint8_t *addr; 373{ 374 uint32_t crc, carry; 375 int idx, bit; 376 uint8_t data; 377 378 /* Compute CRC for the address value. */ 379 crc = 0xFFFFFFFF; /* initial value */ 380 381 for (idx = 0; idx < 6; idx++) { 382 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 383 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 384 crc <<= 1; 385 if (carry) 386 crc = (crc ^ 0x04c11db6) | carry; 387 } 388 } 389 390 /* 391 * return the filter bit position 392 */ 393 return((crc >> 26) & 0x0000003F); 394} 395 396static void 397lge_setmulti(sc) 398 struct lge_softc *sc; 399{ 400 struct ifnet *ifp; 401 struct ifmultiaddr *ifma; 402 u_int32_t h = 0, hashes[2] = { 0, 0 }; 403 404 ifp = &sc->arpcom.ac_if; 405 406 /* Make sure multicast hash table is enabled. */ 407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 408 409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 410 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 411 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 412 return; 413 } 414 415 /* first, zot all the existing hash bits */ 416 CSR_WRITE_4(sc, LGE_MAR0, 0); 417 CSR_WRITE_4(sc, LGE_MAR1, 0); 418 419 /* now program new ones */ 420 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 421 if (ifma->ifma_addr->sa_family != AF_LINK) 422 continue; 423 h = lge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 424 if (h < 32) 425 hashes[0] |= (1 << h); 426 else 427 hashes[1] |= (1 << (h - 32)); 428 } 429 430 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 431 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 432 433 return; 434} 435 436static void 437lge_reset(sc) 438 struct lge_softc *sc; 439{ 440 register int i; 441 442 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 443 444 for (i = 0; i < LGE_TIMEOUT; i++) { 445 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 446 break; 447 } 448 449 if (i == LGE_TIMEOUT) 450 printf("lge%d: reset never completed\n", sc->lge_unit); 451 452 /* Wait a little while for the chip to get its brains in order. */ 453 DELAY(1000); 454 455 return; 456} 457 458/* 459 * Probe for a Level 1 chip. Check the PCI vendor and device 460 * IDs against our list and return a device name if we find a match. 461 */ 462static int 463lge_probe(dev) 464 device_t dev; 465{ 466 struct lge_type *t; 467 468 t = lge_devs; 469 470 while(t->lge_name != NULL) { 471 if ((pci_get_vendor(dev) == t->lge_vid) && 472 (pci_get_device(dev) == t->lge_did)) { 473 device_set_desc(dev, t->lge_name); 474 return(0); 475 } 476 t++; 477 } 478 479 return(ENXIO); 480} 481 482/* 483 * Attach the interface. Allocate softc structures, do ifmedia 484 * setup and ethernet/BPF attach. 485 */ 486static int 487lge_attach(dev) 488 device_t dev; 489{ 490 int s; 491 u_char eaddr[ETHER_ADDR_LEN]; 492 struct lge_softc *sc; 493 struct ifnet *ifp; 494 int unit, error = 0, rid; 495 496 s = splimp(); 497 498 sc = device_get_softc(dev); 499 unit = device_get_unit(dev); 500 bzero(sc, sizeof(struct lge_softc)); 501#ifndef BURN_BRIDGES 502 /* 503 * Handle power management nonsense. 504 */ 505 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 506 u_int32_t iobase, membase, irq; 507 508 /* Save important PCI config data. */ 509 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 510 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 511 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 512 513 /* Reset the power state. */ 514 printf("lge%d: chip is in D%d power mode " 515 "-- setting to D0\n", unit, 516 pci_get_powerstate(dev)); 517 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 518 519 /* Restore PCI config data. */ 520 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 521 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 522 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 523 } 524#endif 525 /* 526 * Map control/status registers. 527 */ 528 pci_enable_busmaster(dev); 529 530 rid = LGE_RID; 531 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 532 533 if (sc->lge_res == NULL) { 534 printf("lge%d: couldn't map ports/memory\n", unit); 535 error = ENXIO; 536 goto fail; 537 } 538 539 sc->lge_btag = rman_get_bustag(sc->lge_res); 540 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 541 542 /* Allocate interrupt */ 543 rid = 0; 544 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 545 RF_SHAREABLE | RF_ACTIVE); 546 547 if (sc->lge_irq == NULL) { 548 printf("lge%d: couldn't map interrupt\n", unit); 549 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 550 error = ENXIO; 551 goto fail; 552 } 553 554 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 555 lge_intr, sc, &sc->lge_intrhand); 556 557 if (error) { 558 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 559 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 560 printf("lge%d: couldn't set up irq\n", unit); 561 goto fail; 562 } 563 564 /* Reset the adapter. */ 565 lge_reset(sc); 566 567 /* 568 * Get station address from the EEPROM. 569 */ 570 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 571 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 572 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 573 574 sc->lge_unit = unit; 575 callout_handle_init(&sc->lge_stat_ch); 576 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 577 578 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 579 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 580 581 if (sc->lge_ldata == NULL) { 582 printf("lge%d: no memory for list buffers!\n", unit); 583 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 584 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 585 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 586 error = ENXIO; 587 goto fail; 588 } 589 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 590 591 /* Try to allocate memory for jumbo buffers. */ 592 if (lge_alloc_jumbo_mem(sc)) { 593 printf("lge%d: jumbo buffer allocation failed\n", 594 sc->lge_unit); 595 contigfree(sc->lge_ldata, 596 sizeof(struct lge_list_data), M_DEVBUF); 597 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 598 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 599 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 600 error = ENXIO; 601 goto fail; 602 } 603 604 ifp = &sc->arpcom.ac_if; 605 ifp->if_softc = sc; 606 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 607 ifp->if_mtu = ETHERMTU; 608 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 609 ifp->if_ioctl = lge_ioctl; 610 ifp->if_start = lge_start; 611 ifp->if_watchdog = lge_watchdog; 612 ifp->if_init = lge_init; 613 ifp->if_baudrate = 1000000000; 614 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 615 ifp->if_capabilities = IFCAP_RXCSUM; 616 ifp->if_capenable = ifp->if_capabilities; 617 618 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 619 sc->lge_pcs = 1; 620 else 621 sc->lge_pcs = 0; 622 623 /* 624 * Do MII setup. 625 */ 626 if (mii_phy_probe(dev, &sc->lge_miibus, 627 lge_ifmedia_upd, lge_ifmedia_sts)) { 628 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 629 contigfree(sc->lge_ldata, 630 sizeof(struct lge_list_data), M_DEVBUF); 631 lge_free_jumbo_mem(sc); 632 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 633 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 634 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 635 error = ENXIO; 636 goto fail; 637 } 638 639 /* 640 * Call MI attach routine. 641 */ 642 ether_ifattach(ifp, eaddr); 643 callout_handle_init(&sc->lge_stat_ch); 644 645fail: 646 splx(s); 647 return(error); 648} 649 650static int 651lge_detach(dev) 652 device_t dev; 653{ 654 struct lge_softc *sc; 655 struct ifnet *ifp; 656 int s; 657 658 s = splimp(); 659 660 sc = device_get_softc(dev); 661 ifp = &sc->arpcom.ac_if; 662 663 lge_reset(sc); 664 lge_stop(sc); 665 ether_ifdetach(ifp); 666 667 bus_generic_detach(dev); 668 device_delete_child(dev, sc->lge_miibus); 669 670 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 671 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 672 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 673 674 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 675 lge_free_jumbo_mem(sc); 676 677 splx(s); 678 679 return(0); 680} 681 682/* 683 * Initialize the transmit descriptors. 684 */ 685static int 686lge_list_tx_init(sc) 687 struct lge_softc *sc; 688{ 689 struct lge_list_data *ld; 690 struct lge_ring_data *cd; 691 int i; 692 693 cd = &sc->lge_cdata; 694 ld = sc->lge_ldata; 695 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 696 ld->lge_tx_list[i].lge_mbuf = NULL; 697 ld->lge_tx_list[i].lge_ctl = 0; 698 } 699 700 cd->lge_tx_prod = cd->lge_tx_cons = 0; 701 702 return(0); 703} 704 705 706/* 707 * Initialize the RX descriptors and allocate mbufs for them. Note that 708 * we arralge the descriptors in a closed ring, so that the last descriptor 709 * points back to the first. 710 */ 711static int 712lge_list_rx_init(sc) 713 struct lge_softc *sc; 714{ 715 struct lge_list_data *ld; 716 struct lge_ring_data *cd; 717 int i; 718 719 ld = sc->lge_ldata; 720 cd = &sc->lge_cdata; 721 722 cd->lge_rx_prod = cd->lge_rx_cons = 0; 723 724 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 725 726 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 727 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 728 break; 729 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 730 return(ENOBUFS); 731 } 732 733 /* Clear possible 'rx command queue empty' interrupt. */ 734 CSR_READ_4(sc, LGE_ISR); 735 736 return(0); 737} 738 739/* 740 * Initialize an RX descriptor and attach an MBUF cluster. 741 */ 742static int 743lge_newbuf(sc, c, m) 744 struct lge_softc *sc; 745 struct lge_rx_desc *c; 746 struct mbuf *m; 747{ 748 struct mbuf *m_new = NULL; 749 caddr_t *buf = NULL; 750 751 if (m == NULL) { 752 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 753 if (m_new == NULL) { 754 printf("lge%d: no memory for rx list " 755 "-- packet dropped!\n", sc->lge_unit); 756 return(ENOBUFS); 757 } 758 759 /* Allocate the jumbo buffer */ 760 buf = lge_jalloc(sc); 761 if (buf == NULL) { 762#ifdef LGE_VERBOSE 763 printf("lge%d: jumbo allocation failed " 764 "-- packet dropped!\n", sc->lge_unit); 765#endif 766 m_freem(m_new); 767 return(ENOBUFS); 768 } 769 /* Attach the buffer to the mbuf */ 770 m_new->m_data = (void *)buf; 771 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 772 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 773 (struct lge_softc *)sc, 0, EXT_NET_DRV); 774 } else { 775 m_new = m; 776 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 777 m_new->m_data = m_new->m_ext.ext_buf; 778 } 779 780 /* 781 * Adjust alignment so packet payload begins on a 782 * longword boundary. Mandatory for Alpha, useful on 783 * x86 too. 784 */ 785 m_adj(m_new, ETHER_ALIGN); 786 787 c->lge_mbuf = m_new; 788 c->lge_fragptr_hi = 0; 789 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 790 c->lge_fraglen = m_new->m_len; 791 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 792 c->lge_sts = 0; 793 794 /* 795 * Put this buffer in the RX command FIFO. To do this, 796 * we just write the physical address of the descriptor 797 * into the RX descriptor address registers. Note that 798 * there are two registers, one high DWORD and one low 799 * DWORD, which lets us specify a 64-bit address if 800 * desired. We only use a 32-bit address for now. 801 * Writing to the low DWORD register is what actually 802 * causes the command to be issued, so we do that 803 * last. 804 */ 805 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 806 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 807 808 return(0); 809} 810 811static int 812lge_alloc_jumbo_mem(sc) 813 struct lge_softc *sc; 814{ 815 caddr_t ptr; 816 register int i; 817 struct lge_jpool_entry *entry; 818 819 /* Grab a big chunk o' storage. */ 820 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 821 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 822 823 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 824 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 825 return(ENOBUFS); 826 } 827 828 SLIST_INIT(&sc->lge_jfree_listhead); 829 SLIST_INIT(&sc->lge_jinuse_listhead); 830 831 /* 832 * Now divide it up into 9K pieces and save the addresses 833 * in an array. 834 */ 835 ptr = sc->lge_cdata.lge_jumbo_buf; 836 for (i = 0; i < LGE_JSLOTS; i++) { 837 sc->lge_cdata.lge_jslots[i] = ptr; 838 ptr += LGE_JLEN; 839 entry = malloc(sizeof(struct lge_jpool_entry), 840 M_DEVBUF, M_NOWAIT); 841 if (entry == NULL) { 842 printf("lge%d: no memory for jumbo " 843 "buffer queue!\n", sc->lge_unit); 844 return(ENOBUFS); 845 } 846 entry->slot = i; 847 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 848 entry, jpool_entries); 849 } 850 851 return(0); 852} 853 854static void 855lge_free_jumbo_mem(sc) 856 struct lge_softc *sc; 857{ 858 int i; 859 struct lge_jpool_entry *entry; 860 861 for (i = 0; i < LGE_JSLOTS; i++) { 862 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 863 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 864 free(entry, M_DEVBUF); 865 } 866 867 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 868 869 return; 870} 871 872/* 873 * Allocate a jumbo buffer. 874 */ 875static void * 876lge_jalloc(sc) 877 struct lge_softc *sc; 878{ 879 struct lge_jpool_entry *entry; 880 881 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 882 883 if (entry == NULL) { 884#ifdef LGE_VERBOSE 885 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 886#endif 887 return(NULL); 888 } 889 890 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 891 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 892 return(sc->lge_cdata.lge_jslots[entry->slot]); 893} 894 895/* 896 * Release a jumbo buffer. 897 */ 898static void 899lge_jfree(buf, args) 900 void *buf; 901 void *args; 902{ 903 struct lge_softc *sc; 904 int i; 905 struct lge_jpool_entry *entry; 906 907 /* Extract the softc struct pointer. */ 908 sc = args; 909 910 if (sc == NULL) 911 panic("lge_jfree: can't find softc pointer!"); 912 913 /* calculate the slot this buffer belongs to */ 914 i = ((vm_offset_t)buf 915 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 916 917 if ((i < 0) || (i >= LGE_JSLOTS)) 918 panic("lge_jfree: asked to free buffer that we don't manage!"); 919 920 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 921 if (entry == NULL) 922 panic("lge_jfree: buffer not in use!"); 923 entry->slot = i; 924 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 925 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 926 927 return; 928} 929 930/* 931 * A frame has been uploaded: pass the resulting mbuf chain up to 932 * the higher level protocols. 933 */ 934static void 935lge_rxeof(sc, cnt) 936 struct lge_softc *sc; 937 int cnt; 938{ 939 struct mbuf *m; 940 struct ifnet *ifp; 941 struct lge_rx_desc *cur_rx; 942 int c, i, total_len = 0; 943 u_int32_t rxsts, rxctl; 944 945 ifp = &sc->arpcom.ac_if; 946 947 /* Find out how many frames were processed. */ 948 c = cnt; 949 i = sc->lge_cdata.lge_rx_cons; 950 951 /* Suck them in. */ 952 while(c) { 953 struct mbuf *m0 = NULL; 954 955 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 956 rxctl = cur_rx->lge_ctl; 957 rxsts = cur_rx->lge_sts; 958 m = cur_rx->lge_mbuf; 959 cur_rx->lge_mbuf = NULL; 960 total_len = LGE_RXBYTES(cur_rx); 961 LGE_INC(i, LGE_RX_LIST_CNT); 962 c--; 963 964 /* 965 * If an error occurs, update stats, clear the 966 * status word and leave the mbuf cluster in place: 967 * it should simply get re-used next time this descriptor 968 * comes up in the ring. 969 */ 970 if (rxctl & LGE_RXCTL_ERRMASK) { 971 ifp->if_ierrors++; 972 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 973 continue; 974 } 975 976 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 977 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 978 ifp, NULL); 979 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 980 if (m0 == NULL) { 981 printf("lge%d: no receive buffers " 982 "available -- packet dropped!\n", 983 sc->lge_unit); 984 ifp->if_ierrors++; 985 continue; 986 } 987 m = m0; 988 } else { 989 m->m_pkthdr.rcvif = ifp; 990 m->m_pkthdr.len = m->m_len = total_len; 991 } 992 993 ifp->if_ipackets++; 994 995 /* Do IP checksum checking. */ 996 if (rxsts & LGE_RXSTS_ISIP) 997 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 998 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 999 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1000 if ((rxsts & LGE_RXSTS_ISTCP && 1001 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1002 (rxsts & LGE_RXSTS_ISUDP && 1003 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1004 m->m_pkthdr.csum_flags |= 1005 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1006 m->m_pkthdr.csum_data = 0xffff; 1007 } 1008 1009 (*ifp->if_input)(ifp, m); 1010 } 1011 1012 sc->lge_cdata.lge_rx_cons = i; 1013 1014 return; 1015} 1016 1017static void 1018lge_rxeoc(sc) 1019 struct lge_softc *sc; 1020{ 1021 struct ifnet *ifp; 1022 1023 ifp = &sc->arpcom.ac_if; 1024 ifp->if_flags &= ~IFF_RUNNING; 1025 lge_init(sc); 1026 return; 1027} 1028 1029/* 1030 * A frame was downloaded to the chip. It's safe for us to clean up 1031 * the list buffers. 1032 */ 1033 1034static void 1035lge_txeof(sc) 1036 struct lge_softc *sc; 1037{ 1038 struct lge_tx_desc *cur_tx = NULL; 1039 struct ifnet *ifp; 1040 u_int32_t idx, txdone; 1041 1042 ifp = &sc->arpcom.ac_if; 1043 1044 /* Clear the timeout timer. */ 1045 ifp->if_timer = 0; 1046 1047 /* 1048 * Go through our tx list and free mbufs for those 1049 * frames that have been transmitted. 1050 */ 1051 idx = sc->lge_cdata.lge_tx_cons; 1052 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1053 1054 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1055 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1056 1057 ifp->if_opackets++; 1058 if (cur_tx->lge_mbuf != NULL) { 1059 m_freem(cur_tx->lge_mbuf); 1060 cur_tx->lge_mbuf = NULL; 1061 } 1062 cur_tx->lge_ctl = 0; 1063 1064 txdone--; 1065 LGE_INC(idx, LGE_TX_LIST_CNT); 1066 ifp->if_timer = 0; 1067 } 1068 1069 sc->lge_cdata.lge_tx_cons = idx; 1070 1071 if (cur_tx != NULL) 1072 ifp->if_flags &= ~IFF_OACTIVE; 1073 1074 return; 1075} 1076 1077static void 1078lge_tick(xsc) 1079 void *xsc; 1080{ 1081 struct lge_softc *sc; 1082 struct mii_data *mii; 1083 struct ifnet *ifp; 1084 int s; 1085 1086 s = splimp(); 1087 1088 sc = xsc; 1089 ifp = &sc->arpcom.ac_if; 1090 1091 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1092 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1093 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1094 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1095 1096 if (!sc->lge_link) { 1097 mii = device_get_softc(sc->lge_miibus); 1098 mii_tick(mii); 1099 if (mii->mii_media_status & IFM_ACTIVE && 1100 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1101 sc->lge_link++; 1102 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1103 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1104 printf("lge%d: gigabit link up\n", 1105 sc->lge_unit); 1106 if (ifp->if_snd.ifq_head != NULL) 1107 lge_start(ifp); 1108 } 1109 } 1110 1111 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1112 1113 splx(s); 1114 1115 return; 1116} 1117 1118static void 1119lge_intr(arg) 1120 void *arg; 1121{ 1122 struct lge_softc *sc; 1123 struct ifnet *ifp; 1124 u_int32_t status; 1125 1126 sc = arg; 1127 ifp = &sc->arpcom.ac_if; 1128 1129 /* Supress unwanted interrupts */ 1130 if (!(ifp->if_flags & IFF_UP)) { 1131 lge_stop(sc); 1132 return; 1133 } 1134 1135 for (;;) { 1136 /* 1137 * Reading the ISR register clears all interrupts, and 1138 * clears the 'interrupts enabled' bit in the IMR 1139 * register. 1140 */ 1141 status = CSR_READ_4(sc, LGE_ISR); 1142 1143 if ((status & LGE_INTRS) == 0) 1144 break; 1145 1146 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1147 lge_txeof(sc); 1148 1149 if (status & LGE_ISR_RXDMA_DONE) 1150 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1151 1152 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1153 lge_rxeoc(sc); 1154 1155 if (status & LGE_ISR_PHY_INTR) { 1156 sc->lge_link = 0; 1157 untimeout(lge_tick, sc, sc->lge_stat_ch); 1158 lge_tick(sc); 1159 } 1160 } 1161 1162 /* Re-enable interrupts. */ 1163 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1164 1165 if (ifp->if_snd.ifq_head != NULL) 1166 lge_start(ifp); 1167 1168 return; 1169} 1170 1171/* 1172 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1173 * pointers to the fragment pointers. 1174 */ 1175static int 1176lge_encap(sc, m_head, txidx) 1177 struct lge_softc *sc; 1178 struct mbuf *m_head; 1179 u_int32_t *txidx; 1180{ 1181 struct lge_frag *f = NULL; 1182 struct lge_tx_desc *cur_tx; 1183 struct mbuf *m; 1184 int frag = 0, tot_len = 0; 1185 1186 /* 1187 * Start packing the mbufs in this chain into 1188 * the fragment pointers. Stop when we run out 1189 * of fragments or hit the end of the mbuf chain. 1190 */ 1191 m = m_head; 1192 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1193 frag = 0; 1194 1195 for (m = m_head; m != NULL; m = m->m_next) { 1196 if (m->m_len != 0) { 1197 tot_len += m->m_len; 1198 f = &cur_tx->lge_frags[frag]; 1199 f->lge_fraglen = m->m_len; 1200 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1201 f->lge_fragptr_hi = 0; 1202 frag++; 1203 } 1204 } 1205 1206 if (m != NULL) 1207 return(ENOBUFS); 1208 1209 cur_tx->lge_mbuf = m_head; 1210 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1211 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1212 1213 /* Queue for transmit */ 1214 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1215 1216 return(0); 1217} 1218 1219/* 1220 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1221 * to the mbuf data regions directly in the transmit lists. We also save a 1222 * copy of the pointers since the transmit list fragment pointers are 1223 * physical addresses. 1224 */ 1225 1226static void 1227lge_start(ifp) 1228 struct ifnet *ifp; 1229{ 1230 struct lge_softc *sc; 1231 struct mbuf *m_head = NULL; 1232 u_int32_t idx; 1233 1234 sc = ifp->if_softc; 1235 1236 if (!sc->lge_link) 1237 return; 1238 1239 idx = sc->lge_cdata.lge_tx_prod; 1240 1241 if (ifp->if_flags & IFF_OACTIVE) 1242 return; 1243 1244 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1245 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1246 break; 1247 1248 IF_DEQUEUE(&ifp->if_snd, m_head); 1249 if (m_head == NULL) 1250 break; 1251 1252 if (lge_encap(sc, m_head, &idx)) { 1253 IF_PREPEND(&ifp->if_snd, m_head); 1254 ifp->if_flags |= IFF_OACTIVE; 1255 break; 1256 } 1257 1258 /* 1259 * If there's a BPF listener, bounce a copy of this frame 1260 * to him. 1261 */ 1262 BPF_MTAP(ifp, m_head); 1263 } 1264 1265 sc->lge_cdata.lge_tx_prod = idx; 1266 1267 /* 1268 * Set a timeout in case the chip goes out to lunch. 1269 */ 1270 ifp->if_timer = 5; 1271 1272 return; 1273} 1274 1275static void 1276lge_init(xsc) 1277 void *xsc; 1278{ 1279 struct lge_softc *sc = xsc; 1280 struct ifnet *ifp = &sc->arpcom.ac_if; 1281 struct mii_data *mii; 1282 int s; 1283 1284 if (ifp->if_flags & IFF_RUNNING) 1285 return; 1286 1287 s = splimp(); 1288 1289 /* 1290 * Cancel pending I/O and free all RX/TX buffers. 1291 */ 1292 lge_stop(sc); 1293 lge_reset(sc); 1294 1295 mii = device_get_softc(sc->lge_miibus); 1296 1297 /* Set MAC address */ 1298 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1299 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1300 1301 /* Init circular RX list. */ 1302 if (lge_list_rx_init(sc) == ENOBUFS) { 1303 printf("lge%d: initialization failed: no " 1304 "memory for rx buffers\n", sc->lge_unit); 1305 lge_stop(sc); 1306 (void)splx(s); 1307 return; 1308 } 1309 1310 /* 1311 * Init tx descriptors. 1312 */ 1313 lge_list_tx_init(sc); 1314 1315 /* Set initial value for MODE1 register. */ 1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1317 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1318 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1319 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1320 1321 /* If we want promiscuous mode, set the allframes bit. */ 1322 if (ifp->if_flags & IFF_PROMISC) { 1323 CSR_WRITE_4(sc, LGE_MODE1, 1324 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1325 } else { 1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1327 } 1328 1329 /* 1330 * Set the capture broadcast bit to capture broadcast frames. 1331 */ 1332 if (ifp->if_flags & IFF_BROADCAST) { 1333 CSR_WRITE_4(sc, LGE_MODE1, 1334 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1335 } else { 1336 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1337 } 1338 1339 /* Packet padding workaround? */ 1340 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1341 1342 /* No error frames */ 1343 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1344 1345 /* Receive large frames */ 1346 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1347 1348 /* Workaround: disable RX/TX flow control */ 1349 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1351 1352 /* Make sure to strip CRC from received frames */ 1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1354 1355 /* Turn off magic packet mode */ 1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1357 1358 /* Turn off all VLAN stuff */ 1359 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1360 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1361 1362 /* Workarond: FIFO overflow */ 1363 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1364 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1365 1366 /* 1367 * Load the multicast filter. 1368 */ 1369 lge_setmulti(sc); 1370 1371 /* 1372 * Enable hardware checksum validation for all received IPv4 1373 * packets, do not reject packets with bad checksums. 1374 */ 1375 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1376 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1377 LGE_MODE2_RX_ERRCSUM); 1378 1379 /* 1380 * Enable the delivery of PHY interrupts based on 1381 * link/speed/duplex status chalges. 1382 */ 1383 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1384 1385 /* Enable receiver and transmitter. */ 1386 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1387 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1388 1389 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1391 1392 /* 1393 * Enable interrupts. 1394 */ 1395 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1396 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1397 1398 lge_ifmedia_upd(ifp); 1399 1400 ifp->if_flags |= IFF_RUNNING; 1401 ifp->if_flags &= ~IFF_OACTIVE; 1402 1403 (void)splx(s); 1404 1405 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1406 1407 return; 1408} 1409 1410/* 1411 * Set media options. 1412 */ 1413static int 1414lge_ifmedia_upd(ifp) 1415 struct ifnet *ifp; 1416{ 1417 struct lge_softc *sc; 1418 struct mii_data *mii; 1419 1420 sc = ifp->if_softc; 1421 1422 mii = device_get_softc(sc->lge_miibus); 1423 sc->lge_link = 0; 1424 if (mii->mii_instance) { 1425 struct mii_softc *miisc; 1426 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1427 miisc = LIST_NEXT(miisc, mii_list)) 1428 mii_phy_reset(miisc); 1429 } 1430 mii_mediachg(mii); 1431 1432 return(0); 1433} 1434 1435/* 1436 * Report current media status. 1437 */ 1438static void 1439lge_ifmedia_sts(ifp, ifmr) 1440 struct ifnet *ifp; 1441 struct ifmediareq *ifmr; 1442{ 1443 struct lge_softc *sc; 1444 struct mii_data *mii; 1445 1446 sc = ifp->if_softc; 1447 1448 mii = device_get_softc(sc->lge_miibus); 1449 mii_pollstat(mii); 1450 ifmr->ifm_active = mii->mii_media_active; 1451 ifmr->ifm_status = mii->mii_media_status; 1452 1453 return; 1454} 1455 1456static int 1457lge_ioctl(ifp, command, data) 1458 struct ifnet *ifp; 1459 u_long command; 1460 caddr_t data; 1461{ 1462 struct lge_softc *sc = ifp->if_softc; 1463 struct ifreq *ifr = (struct ifreq *) data; 1464 struct mii_data *mii; 1465 int s, error = 0; 1466 1467 s = splimp(); 1468 1469 switch(command) { 1470 case SIOCSIFMTU: 1471 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1472 error = EINVAL; 1473 else 1474 ifp->if_mtu = ifr->ifr_mtu; 1475 break; 1476 case SIOCSIFFLAGS: 1477 if (ifp->if_flags & IFF_UP) { 1478 if (ifp->if_flags & IFF_RUNNING && 1479 ifp->if_flags & IFF_PROMISC && 1480 !(sc->lge_if_flags & IFF_PROMISC)) { 1481 CSR_WRITE_4(sc, LGE_MODE1, 1482 LGE_MODE1_SETRST_CTL1| 1483 LGE_MODE1_RX_PROMISC); 1484 } else if (ifp->if_flags & IFF_RUNNING && 1485 !(ifp->if_flags & IFF_PROMISC) && 1486 sc->lge_if_flags & IFF_PROMISC) { 1487 CSR_WRITE_4(sc, LGE_MODE1, 1488 LGE_MODE1_RX_PROMISC); 1489 } else { 1490 ifp->if_flags &= ~IFF_RUNNING; 1491 lge_init(sc); 1492 } 1493 } else { 1494 if (ifp->if_flags & IFF_RUNNING) 1495 lge_stop(sc); 1496 } 1497 sc->lge_if_flags = ifp->if_flags; 1498 error = 0; 1499 break; 1500 case SIOCADDMULTI: 1501 case SIOCDELMULTI: 1502 lge_setmulti(sc); 1503 error = 0; 1504 break; 1505 case SIOCGIFMEDIA: 1506 case SIOCSIFMEDIA: 1507 mii = device_get_softc(sc->lge_miibus); 1508 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1509 break; 1510 default: 1511 error = ether_ioctl(ifp, command, data); 1512 break; 1513 } 1514 1515 (void)splx(s); 1516 1517 return(error); 1518} 1519 1520static void 1521lge_watchdog(ifp) 1522 struct ifnet *ifp; 1523{ 1524 struct lge_softc *sc; 1525 1526 sc = ifp->if_softc; 1527 1528 ifp->if_oerrors++; 1529 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1530 1531 lge_stop(sc); 1532 lge_reset(sc); 1533 ifp->if_flags &= ~IFF_RUNNING; 1534 lge_init(sc); 1535 1536 if (ifp->if_snd.ifq_head != NULL) 1537 lge_start(ifp); 1538 1539 return; 1540} 1541 1542/* 1543 * Stop the adapter and free any mbufs allocated to the 1544 * RX and TX lists. 1545 */ 1546static void 1547lge_stop(sc) 1548 struct lge_softc *sc; 1549{ 1550 register int i; 1551 struct ifnet *ifp; 1552 1553 ifp = &sc->arpcom.ac_if; 1554 ifp->if_timer = 0; 1555 untimeout(lge_tick, sc, sc->lge_stat_ch); 1556 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1557 1558 /* Disable receiver and transmitter. */ 1559 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1560 sc->lge_link = 0; 1561 1562 /* 1563 * Free data in the RX lists. 1564 */ 1565 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1566 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1567 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1568 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1569 } 1570 } 1571 bzero((char *)&sc->lge_ldata->lge_rx_list, 1572 sizeof(sc->lge_ldata->lge_rx_list)); 1573 1574 /* 1575 * Free the TX list buffers. 1576 */ 1577 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1578 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1579 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1580 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1581 } 1582 } 1583 1584 bzero((char *)&sc->lge_ldata->lge_tx_list, 1585 sizeof(sc->lge_ldata->lge_tx_list)); 1586 1587 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1588 1589 return; 1590} 1591 1592/* 1593 * Stop all chip I/O so that the kernel's probe routines don't 1594 * get confused by errant DMAs when rebooting. 1595 */ 1596static void 1597lge_shutdown(dev) 1598 device_t dev; 1599{ 1600 struct lge_softc *sc; 1601 1602 sc = device_get_softc(dev); 1603 1604 lge_reset(sc); 1605 lge_stop(sc); 1606 1607 return; 1608} 1609