if_lge.c revision 126966
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 126966 2004-03-14 07:12:25Z mdodd $"); 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/socket.h> 79 80#include <net/if.h> 81#include <net/if_arp.h> 82#include <net/ethernet.h> 83#include <net/if_dl.h> 84#include <net/if_media.h> 85 86#include <net/bpf.h> 87 88#include <vm/vm.h> /* for vtophys */ 89#include <vm/pmap.h> /* for vtophys */ 90#include <machine/clock.h> /* for DELAY */ 91#include <machine/bus_pio.h> 92#include <machine/bus_memio.h> 93#include <machine/bus.h> 94#include <machine/resource.h> 95#include <sys/bus.h> 96#include <sys/rman.h> 97 98#include <dev/mii/mii.h> 99#include <dev/mii/miivar.h> 100 101#include <dev/pci/pcireg.h> 102#include <dev/pci/pcivar.h> 103 104#define LGE_USEIOSPACE 105 106#include <dev/lge/if_lgereg.h> 107 108/* "controller miibus0" required. See GENERIC if you get errors here. */ 109#include "miibus_if.h" 110 111/* 112 * Various supported device vendors/types and their names. 113 */ 114static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117}; 118 119static int lge_probe(device_t); 120static int lge_attach(device_t); 121static int lge_detach(device_t); 122 123static int lge_alloc_jumbo_mem(struct lge_softc *); 124static void lge_free_jumbo_mem(struct lge_softc *); 125static void *lge_jalloc(struct lge_softc *); 126static void lge_jfree(void *, void *); 127 128static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130static void lge_rxeof(struct lge_softc *, int); 131static void lge_rxeoc(struct lge_softc *); 132static void lge_txeof(struct lge_softc *); 133static void lge_intr(void *); 134static void lge_tick(void *); 135static void lge_start(struct ifnet *); 136static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137static void lge_init(void *); 138static void lge_stop(struct lge_softc *); 139static void lge_watchdog(struct ifnet *); 140static void lge_shutdown(device_t); 141static int lge_ifmedia_upd(struct ifnet *); 142static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147static int lge_miibus_readreg(device_t, int, int); 148static int lge_miibus_writereg(device_t, int, int, int); 149static void lge_miibus_statchg(device_t); 150 151static void lge_setmulti(struct lge_softc *); 152static uint32_t lge_mchash(const uint8_t *); 153static void lge_reset(struct lge_softc *); 154static int lge_list_rx_init(struct lge_softc *); 155static int lge_list_tx_init(struct lge_softc *); 156 157#ifdef LGE_USEIOSPACE 158#define LGE_RES SYS_RES_IOPORT 159#define LGE_RID LGE_PCI_LOIO 160#else 161#define LGE_RES SYS_RES_MEMORY 162#define LGE_RID LGE_PCI_LOMEM 163#endif 164 165static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182}; 183 184static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188}; 189 190static devclass_t lge_devclass; 191 192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194MODULE_DEPEND(lge, pci, 1, 1, 1); 195MODULE_DEPEND(lge, ether, 1, 1, 1); 196MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198#define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202#define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206#define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209#define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212/* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215static void 216lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220{ 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244} 245 246/* 247 * Read a sequence of words from the EEPROM. 248 */ 249static void 250lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256{ 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270} 271 272static int 273lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276{ 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 printf("lge%d: PHY read timed out\n", sc->lge_unit); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302} 303 304static int 305lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308{ 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 printf("lge%d: PHY write timed out\n", sc->lge_unit); 323 return(0); 324 } 325 326 return(0); 327} 328 329static void 330lge_miibus_statchg(dev) 331 device_t dev; 332{ 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368} 369 370static uint32_t 371lge_mchash(addr) 372 const uint8_t *addr; 373{ 374 uint32_t crc, carry; 375 int idx, bit; 376 uint8_t data; 377 378 /* Compute CRC for the address value. */ 379 crc = 0xFFFFFFFF; /* initial value */ 380 381 for (idx = 0; idx < 6; idx++) { 382 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 383 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 384 crc <<= 1; 385 if (carry) 386 crc = (crc ^ 0x04c11db6) | carry; 387 } 388 } 389 390 /* 391 * return the filter bit position 392 */ 393 return((crc >> 26) & 0x0000003F); 394} 395 396static void 397lge_setmulti(sc) 398 struct lge_softc *sc; 399{ 400 struct ifnet *ifp; 401 struct ifmultiaddr *ifma; 402 u_int32_t h = 0, hashes[2] = { 0, 0 }; 403 404 ifp = &sc->arpcom.ac_if; 405 406 /* Make sure multicast hash table is enabled. */ 407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 408 409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 410 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 411 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 412 return; 413 } 414 415 /* first, zot all the existing hash bits */ 416 CSR_WRITE_4(sc, LGE_MAR0, 0); 417 CSR_WRITE_4(sc, LGE_MAR1, 0); 418 419 /* now program new ones */ 420 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 421 if (ifma->ifma_addr->sa_family != AF_LINK) 422 continue; 423 h = lge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 424 if (h < 32) 425 hashes[0] |= (1 << h); 426 else 427 hashes[1] |= (1 << (h - 32)); 428 } 429 430 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 431 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 432 433 return; 434} 435 436static void 437lge_reset(sc) 438 struct lge_softc *sc; 439{ 440 register int i; 441 442 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 443 444 for (i = 0; i < LGE_TIMEOUT; i++) { 445 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 446 break; 447 } 448 449 if (i == LGE_TIMEOUT) 450 printf("lge%d: reset never completed\n", sc->lge_unit); 451 452 /* Wait a little while for the chip to get its brains in order. */ 453 DELAY(1000); 454 455 return; 456} 457 458/* 459 * Probe for a Level 1 chip. Check the PCI vendor and device 460 * IDs against our list and return a device name if we find a match. 461 */ 462static int 463lge_probe(dev) 464 device_t dev; 465{ 466 struct lge_type *t; 467 468 t = lge_devs; 469 470 while(t->lge_name != NULL) { 471 if ((pci_get_vendor(dev) == t->lge_vid) && 472 (pci_get_device(dev) == t->lge_did)) { 473 device_set_desc(dev, t->lge_name); 474 return(0); 475 } 476 t++; 477 } 478 479 return(ENXIO); 480} 481 482/* 483 * Attach the interface. Allocate softc structures, do ifmedia 484 * setup and ethernet/BPF attach. 485 */ 486static int 487lge_attach(dev) 488 device_t dev; 489{ 490 int s; 491 u_char eaddr[ETHER_ADDR_LEN]; 492 struct lge_softc *sc; 493 struct ifnet *ifp; 494 int unit, error = 0, rid; 495 496 s = splimp(); 497 498 sc = device_get_softc(dev); 499 unit = device_get_unit(dev); 500 bzero(sc, sizeof(struct lge_softc)); 501#ifndef BURN_BRIDGES 502 /* 503 * Handle power management nonsense. 504 */ 505 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 506 u_int32_t iobase, membase, irq; 507 508 /* Save important PCI config data. */ 509 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 510 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 511 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 512 513 /* Reset the power state. */ 514 printf("lge%d: chip is in D%d power mode " 515 "-- setting to D0\n", unit, 516 pci_get_powerstate(dev)); 517 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 518 519 /* Restore PCI config data. */ 520 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 521 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 522 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 523 } 524#endif 525 /* 526 * Map control/status registers. 527 */ 528 pci_enable_busmaster(dev); 529 530 rid = LGE_RID; 531 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 532 0, ~0, 1, RF_ACTIVE); 533 534 if (sc->lge_res == NULL) { 535 printf("lge%d: couldn't map ports/memory\n", unit); 536 error = ENXIO; 537 goto fail; 538 } 539 540 sc->lge_btag = rman_get_bustag(sc->lge_res); 541 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 542 543 /* Allocate interrupt */ 544 rid = 0; 545 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 546 RF_SHAREABLE | RF_ACTIVE); 547 548 if (sc->lge_irq == NULL) { 549 printf("lge%d: couldn't map interrupt\n", unit); 550 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 551 error = ENXIO; 552 goto fail; 553 } 554 555 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 556 lge_intr, sc, &sc->lge_intrhand); 557 558 if (error) { 559 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 560 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 561 printf("lge%d: couldn't set up irq\n", unit); 562 goto fail; 563 } 564 565 /* Reset the adapter. */ 566 lge_reset(sc); 567 568 /* 569 * Get station address from the EEPROM. 570 */ 571 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 572 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 573 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 574 575 sc->lge_unit = unit; 576 callout_handle_init(&sc->lge_stat_ch); 577 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 578 579 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 580 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 581 582 if (sc->lge_ldata == NULL) { 583 printf("lge%d: no memory for list buffers!\n", unit); 584 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 585 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 586 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 587 error = ENXIO; 588 goto fail; 589 } 590 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 591 592 /* Try to allocate memory for jumbo buffers. */ 593 if (lge_alloc_jumbo_mem(sc)) { 594 printf("lge%d: jumbo buffer allocation failed\n", 595 sc->lge_unit); 596 contigfree(sc->lge_ldata, 597 sizeof(struct lge_list_data), M_DEVBUF); 598 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 599 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 600 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 601 error = ENXIO; 602 goto fail; 603 } 604 605 ifp = &sc->arpcom.ac_if; 606 ifp->if_softc = sc; 607 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 608 ifp->if_mtu = ETHERMTU; 609 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 610 ifp->if_ioctl = lge_ioctl; 611 ifp->if_output = ether_output; 612 ifp->if_start = lge_start; 613 ifp->if_watchdog = lge_watchdog; 614 ifp->if_init = lge_init; 615 ifp->if_baudrate = 1000000000; 616 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 617 ifp->if_capabilities = IFCAP_RXCSUM; 618 ifp->if_capenable = ifp->if_capabilities; 619 620 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 621 sc->lge_pcs = 1; 622 else 623 sc->lge_pcs = 0; 624 625 /* 626 * Do MII setup. 627 */ 628 if (mii_phy_probe(dev, &sc->lge_miibus, 629 lge_ifmedia_upd, lge_ifmedia_sts)) { 630 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 631 contigfree(sc->lge_ldata, 632 sizeof(struct lge_list_data), M_DEVBUF); 633 lge_free_jumbo_mem(sc); 634 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 635 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 636 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 637 error = ENXIO; 638 goto fail; 639 } 640 641 /* 642 * Call MI attach routine. 643 */ 644 ether_ifattach(ifp, eaddr); 645 callout_handle_init(&sc->lge_stat_ch); 646 647fail: 648 splx(s); 649 return(error); 650} 651 652static int 653lge_detach(dev) 654 device_t dev; 655{ 656 struct lge_softc *sc; 657 struct ifnet *ifp; 658 int s; 659 660 s = splimp(); 661 662 sc = device_get_softc(dev); 663 ifp = &sc->arpcom.ac_if; 664 665 lge_reset(sc); 666 lge_stop(sc); 667 ether_ifdetach(ifp); 668 669 bus_generic_detach(dev); 670 device_delete_child(dev, sc->lge_miibus); 671 672 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 673 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 674 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 675 676 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 677 lge_free_jumbo_mem(sc); 678 679 splx(s); 680 681 return(0); 682} 683 684/* 685 * Initialize the transmit descriptors. 686 */ 687static int 688lge_list_tx_init(sc) 689 struct lge_softc *sc; 690{ 691 struct lge_list_data *ld; 692 struct lge_ring_data *cd; 693 int i; 694 695 cd = &sc->lge_cdata; 696 ld = sc->lge_ldata; 697 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 698 ld->lge_tx_list[i].lge_mbuf = NULL; 699 ld->lge_tx_list[i].lge_ctl = 0; 700 } 701 702 cd->lge_tx_prod = cd->lge_tx_cons = 0; 703 704 return(0); 705} 706 707 708/* 709 * Initialize the RX descriptors and allocate mbufs for them. Note that 710 * we arralge the descriptors in a closed ring, so that the last descriptor 711 * points back to the first. 712 */ 713static int 714lge_list_rx_init(sc) 715 struct lge_softc *sc; 716{ 717 struct lge_list_data *ld; 718 struct lge_ring_data *cd; 719 int i; 720 721 ld = sc->lge_ldata; 722 cd = &sc->lge_cdata; 723 724 cd->lge_rx_prod = cd->lge_rx_cons = 0; 725 726 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 727 728 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 729 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 730 break; 731 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 732 return(ENOBUFS); 733 } 734 735 /* Clear possible 'rx command queue empty' interrupt. */ 736 CSR_READ_4(sc, LGE_ISR); 737 738 return(0); 739} 740 741/* 742 * Initialize an RX descriptor and attach an MBUF cluster. 743 */ 744static int 745lge_newbuf(sc, c, m) 746 struct lge_softc *sc; 747 struct lge_rx_desc *c; 748 struct mbuf *m; 749{ 750 struct mbuf *m_new = NULL; 751 caddr_t *buf = NULL; 752 753 if (m == NULL) { 754 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 755 if (m_new == NULL) { 756 printf("lge%d: no memory for rx list " 757 "-- packet dropped!\n", sc->lge_unit); 758 return(ENOBUFS); 759 } 760 761 /* Allocate the jumbo buffer */ 762 buf = lge_jalloc(sc); 763 if (buf == NULL) { 764#ifdef LGE_VERBOSE 765 printf("lge%d: jumbo allocation failed " 766 "-- packet dropped!\n", sc->lge_unit); 767#endif 768 m_freem(m_new); 769 return(ENOBUFS); 770 } 771 /* Attach the buffer to the mbuf */ 772 m_new->m_data = (void *)buf; 773 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 774 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 775 (struct lge_softc *)sc, 0, EXT_NET_DRV); 776 } else { 777 m_new = m; 778 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 779 m_new->m_data = m_new->m_ext.ext_buf; 780 } 781 782 /* 783 * Adjust alignment so packet payload begins on a 784 * longword boundary. Mandatory for Alpha, useful on 785 * x86 too. 786 */ 787 m_adj(m_new, ETHER_ALIGN); 788 789 c->lge_mbuf = m_new; 790 c->lge_fragptr_hi = 0; 791 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 792 c->lge_fraglen = m_new->m_len; 793 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 794 c->lge_sts = 0; 795 796 /* 797 * Put this buffer in the RX command FIFO. To do this, 798 * we just write the physical address of the descriptor 799 * into the RX descriptor address registers. Note that 800 * there are two registers, one high DWORD and one low 801 * DWORD, which lets us specify a 64-bit address if 802 * desired. We only use a 32-bit address for now. 803 * Writing to the low DWORD register is what actually 804 * causes the command to be issued, so we do that 805 * last. 806 */ 807 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 808 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 809 810 return(0); 811} 812 813static int 814lge_alloc_jumbo_mem(sc) 815 struct lge_softc *sc; 816{ 817 caddr_t ptr; 818 register int i; 819 struct lge_jpool_entry *entry; 820 821 /* Grab a big chunk o' storage. */ 822 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 823 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 824 825 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 826 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 827 return(ENOBUFS); 828 } 829 830 SLIST_INIT(&sc->lge_jfree_listhead); 831 SLIST_INIT(&sc->lge_jinuse_listhead); 832 833 /* 834 * Now divide it up into 9K pieces and save the addresses 835 * in an array. 836 */ 837 ptr = sc->lge_cdata.lge_jumbo_buf; 838 for (i = 0; i < LGE_JSLOTS; i++) { 839 sc->lge_cdata.lge_jslots[i] = ptr; 840 ptr += LGE_JLEN; 841 entry = malloc(sizeof(struct lge_jpool_entry), 842 M_DEVBUF, M_NOWAIT); 843 if (entry == NULL) { 844 printf("lge%d: no memory for jumbo " 845 "buffer queue!\n", sc->lge_unit); 846 return(ENOBUFS); 847 } 848 entry->slot = i; 849 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 850 entry, jpool_entries); 851 } 852 853 return(0); 854} 855 856static void 857lge_free_jumbo_mem(sc) 858 struct lge_softc *sc; 859{ 860 int i; 861 struct lge_jpool_entry *entry; 862 863 for (i = 0; i < LGE_JSLOTS; i++) { 864 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 865 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 866 free(entry, M_DEVBUF); 867 } 868 869 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 870 871 return; 872} 873 874/* 875 * Allocate a jumbo buffer. 876 */ 877static void * 878lge_jalloc(sc) 879 struct lge_softc *sc; 880{ 881 struct lge_jpool_entry *entry; 882 883 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 884 885 if (entry == NULL) { 886#ifdef LGE_VERBOSE 887 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 888#endif 889 return(NULL); 890 } 891 892 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 893 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 894 return(sc->lge_cdata.lge_jslots[entry->slot]); 895} 896 897/* 898 * Release a jumbo buffer. 899 */ 900static void 901lge_jfree(buf, args) 902 void *buf; 903 void *args; 904{ 905 struct lge_softc *sc; 906 int i; 907 struct lge_jpool_entry *entry; 908 909 /* Extract the softc struct pointer. */ 910 sc = args; 911 912 if (sc == NULL) 913 panic("lge_jfree: can't find softc pointer!"); 914 915 /* calculate the slot this buffer belongs to */ 916 i = ((vm_offset_t)buf 917 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 918 919 if ((i < 0) || (i >= LGE_JSLOTS)) 920 panic("lge_jfree: asked to free buffer that we don't manage!"); 921 922 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 923 if (entry == NULL) 924 panic("lge_jfree: buffer not in use!"); 925 entry->slot = i; 926 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 927 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 928 929 return; 930} 931 932/* 933 * A frame has been uploaded: pass the resulting mbuf chain up to 934 * the higher level protocols. 935 */ 936static void 937lge_rxeof(sc, cnt) 938 struct lge_softc *sc; 939 int cnt; 940{ 941 struct mbuf *m; 942 struct ifnet *ifp; 943 struct lge_rx_desc *cur_rx; 944 int c, i, total_len = 0; 945 u_int32_t rxsts, rxctl; 946 947 ifp = &sc->arpcom.ac_if; 948 949 /* Find out how many frames were processed. */ 950 c = cnt; 951 i = sc->lge_cdata.lge_rx_cons; 952 953 /* Suck them in. */ 954 while(c) { 955 struct mbuf *m0 = NULL; 956 957 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 958 rxctl = cur_rx->lge_ctl; 959 rxsts = cur_rx->lge_sts; 960 m = cur_rx->lge_mbuf; 961 cur_rx->lge_mbuf = NULL; 962 total_len = LGE_RXBYTES(cur_rx); 963 LGE_INC(i, LGE_RX_LIST_CNT); 964 c--; 965 966 /* 967 * If an error occurs, update stats, clear the 968 * status word and leave the mbuf cluster in place: 969 * it should simply get re-used next time this descriptor 970 * comes up in the ring. 971 */ 972 if (rxctl & LGE_RXCTL_ERRMASK) { 973 ifp->if_ierrors++; 974 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 975 continue; 976 } 977 978 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 979 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 980 ifp, NULL); 981 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 982 if (m0 == NULL) { 983 printf("lge%d: no receive buffers " 984 "available -- packet dropped!\n", 985 sc->lge_unit); 986 ifp->if_ierrors++; 987 continue; 988 } 989 m = m0; 990 } else { 991 m->m_pkthdr.rcvif = ifp; 992 m->m_pkthdr.len = m->m_len = total_len; 993 } 994 995 ifp->if_ipackets++; 996 997 /* Do IP checksum checking. */ 998 if (rxsts & LGE_RXSTS_ISIP) 999 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1000 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1001 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1002 if ((rxsts & LGE_RXSTS_ISTCP && 1003 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1004 (rxsts & LGE_RXSTS_ISUDP && 1005 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1006 m->m_pkthdr.csum_flags |= 1007 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1008 m->m_pkthdr.csum_data = 0xffff; 1009 } 1010 1011 (*ifp->if_input)(ifp, m); 1012 } 1013 1014 sc->lge_cdata.lge_rx_cons = i; 1015 1016 return; 1017} 1018 1019static void 1020lge_rxeoc(sc) 1021 struct lge_softc *sc; 1022{ 1023 struct ifnet *ifp; 1024 1025 ifp = &sc->arpcom.ac_if; 1026 ifp->if_flags &= ~IFF_RUNNING; 1027 lge_init(sc); 1028 return; 1029} 1030 1031/* 1032 * A frame was downloaded to the chip. It's safe for us to clean up 1033 * the list buffers. 1034 */ 1035 1036static void 1037lge_txeof(sc) 1038 struct lge_softc *sc; 1039{ 1040 struct lge_tx_desc *cur_tx = NULL; 1041 struct ifnet *ifp; 1042 u_int32_t idx, txdone; 1043 1044 ifp = &sc->arpcom.ac_if; 1045 1046 /* Clear the timeout timer. */ 1047 ifp->if_timer = 0; 1048 1049 /* 1050 * Go through our tx list and free mbufs for those 1051 * frames that have been transmitted. 1052 */ 1053 idx = sc->lge_cdata.lge_tx_cons; 1054 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1055 1056 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1057 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1058 1059 ifp->if_opackets++; 1060 if (cur_tx->lge_mbuf != NULL) { 1061 m_freem(cur_tx->lge_mbuf); 1062 cur_tx->lge_mbuf = NULL; 1063 } 1064 cur_tx->lge_ctl = 0; 1065 1066 txdone--; 1067 LGE_INC(idx, LGE_TX_LIST_CNT); 1068 ifp->if_timer = 0; 1069 } 1070 1071 sc->lge_cdata.lge_tx_cons = idx; 1072 1073 if (cur_tx != NULL) 1074 ifp->if_flags &= ~IFF_OACTIVE; 1075 1076 return; 1077} 1078 1079static void 1080lge_tick(xsc) 1081 void *xsc; 1082{ 1083 struct lge_softc *sc; 1084 struct mii_data *mii; 1085 struct ifnet *ifp; 1086 int s; 1087 1088 s = splimp(); 1089 1090 sc = xsc; 1091 ifp = &sc->arpcom.ac_if; 1092 1093 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1094 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1095 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1096 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1097 1098 if (!sc->lge_link) { 1099 mii = device_get_softc(sc->lge_miibus); 1100 mii_tick(mii); 1101 if (mii->mii_media_status & IFM_ACTIVE && 1102 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1103 sc->lge_link++; 1104 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1105 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1106 printf("lge%d: gigabit link up\n", 1107 sc->lge_unit); 1108 if (ifp->if_snd.ifq_head != NULL) 1109 lge_start(ifp); 1110 } 1111 } 1112 1113 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1114 1115 splx(s); 1116 1117 return; 1118} 1119 1120static void 1121lge_intr(arg) 1122 void *arg; 1123{ 1124 struct lge_softc *sc; 1125 struct ifnet *ifp; 1126 u_int32_t status; 1127 1128 sc = arg; 1129 ifp = &sc->arpcom.ac_if; 1130 1131 /* Supress unwanted interrupts */ 1132 if (!(ifp->if_flags & IFF_UP)) { 1133 lge_stop(sc); 1134 return; 1135 } 1136 1137 for (;;) { 1138 /* 1139 * Reading the ISR register clears all interrupts, and 1140 * clears the 'interrupts enabled' bit in the IMR 1141 * register. 1142 */ 1143 status = CSR_READ_4(sc, LGE_ISR); 1144 1145 if ((status & LGE_INTRS) == 0) 1146 break; 1147 1148 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1149 lge_txeof(sc); 1150 1151 if (status & LGE_ISR_RXDMA_DONE) 1152 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1153 1154 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1155 lge_rxeoc(sc); 1156 1157 if (status & LGE_ISR_PHY_INTR) { 1158 sc->lge_link = 0; 1159 untimeout(lge_tick, sc, sc->lge_stat_ch); 1160 lge_tick(sc); 1161 } 1162 } 1163 1164 /* Re-enable interrupts. */ 1165 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1166 1167 if (ifp->if_snd.ifq_head != NULL) 1168 lge_start(ifp); 1169 1170 return; 1171} 1172 1173/* 1174 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1175 * pointers to the fragment pointers. 1176 */ 1177static int 1178lge_encap(sc, m_head, txidx) 1179 struct lge_softc *sc; 1180 struct mbuf *m_head; 1181 u_int32_t *txidx; 1182{ 1183 struct lge_frag *f = NULL; 1184 struct lge_tx_desc *cur_tx; 1185 struct mbuf *m; 1186 int frag = 0, tot_len = 0; 1187 1188 /* 1189 * Start packing the mbufs in this chain into 1190 * the fragment pointers. Stop when we run out 1191 * of fragments or hit the end of the mbuf chain. 1192 */ 1193 m = m_head; 1194 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1195 frag = 0; 1196 1197 for (m = m_head; m != NULL; m = m->m_next) { 1198 if (m->m_len != 0) { 1199 tot_len += m->m_len; 1200 f = &cur_tx->lge_frags[frag]; 1201 f->lge_fraglen = m->m_len; 1202 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1203 f->lge_fragptr_hi = 0; 1204 frag++; 1205 } 1206 } 1207 1208 if (m != NULL) 1209 return(ENOBUFS); 1210 1211 cur_tx->lge_mbuf = m_head; 1212 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1213 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1214 1215 /* Queue for transmit */ 1216 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1217 1218 return(0); 1219} 1220 1221/* 1222 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1223 * to the mbuf data regions directly in the transmit lists. We also save a 1224 * copy of the pointers since the transmit list fragment pointers are 1225 * physical addresses. 1226 */ 1227 1228static void 1229lge_start(ifp) 1230 struct ifnet *ifp; 1231{ 1232 struct lge_softc *sc; 1233 struct mbuf *m_head = NULL; 1234 u_int32_t idx; 1235 1236 sc = ifp->if_softc; 1237 1238 if (!sc->lge_link) 1239 return; 1240 1241 idx = sc->lge_cdata.lge_tx_prod; 1242 1243 if (ifp->if_flags & IFF_OACTIVE) 1244 return; 1245 1246 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1247 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1248 break; 1249 1250 IF_DEQUEUE(&ifp->if_snd, m_head); 1251 if (m_head == NULL) 1252 break; 1253 1254 if (lge_encap(sc, m_head, &idx)) { 1255 IF_PREPEND(&ifp->if_snd, m_head); 1256 ifp->if_flags |= IFF_OACTIVE; 1257 break; 1258 } 1259 1260 /* 1261 * If there's a BPF listener, bounce a copy of this frame 1262 * to him. 1263 */ 1264 BPF_MTAP(ifp, m_head); 1265 } 1266 1267 sc->lge_cdata.lge_tx_prod = idx; 1268 1269 /* 1270 * Set a timeout in case the chip goes out to lunch. 1271 */ 1272 ifp->if_timer = 5; 1273 1274 return; 1275} 1276 1277static void 1278lge_init(xsc) 1279 void *xsc; 1280{ 1281 struct lge_softc *sc = xsc; 1282 struct ifnet *ifp = &sc->arpcom.ac_if; 1283 struct mii_data *mii; 1284 int s; 1285 1286 if (ifp->if_flags & IFF_RUNNING) 1287 return; 1288 1289 s = splimp(); 1290 1291 /* 1292 * Cancel pending I/O and free all RX/TX buffers. 1293 */ 1294 lge_stop(sc); 1295 lge_reset(sc); 1296 1297 mii = device_get_softc(sc->lge_miibus); 1298 1299 /* Set MAC address */ 1300 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1301 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1302 1303 /* Init circular RX list. */ 1304 if (lge_list_rx_init(sc) == ENOBUFS) { 1305 printf("lge%d: initialization failed: no " 1306 "memory for rx buffers\n", sc->lge_unit); 1307 lge_stop(sc); 1308 (void)splx(s); 1309 return; 1310 } 1311 1312 /* 1313 * Init tx descriptors. 1314 */ 1315 lge_list_tx_init(sc); 1316 1317 /* Set initial value for MODE1 register. */ 1318 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1319 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1320 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1321 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1322 1323 /* If we want promiscuous mode, set the allframes bit. */ 1324 if (ifp->if_flags & IFF_PROMISC) { 1325 CSR_WRITE_4(sc, LGE_MODE1, 1326 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1327 } else { 1328 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1329 } 1330 1331 /* 1332 * Set the capture broadcast bit to capture broadcast frames. 1333 */ 1334 if (ifp->if_flags & IFF_BROADCAST) { 1335 CSR_WRITE_4(sc, LGE_MODE1, 1336 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1337 } else { 1338 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1339 } 1340 1341 /* Packet padding workaround? */ 1342 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1343 1344 /* No error frames */ 1345 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1346 1347 /* Receive large frames */ 1348 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1349 1350 /* Workaround: disable RX/TX flow control */ 1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1352 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1353 1354 /* Make sure to strip CRC from received frames */ 1355 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1356 1357 /* Turn off magic packet mode */ 1358 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1359 1360 /* Turn off all VLAN stuff */ 1361 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1362 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1363 1364 /* Workarond: FIFO overflow */ 1365 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1366 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1367 1368 /* 1369 * Load the multicast filter. 1370 */ 1371 lge_setmulti(sc); 1372 1373 /* 1374 * Enable hardware checksum validation for all received IPv4 1375 * packets, do not reject packets with bad checksums. 1376 */ 1377 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1378 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1379 LGE_MODE2_RX_ERRCSUM); 1380 1381 /* 1382 * Enable the delivery of PHY interrupts based on 1383 * link/speed/duplex status chalges. 1384 */ 1385 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1386 1387 /* Enable receiver and transmitter. */ 1388 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1389 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1390 1391 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1392 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1393 1394 /* 1395 * Enable interrupts. 1396 */ 1397 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1398 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1399 1400 lge_ifmedia_upd(ifp); 1401 1402 ifp->if_flags |= IFF_RUNNING; 1403 ifp->if_flags &= ~IFF_OACTIVE; 1404 1405 (void)splx(s); 1406 1407 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1408 1409 return; 1410} 1411 1412/* 1413 * Set media options. 1414 */ 1415static int 1416lge_ifmedia_upd(ifp) 1417 struct ifnet *ifp; 1418{ 1419 struct lge_softc *sc; 1420 struct mii_data *mii; 1421 1422 sc = ifp->if_softc; 1423 1424 mii = device_get_softc(sc->lge_miibus); 1425 sc->lge_link = 0; 1426 if (mii->mii_instance) { 1427 struct mii_softc *miisc; 1428 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1429 miisc = LIST_NEXT(miisc, mii_list)) 1430 mii_phy_reset(miisc); 1431 } 1432 mii_mediachg(mii); 1433 1434 return(0); 1435} 1436 1437/* 1438 * Report current media status. 1439 */ 1440static void 1441lge_ifmedia_sts(ifp, ifmr) 1442 struct ifnet *ifp; 1443 struct ifmediareq *ifmr; 1444{ 1445 struct lge_softc *sc; 1446 struct mii_data *mii; 1447 1448 sc = ifp->if_softc; 1449 1450 mii = device_get_softc(sc->lge_miibus); 1451 mii_pollstat(mii); 1452 ifmr->ifm_active = mii->mii_media_active; 1453 ifmr->ifm_status = mii->mii_media_status; 1454 1455 return; 1456} 1457 1458static int 1459lge_ioctl(ifp, command, data) 1460 struct ifnet *ifp; 1461 u_long command; 1462 caddr_t data; 1463{ 1464 struct lge_softc *sc = ifp->if_softc; 1465 struct ifreq *ifr = (struct ifreq *) data; 1466 struct mii_data *mii; 1467 int s, error = 0; 1468 1469 s = splimp(); 1470 1471 switch(command) { 1472 case SIOCSIFMTU: 1473 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1474 error = EINVAL; 1475 else 1476 ifp->if_mtu = ifr->ifr_mtu; 1477 break; 1478 case SIOCSIFFLAGS: 1479 if (ifp->if_flags & IFF_UP) { 1480 if (ifp->if_flags & IFF_RUNNING && 1481 ifp->if_flags & IFF_PROMISC && 1482 !(sc->lge_if_flags & IFF_PROMISC)) { 1483 CSR_WRITE_4(sc, LGE_MODE1, 1484 LGE_MODE1_SETRST_CTL1| 1485 LGE_MODE1_RX_PROMISC); 1486 } else if (ifp->if_flags & IFF_RUNNING && 1487 !(ifp->if_flags & IFF_PROMISC) && 1488 sc->lge_if_flags & IFF_PROMISC) { 1489 CSR_WRITE_4(sc, LGE_MODE1, 1490 LGE_MODE1_RX_PROMISC); 1491 } else { 1492 ifp->if_flags &= ~IFF_RUNNING; 1493 lge_init(sc); 1494 } 1495 } else { 1496 if (ifp->if_flags & IFF_RUNNING) 1497 lge_stop(sc); 1498 } 1499 sc->lge_if_flags = ifp->if_flags; 1500 error = 0; 1501 break; 1502 case SIOCADDMULTI: 1503 case SIOCDELMULTI: 1504 lge_setmulti(sc); 1505 error = 0; 1506 break; 1507 case SIOCGIFMEDIA: 1508 case SIOCSIFMEDIA: 1509 mii = device_get_softc(sc->lge_miibus); 1510 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1511 break; 1512 default: 1513 error = ether_ioctl(ifp, command, data); 1514 break; 1515 } 1516 1517 (void)splx(s); 1518 1519 return(error); 1520} 1521 1522static void 1523lge_watchdog(ifp) 1524 struct ifnet *ifp; 1525{ 1526 struct lge_softc *sc; 1527 1528 sc = ifp->if_softc; 1529 1530 ifp->if_oerrors++; 1531 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1532 1533 lge_stop(sc); 1534 lge_reset(sc); 1535 ifp->if_flags &= ~IFF_RUNNING; 1536 lge_init(sc); 1537 1538 if (ifp->if_snd.ifq_head != NULL) 1539 lge_start(ifp); 1540 1541 return; 1542} 1543 1544/* 1545 * Stop the adapter and free any mbufs allocated to the 1546 * RX and TX lists. 1547 */ 1548static void 1549lge_stop(sc) 1550 struct lge_softc *sc; 1551{ 1552 register int i; 1553 struct ifnet *ifp; 1554 1555 ifp = &sc->arpcom.ac_if; 1556 ifp->if_timer = 0; 1557 untimeout(lge_tick, sc, sc->lge_stat_ch); 1558 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1559 1560 /* Disable receiver and transmitter. */ 1561 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1562 sc->lge_link = 0; 1563 1564 /* 1565 * Free data in the RX lists. 1566 */ 1567 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1568 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1569 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1570 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1571 } 1572 } 1573 bzero((char *)&sc->lge_ldata->lge_rx_list, 1574 sizeof(sc->lge_ldata->lge_rx_list)); 1575 1576 /* 1577 * Free the TX list buffers. 1578 */ 1579 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1580 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1581 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1582 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1583 } 1584 } 1585 1586 bzero((char *)&sc->lge_ldata->lge_tx_list, 1587 sizeof(sc->lge_ldata->lge_tx_list)); 1588 1589 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1590 1591 return; 1592} 1593 1594/* 1595 * Stop all chip I/O so that the kernel's probe routines don't 1596 * get confused by errant DMAs when rebooting. 1597 */ 1598static void 1599lge_shutdown(dev) 1600 device_t dev; 1601{ 1602 struct lge_softc *sc; 1603 1604 sc = device_get_softc(dev); 1605 1606 lge_reset(sc); 1607 lge_stop(sc); 1608 1609 return; 1610} 1611