if_lge.c revision 119418
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 119418 2003-08-24 17:55:58Z obrien $"); 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72#include <sys/cdefs.h> 73__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 119418 2003-08-24 17:55:58Z obrien $"); 74 75#include <sys/param.h> 76#include <sys/systm.h> 77#include <sys/sockio.h> 78#include <sys/mbuf.h> 79#include <sys/malloc.h> 80#include <sys/kernel.h> 81#include <sys/socket.h> 82 83#include <net/if.h> 84#include <net/if_arp.h> 85#include <net/ethernet.h> 86#include <net/if_dl.h> 87#include <net/if_media.h> 88 89#include <net/bpf.h> 90 91#include <vm/vm.h> /* for vtophys */ 92#include <vm/pmap.h> /* for vtophys */ 93#include <machine/clock.h> /* for DELAY */ 94#include <machine/bus_pio.h> 95#include <machine/bus_memio.h> 96#include <machine/bus.h> 97#include <machine/resource.h> 98#include <sys/bus.h> 99#include <sys/rman.h> 100 101#include <dev/mii/mii.h> 102#include <dev/mii/miivar.h> 103 104#include <dev/pci/pcireg.h> 105#include <dev/pci/pcivar.h> 106 107#define LGE_USEIOSPACE 108 109#include <dev/lge/if_lgereg.h> 110 111/* "controller miibus0" required. See GENERIC if you get errors here. */ 112#include "miibus_if.h" 113 114/* 115 * Various supported device vendors/types and their names. 116 */ 117static struct lge_type lge_devs[] = { 118 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 119 { 0, 0, NULL } 120}; 121 122static int lge_probe(device_t); 123static int lge_attach(device_t); 124static int lge_detach(device_t); 125 126static int lge_alloc_jumbo_mem(struct lge_softc *); 127static void lge_free_jumbo_mem(struct lge_softc *); 128static void *lge_jalloc(struct lge_softc *); 129static void lge_jfree(void *, void *); 130 131static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 132static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 133static void lge_rxeof(struct lge_softc *, int); 134static void lge_rxeoc(struct lge_softc *); 135static void lge_txeof(struct lge_softc *); 136static void lge_intr(void *); 137static void lge_tick(void *); 138static void lge_start(struct ifnet *); 139static int lge_ioctl(struct ifnet *, u_long, caddr_t); 140static void lge_init(void *); 141static void lge_stop(struct lge_softc *); 142static void lge_watchdog(struct ifnet *); 143static void lge_shutdown(device_t); 144static int lge_ifmedia_upd(struct ifnet *); 145static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 148static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 149 150static int lge_miibus_readreg(device_t, int, int); 151static int lge_miibus_writereg(device_t, int, int, int); 152static void lge_miibus_statchg(device_t); 153 154static void lge_setmulti(struct lge_softc *); 155static u_int32_t lge_crc(struct lge_softc *, caddr_t); 156static void lge_reset(struct lge_softc *); 157static int lge_list_rx_init(struct lge_softc *); 158static int lge_list_tx_init(struct lge_softc *); 159 160#ifdef LGE_USEIOSPACE 161#define LGE_RES SYS_RES_IOPORT 162#define LGE_RID LGE_PCI_LOIO 163#else 164#define LGE_RES SYS_RES_MEMORY 165#define LGE_RID LGE_PCI_LOMEM 166#endif 167 168static device_method_t lge_methods[] = { 169 /* Device interface */ 170 DEVMETHOD(device_probe, lge_probe), 171 DEVMETHOD(device_attach, lge_attach), 172 DEVMETHOD(device_detach, lge_detach), 173 DEVMETHOD(device_shutdown, lge_shutdown), 174 175 /* bus interface */ 176 DEVMETHOD(bus_print_child, bus_generic_print_child), 177 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 178 179 /* MII interface */ 180 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 181 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 182 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 183 184 { 0, 0 } 185}; 186 187static driver_t lge_driver = { 188 "lge", 189 lge_methods, 190 sizeof(struct lge_softc) 191}; 192 193static devclass_t lge_devclass; 194 195DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 196DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 197MODULE_DEPEND(lge, pci, 1, 1, 1); 198MODULE_DEPEND(lge, ether, 1, 1, 1); 199MODULE_DEPEND(lge, miibus, 1, 1, 1); 200 201#define LGE_SETBIT(sc, reg, x) \ 202 CSR_WRITE_4(sc, reg, \ 203 CSR_READ_4(sc, reg) | (x)) 204 205#define LGE_CLRBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, \ 207 CSR_READ_4(sc, reg) & ~(x)) 208 209#define SIO_SET(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 211 212#define SIO_CLR(x) \ 213 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 214 215/* 216 * Read a word of data stored in the EEPROM at address 'addr.' 217 */ 218static void 219lge_eeprom_getword(sc, addr, dest) 220 struct lge_softc *sc; 221 int addr; 222 u_int16_t *dest; 223{ 224 register int i; 225 u_int32_t val; 226 227 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 228 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 229 230 for (i = 0; i < LGE_TIMEOUT; i++) 231 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 232 break; 233 234 if (i == LGE_TIMEOUT) { 235 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 236 return; 237 } 238 239 val = CSR_READ_4(sc, LGE_EEDATA); 240 241 if (addr & 1) 242 *dest = (val >> 16) & 0xFFFF; 243 else 244 *dest = val & 0xFFFF; 245 246 return; 247} 248 249/* 250 * Read a sequence of words from the EEPROM. 251 */ 252static void 253lge_read_eeprom(sc, dest, off, cnt, swap) 254 struct lge_softc *sc; 255 caddr_t dest; 256 int off; 257 int cnt; 258 int swap; 259{ 260 int i; 261 u_int16_t word = 0, *ptr; 262 263 for (i = 0; i < cnt; i++) { 264 lge_eeprom_getword(sc, off + i, &word); 265 ptr = (u_int16_t *)(dest + (i * 2)); 266 if (swap) 267 *ptr = ntohs(word); 268 else 269 *ptr = word; 270 } 271 272 return; 273} 274 275static int 276lge_miibus_readreg(dev, phy, reg) 277 device_t dev; 278 int phy, reg; 279{ 280 struct lge_softc *sc; 281 int i; 282 283 sc = device_get_softc(dev); 284 285 /* 286 * If we have a non-PCS PHY, pretend that the internal 287 * autoneg stuff at PHY address 0 isn't there so that 288 * the miibus code will find only the GMII PHY. 289 */ 290 if (sc->lge_pcs == 0 && phy == 0) 291 return(0); 292 293 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 294 295 for (i = 0; i < LGE_TIMEOUT; i++) 296 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 297 break; 298 299 if (i == LGE_TIMEOUT) { 300 printf("lge%d: PHY read timed out\n", sc->lge_unit); 301 return(0); 302 } 303 304 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 305} 306 307static int 308lge_miibus_writereg(dev, phy, reg, data) 309 device_t dev; 310 int phy, reg, data; 311{ 312 struct lge_softc *sc; 313 int i; 314 315 sc = device_get_softc(dev); 316 317 CSR_WRITE_4(sc, LGE_GMIICTL, 318 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 319 320 for (i = 0; i < LGE_TIMEOUT; i++) 321 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 322 break; 323 324 if (i == LGE_TIMEOUT) { 325 printf("lge%d: PHY write timed out\n", sc->lge_unit); 326 return(0); 327 } 328 329 return(0); 330} 331 332static void 333lge_miibus_statchg(dev) 334 device_t dev; 335{ 336 struct lge_softc *sc; 337 struct mii_data *mii; 338 339 sc = device_get_softc(dev); 340 mii = device_get_softc(sc->lge_miibus); 341 342 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 343 switch (IFM_SUBTYPE(mii->mii_media_active)) { 344 case IFM_1000_T: 345 case IFM_1000_SX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 347 break; 348 case IFM_100_TX: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 350 break; 351 case IFM_10_T: 352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 353 break; 354 default: 355 /* 356 * Choose something, even if it's wrong. Clearing 357 * all the bits will hose autoneg on the internal 358 * PHY. 359 */ 360 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 361 break; 362 } 363 364 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 365 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 366 } else { 367 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 368 } 369 370 return; 371} 372 373static u_int32_t 374lge_crc(sc, addr) 375 struct lge_softc *sc; 376 caddr_t addr; 377{ 378 u_int32_t crc, carry; 379 int i, j; 380 u_int8_t c; 381 382 /* Compute CRC for the address value. */ 383 crc = 0xFFFFFFFF; /* initial value */ 384 385 for (i = 0; i < 6; i++) { 386 c = *(addr + i); 387 for (j = 0; j < 8; j++) { 388 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 389 crc <<= 1; 390 c >>= 1; 391 if (carry) 392 crc = (crc ^ 0x04c11db6) | carry; 393 } 394 } 395 396 /* 397 * return the filter bit position 398 */ 399 return((crc >> 26) & 0x0000003F); 400} 401 402static void 403lge_setmulti(sc) 404 struct lge_softc *sc; 405{ 406 struct ifnet *ifp; 407 struct ifmultiaddr *ifma; 408 u_int32_t h = 0, hashes[2] = { 0, 0 }; 409 410 ifp = &sc->arpcom.ac_if; 411 412 /* Make sure multicast hash table is enabled. */ 413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 414 415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 418 return; 419 } 420 421 /* first, zot all the existing hash bits */ 422 CSR_WRITE_4(sc, LGE_MAR0, 0); 423 CSR_WRITE_4(sc, LGE_MAR1, 0); 424 425 /* now program new ones */ 426 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 427 if (ifma->ifma_addr->sa_family != AF_LINK) 428 continue; 429 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 430 if (h < 32) 431 hashes[0] |= (1 << h); 432 else 433 hashes[1] |= (1 << (h - 32)); 434 } 435 436 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 437 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 438 439 return; 440} 441 442static void 443lge_reset(sc) 444 struct lge_softc *sc; 445{ 446 register int i; 447 448 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 449 450 for (i = 0; i < LGE_TIMEOUT; i++) { 451 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 452 break; 453 } 454 455 if (i == LGE_TIMEOUT) 456 printf("lge%d: reset never completed\n", sc->lge_unit); 457 458 /* Wait a little while for the chip to get its brains in order. */ 459 DELAY(1000); 460 461 return; 462} 463 464/* 465 * Probe for a Level 1 chip. Check the PCI vendor and device 466 * IDs against our list and return a device name if we find a match. 467 */ 468static int 469lge_probe(dev) 470 device_t dev; 471{ 472 struct lge_type *t; 473 474 t = lge_devs; 475 476 while(t->lge_name != NULL) { 477 if ((pci_get_vendor(dev) == t->lge_vid) && 478 (pci_get_device(dev) == t->lge_did)) { 479 device_set_desc(dev, t->lge_name); 480 return(0); 481 } 482 t++; 483 } 484 485 return(ENXIO); 486} 487 488/* 489 * Attach the interface. Allocate softc structures, do ifmedia 490 * setup and ethernet/BPF attach. 491 */ 492static int 493lge_attach(dev) 494 device_t dev; 495{ 496 int s; 497 u_char eaddr[ETHER_ADDR_LEN]; 498 struct lge_softc *sc; 499 struct ifnet *ifp; 500 int unit, error = 0, rid; 501 502 s = splimp(); 503 504 sc = device_get_softc(dev); 505 unit = device_get_unit(dev); 506 bzero(sc, sizeof(struct lge_softc)); 507#ifndef BURN_BRIDGES 508 /* 509 * Handle power management nonsense. 510 */ 511 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 512 u_int32_t iobase, membase, irq; 513 514 /* Save important PCI config data. */ 515 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 516 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 517 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 518 519 /* Reset the power state. */ 520 printf("lge%d: chip is in D%d power mode " 521 "-- setting to D0\n", unit, 522 pci_get_powerstate(dev)); 523 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 524 525 /* Restore PCI config data. */ 526 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 527 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 528 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 529 } 530#endif 531 /* 532 * Map control/status registers. 533 */ 534 pci_enable_busmaster(dev); 535 536 rid = LGE_RID; 537 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 538 0, ~0, 1, RF_ACTIVE); 539 540 if (sc->lge_res == NULL) { 541 printf("lge%d: couldn't map ports/memory\n", unit); 542 error = ENXIO; 543 goto fail; 544 } 545 546 sc->lge_btag = rman_get_bustag(sc->lge_res); 547 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 548 549 /* Allocate interrupt */ 550 rid = 0; 551 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 552 RF_SHAREABLE | RF_ACTIVE); 553 554 if (sc->lge_irq == NULL) { 555 printf("lge%d: couldn't map interrupt\n", unit); 556 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 557 error = ENXIO; 558 goto fail; 559 } 560 561 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 562 lge_intr, sc, &sc->lge_intrhand); 563 564 if (error) { 565 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 566 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 567 printf("lge%d: couldn't set up irq\n", unit); 568 goto fail; 569 } 570 571 /* Reset the adapter. */ 572 lge_reset(sc); 573 574 /* 575 * Get station address from the EEPROM. 576 */ 577 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 578 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 579 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 580 581 /* 582 * A Level 1 chip was detected. Inform the world. 583 */ 584 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 585 586 sc->lge_unit = unit; 587 callout_handle_init(&sc->lge_stat_ch); 588 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 589 590 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 591 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 592 593 if (sc->lge_ldata == NULL) { 594 printf("lge%d: no memory for list buffers!\n", unit); 595 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 596 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 597 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 598 error = ENXIO; 599 goto fail; 600 } 601 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 602 603 /* Try to allocate memory for jumbo buffers. */ 604 if (lge_alloc_jumbo_mem(sc)) { 605 printf("lge%d: jumbo buffer allocation failed\n", 606 sc->lge_unit); 607 contigfree(sc->lge_ldata, 608 sizeof(struct lge_list_data), M_DEVBUF); 609 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 610 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 611 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 612 error = ENXIO; 613 goto fail; 614 } 615 616 ifp = &sc->arpcom.ac_if; 617 ifp->if_softc = sc; 618 ifp->if_unit = unit; 619 ifp->if_name = "lge"; 620 ifp->if_mtu = ETHERMTU; 621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 622 ifp->if_ioctl = lge_ioctl; 623 ifp->if_output = ether_output; 624 ifp->if_start = lge_start; 625 ifp->if_watchdog = lge_watchdog; 626 ifp->if_init = lge_init; 627 ifp->if_baudrate = 1000000000; 628 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 629 ifp->if_capabilities = IFCAP_RXCSUM; 630 ifp->if_capenable = ifp->if_capabilities; 631 632 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 633 sc->lge_pcs = 1; 634 else 635 sc->lge_pcs = 0; 636 637 /* 638 * Do MII setup. 639 */ 640 if (mii_phy_probe(dev, &sc->lge_miibus, 641 lge_ifmedia_upd, lge_ifmedia_sts)) { 642 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 643 contigfree(sc->lge_ldata, 644 sizeof(struct lge_list_data), M_DEVBUF); 645 lge_free_jumbo_mem(sc); 646 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 647 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 648 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 649 error = ENXIO; 650 goto fail; 651 } 652 653 /* 654 * Call MI attach routine. 655 */ 656 ether_ifattach(ifp, eaddr); 657 callout_handle_init(&sc->lge_stat_ch); 658 659fail: 660 splx(s); 661 return(error); 662} 663 664static int 665lge_detach(dev) 666 device_t dev; 667{ 668 struct lge_softc *sc; 669 struct ifnet *ifp; 670 int s; 671 672 s = splimp(); 673 674 sc = device_get_softc(dev); 675 ifp = &sc->arpcom.ac_if; 676 677 lge_reset(sc); 678 lge_stop(sc); 679 ether_ifdetach(ifp); 680 681 bus_generic_detach(dev); 682 device_delete_child(dev, sc->lge_miibus); 683 684 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 685 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 686 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 687 688 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 689 lge_free_jumbo_mem(sc); 690 691 splx(s); 692 693 return(0); 694} 695 696/* 697 * Initialize the transmit descriptors. 698 */ 699static int 700lge_list_tx_init(sc) 701 struct lge_softc *sc; 702{ 703 struct lge_list_data *ld; 704 struct lge_ring_data *cd; 705 int i; 706 707 cd = &sc->lge_cdata; 708 ld = sc->lge_ldata; 709 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 710 ld->lge_tx_list[i].lge_mbuf = NULL; 711 ld->lge_tx_list[i].lge_ctl = 0; 712 } 713 714 cd->lge_tx_prod = cd->lge_tx_cons = 0; 715 716 return(0); 717} 718 719 720/* 721 * Initialize the RX descriptors and allocate mbufs for them. Note that 722 * we arralge the descriptors in a closed ring, so that the last descriptor 723 * points back to the first. 724 */ 725static int 726lge_list_rx_init(sc) 727 struct lge_softc *sc; 728{ 729 struct lge_list_data *ld; 730 struct lge_ring_data *cd; 731 int i; 732 733 ld = sc->lge_ldata; 734 cd = &sc->lge_cdata; 735 736 cd->lge_rx_prod = cd->lge_rx_cons = 0; 737 738 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 739 740 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 741 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 742 break; 743 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 744 return(ENOBUFS); 745 } 746 747 /* Clear possible 'rx command queue empty' interrupt. */ 748 CSR_READ_4(sc, LGE_ISR); 749 750 return(0); 751} 752 753/* 754 * Initialize an RX descriptor and attach an MBUF cluster. 755 */ 756static int 757lge_newbuf(sc, c, m) 758 struct lge_softc *sc; 759 struct lge_rx_desc *c; 760 struct mbuf *m; 761{ 762 struct mbuf *m_new = NULL; 763 caddr_t *buf = NULL; 764 765 if (m == NULL) { 766 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 767 if (m_new == NULL) { 768 printf("lge%d: no memory for rx list " 769 "-- packet dropped!\n", sc->lge_unit); 770 return(ENOBUFS); 771 } 772 773 /* Allocate the jumbo buffer */ 774 buf = lge_jalloc(sc); 775 if (buf == NULL) { 776#ifdef LGE_VERBOSE 777 printf("lge%d: jumbo allocation failed " 778 "-- packet dropped!\n", sc->lge_unit); 779#endif 780 m_freem(m_new); 781 return(ENOBUFS); 782 } 783 /* Attach the buffer to the mbuf */ 784 m_new->m_data = (void *)buf; 785 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 786 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 787 (struct lge_softc *)sc, 0, EXT_NET_DRV); 788 } else { 789 m_new = m; 790 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 791 m_new->m_data = m_new->m_ext.ext_buf; 792 } 793 794 /* 795 * Adjust alignment so packet payload begins on a 796 * longword boundary. Mandatory for Alpha, useful on 797 * x86 too. 798 */ 799 m_adj(m_new, ETHER_ALIGN); 800 801 c->lge_mbuf = m_new; 802 c->lge_fragptr_hi = 0; 803 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 804 c->lge_fraglen = m_new->m_len; 805 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 806 c->lge_sts = 0; 807 808 /* 809 * Put this buffer in the RX command FIFO. To do this, 810 * we just write the physical address of the descriptor 811 * into the RX descriptor address registers. Note that 812 * there are two registers, one high DWORD and one low 813 * DWORD, which lets us specify a 64-bit address if 814 * desired. We only use a 32-bit address for now. 815 * Writing to the low DWORD register is what actually 816 * causes the command to be issued, so we do that 817 * last. 818 */ 819 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 820 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 821 822 return(0); 823} 824 825static int 826lge_alloc_jumbo_mem(sc) 827 struct lge_softc *sc; 828{ 829 caddr_t ptr; 830 register int i; 831 struct lge_jpool_entry *entry; 832 833 /* Grab a big chunk o' storage. */ 834 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 835 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 836 837 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 838 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 839 return(ENOBUFS); 840 } 841 842 SLIST_INIT(&sc->lge_jfree_listhead); 843 SLIST_INIT(&sc->lge_jinuse_listhead); 844 845 /* 846 * Now divide it up into 9K pieces and save the addresses 847 * in an array. 848 */ 849 ptr = sc->lge_cdata.lge_jumbo_buf; 850 for (i = 0; i < LGE_JSLOTS; i++) { 851 sc->lge_cdata.lge_jslots[i] = ptr; 852 ptr += LGE_JLEN; 853 entry = malloc(sizeof(struct lge_jpool_entry), 854 M_DEVBUF, M_NOWAIT); 855 if (entry == NULL) { 856 printf("lge%d: no memory for jumbo " 857 "buffer queue!\n", sc->lge_unit); 858 return(ENOBUFS); 859 } 860 entry->slot = i; 861 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 862 entry, jpool_entries); 863 } 864 865 return(0); 866} 867 868static void 869lge_free_jumbo_mem(sc) 870 struct lge_softc *sc; 871{ 872 int i; 873 struct lge_jpool_entry *entry; 874 875 for (i = 0; i < LGE_JSLOTS; i++) { 876 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 877 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 878 free(entry, M_DEVBUF); 879 } 880 881 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 882 883 return; 884} 885 886/* 887 * Allocate a jumbo buffer. 888 */ 889static void * 890lge_jalloc(sc) 891 struct lge_softc *sc; 892{ 893 struct lge_jpool_entry *entry; 894 895 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 896 897 if (entry == NULL) { 898#ifdef LGE_VERBOSE 899 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 900#endif 901 return(NULL); 902 } 903 904 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 905 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 906 return(sc->lge_cdata.lge_jslots[entry->slot]); 907} 908 909/* 910 * Release a jumbo buffer. 911 */ 912static void 913lge_jfree(buf, args) 914 void *buf; 915 void *args; 916{ 917 struct lge_softc *sc; 918 int i; 919 struct lge_jpool_entry *entry; 920 921 /* Extract the softc struct pointer. */ 922 sc = args; 923 924 if (sc == NULL) 925 panic("lge_jfree: can't find softc pointer!"); 926 927 /* calculate the slot this buffer belongs to */ 928 i = ((vm_offset_t)buf 929 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 930 931 if ((i < 0) || (i >= LGE_JSLOTS)) 932 panic("lge_jfree: asked to free buffer that we don't manage!"); 933 934 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 935 if (entry == NULL) 936 panic("lge_jfree: buffer not in use!"); 937 entry->slot = i; 938 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 939 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 940 941 return; 942} 943 944/* 945 * A frame has been uploaded: pass the resulting mbuf chain up to 946 * the higher level protocols. 947 */ 948static void 949lge_rxeof(sc, cnt) 950 struct lge_softc *sc; 951 int cnt; 952{ 953 struct mbuf *m; 954 struct ifnet *ifp; 955 struct lge_rx_desc *cur_rx; 956 int c, i, total_len = 0; 957 u_int32_t rxsts, rxctl; 958 959 ifp = &sc->arpcom.ac_if; 960 961 /* Find out how many frames were processed. */ 962 c = cnt; 963 i = sc->lge_cdata.lge_rx_cons; 964 965 /* Suck them in. */ 966 while(c) { 967 struct mbuf *m0 = NULL; 968 969 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 970 rxctl = cur_rx->lge_ctl; 971 rxsts = cur_rx->lge_sts; 972 m = cur_rx->lge_mbuf; 973 cur_rx->lge_mbuf = NULL; 974 total_len = LGE_RXBYTES(cur_rx); 975 LGE_INC(i, LGE_RX_LIST_CNT); 976 c--; 977 978 /* 979 * If an error occurs, update stats, clear the 980 * status word and leave the mbuf cluster in place: 981 * it should simply get re-used next time this descriptor 982 * comes up in the ring. 983 */ 984 if (rxctl & LGE_RXCTL_ERRMASK) { 985 ifp->if_ierrors++; 986 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 987 continue; 988 } 989 990 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 991 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 992 ifp, NULL); 993 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 994 if (m0 == NULL) { 995 printf("lge%d: no receive buffers " 996 "available -- packet dropped!\n", 997 sc->lge_unit); 998 ifp->if_ierrors++; 999 continue; 1000 } 1001 m = m0; 1002 } else { 1003 m->m_pkthdr.rcvif = ifp; 1004 m->m_pkthdr.len = m->m_len = total_len; 1005 } 1006 1007 ifp->if_ipackets++; 1008 1009 /* Do IP checksum checking. */ 1010 if (rxsts & LGE_RXSTS_ISIP) 1011 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1012 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1013 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1014 if ((rxsts & LGE_RXSTS_ISTCP && 1015 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1016 (rxsts & LGE_RXSTS_ISUDP && 1017 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1018 m->m_pkthdr.csum_flags |= 1019 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1020 m->m_pkthdr.csum_data = 0xffff; 1021 } 1022 1023 (*ifp->if_input)(ifp, m); 1024 } 1025 1026 sc->lge_cdata.lge_rx_cons = i; 1027 1028 return; 1029} 1030 1031static void 1032lge_rxeoc(sc) 1033 struct lge_softc *sc; 1034{ 1035 struct ifnet *ifp; 1036 1037 ifp = &sc->arpcom.ac_if; 1038 ifp->if_flags &= ~IFF_RUNNING; 1039 lge_init(sc); 1040 return; 1041} 1042 1043/* 1044 * A frame was downloaded to the chip. It's safe for us to clean up 1045 * the list buffers. 1046 */ 1047 1048static void 1049lge_txeof(sc) 1050 struct lge_softc *sc; 1051{ 1052 struct lge_tx_desc *cur_tx = NULL; 1053 struct ifnet *ifp; 1054 u_int32_t idx, txdone; 1055 1056 ifp = &sc->arpcom.ac_if; 1057 1058 /* Clear the timeout timer. */ 1059 ifp->if_timer = 0; 1060 1061 /* 1062 * Go through our tx list and free mbufs for those 1063 * frames that have been transmitted. 1064 */ 1065 idx = sc->lge_cdata.lge_tx_cons; 1066 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1067 1068 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1069 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1070 1071 ifp->if_opackets++; 1072 if (cur_tx->lge_mbuf != NULL) { 1073 m_freem(cur_tx->lge_mbuf); 1074 cur_tx->lge_mbuf = NULL; 1075 } 1076 cur_tx->lge_ctl = 0; 1077 1078 txdone--; 1079 LGE_INC(idx, LGE_TX_LIST_CNT); 1080 ifp->if_timer = 0; 1081 } 1082 1083 sc->lge_cdata.lge_tx_cons = idx; 1084 1085 if (cur_tx != NULL) 1086 ifp->if_flags &= ~IFF_OACTIVE; 1087 1088 return; 1089} 1090 1091static void 1092lge_tick(xsc) 1093 void *xsc; 1094{ 1095 struct lge_softc *sc; 1096 struct mii_data *mii; 1097 struct ifnet *ifp; 1098 int s; 1099 1100 s = splimp(); 1101 1102 sc = xsc; 1103 ifp = &sc->arpcom.ac_if; 1104 1105 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1106 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1107 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1108 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1109 1110 if (!sc->lge_link) { 1111 mii = device_get_softc(sc->lge_miibus); 1112 mii_tick(mii); 1113 if (mii->mii_media_status & IFM_ACTIVE && 1114 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1115 sc->lge_link++; 1116 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1117 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1118 printf("lge%d: gigabit link up\n", 1119 sc->lge_unit); 1120 if (ifp->if_snd.ifq_head != NULL) 1121 lge_start(ifp); 1122 } 1123 } 1124 1125 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1126 1127 splx(s); 1128 1129 return; 1130} 1131 1132static void 1133lge_intr(arg) 1134 void *arg; 1135{ 1136 struct lge_softc *sc; 1137 struct ifnet *ifp; 1138 u_int32_t status; 1139 1140 sc = arg; 1141 ifp = &sc->arpcom.ac_if; 1142 1143 /* Supress unwanted interrupts */ 1144 if (!(ifp->if_flags & IFF_UP)) { 1145 lge_stop(sc); 1146 return; 1147 } 1148 1149 for (;;) { 1150 /* 1151 * Reading the ISR register clears all interrupts, and 1152 * clears the 'interrupts enabled' bit in the IMR 1153 * register. 1154 */ 1155 status = CSR_READ_4(sc, LGE_ISR); 1156 1157 if ((status & LGE_INTRS) == 0) 1158 break; 1159 1160 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1161 lge_txeof(sc); 1162 1163 if (status & LGE_ISR_RXDMA_DONE) 1164 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1165 1166 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1167 lge_rxeoc(sc); 1168 1169 if (status & LGE_ISR_PHY_INTR) { 1170 sc->lge_link = 0; 1171 untimeout(lge_tick, sc, sc->lge_stat_ch); 1172 lge_tick(sc); 1173 } 1174 } 1175 1176 /* Re-enable interrupts. */ 1177 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1178 1179 if (ifp->if_snd.ifq_head != NULL) 1180 lge_start(ifp); 1181 1182 return; 1183} 1184 1185/* 1186 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1187 * pointers to the fragment pointers. 1188 */ 1189static int 1190lge_encap(sc, m_head, txidx) 1191 struct lge_softc *sc; 1192 struct mbuf *m_head; 1193 u_int32_t *txidx; 1194{ 1195 struct lge_frag *f = NULL; 1196 struct lge_tx_desc *cur_tx; 1197 struct mbuf *m; 1198 int frag = 0, tot_len = 0; 1199 1200 /* 1201 * Start packing the mbufs in this chain into 1202 * the fragment pointers. Stop when we run out 1203 * of fragments or hit the end of the mbuf chain. 1204 */ 1205 m = m_head; 1206 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1207 frag = 0; 1208 1209 for (m = m_head; m != NULL; m = m->m_next) { 1210 if (m->m_len != 0) { 1211 tot_len += m->m_len; 1212 f = &cur_tx->lge_frags[frag]; 1213 f->lge_fraglen = m->m_len; 1214 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1215 f->lge_fragptr_hi = 0; 1216 frag++; 1217 } 1218 } 1219 1220 if (m != NULL) 1221 return(ENOBUFS); 1222 1223 cur_tx->lge_mbuf = m_head; 1224 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1225 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1226 1227 /* Queue for transmit */ 1228 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1229 1230 return(0); 1231} 1232 1233/* 1234 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1235 * to the mbuf data regions directly in the transmit lists. We also save a 1236 * copy of the pointers since the transmit list fragment pointers are 1237 * physical addresses. 1238 */ 1239 1240static void 1241lge_start(ifp) 1242 struct ifnet *ifp; 1243{ 1244 struct lge_softc *sc; 1245 struct mbuf *m_head = NULL; 1246 u_int32_t idx; 1247 1248 sc = ifp->if_softc; 1249 1250 if (!sc->lge_link) 1251 return; 1252 1253 idx = sc->lge_cdata.lge_tx_prod; 1254 1255 if (ifp->if_flags & IFF_OACTIVE) 1256 return; 1257 1258 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1259 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1260 break; 1261 1262 IF_DEQUEUE(&ifp->if_snd, m_head); 1263 if (m_head == NULL) 1264 break; 1265 1266 if (lge_encap(sc, m_head, &idx)) { 1267 IF_PREPEND(&ifp->if_snd, m_head); 1268 ifp->if_flags |= IFF_OACTIVE; 1269 break; 1270 } 1271 1272 /* 1273 * If there's a BPF listener, bounce a copy of this frame 1274 * to him. 1275 */ 1276 BPF_MTAP(ifp, m_head); 1277 } 1278 1279 sc->lge_cdata.lge_tx_prod = idx; 1280 1281 /* 1282 * Set a timeout in case the chip goes out to lunch. 1283 */ 1284 ifp->if_timer = 5; 1285 1286 return; 1287} 1288 1289static void 1290lge_init(xsc) 1291 void *xsc; 1292{ 1293 struct lge_softc *sc = xsc; 1294 struct ifnet *ifp = &sc->arpcom.ac_if; 1295 struct mii_data *mii; 1296 int s; 1297 1298 if (ifp->if_flags & IFF_RUNNING) 1299 return; 1300 1301 s = splimp(); 1302 1303 /* 1304 * Cancel pending I/O and free all RX/TX buffers. 1305 */ 1306 lge_stop(sc); 1307 lge_reset(sc); 1308 1309 mii = device_get_softc(sc->lge_miibus); 1310 1311 /* Set MAC address */ 1312 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1313 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1314 1315 /* Init circular RX list. */ 1316 if (lge_list_rx_init(sc) == ENOBUFS) { 1317 printf("lge%d: initialization failed: no " 1318 "memory for rx buffers\n", sc->lge_unit); 1319 lge_stop(sc); 1320 (void)splx(s); 1321 return; 1322 } 1323 1324 /* 1325 * Init tx descriptors. 1326 */ 1327 lge_list_tx_init(sc); 1328 1329 /* Set initial value for MODE1 register. */ 1330 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1331 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1332 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1333 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1334 1335 /* If we want promiscuous mode, set the allframes bit. */ 1336 if (ifp->if_flags & IFF_PROMISC) { 1337 CSR_WRITE_4(sc, LGE_MODE1, 1338 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1339 } else { 1340 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1341 } 1342 1343 /* 1344 * Set the capture broadcast bit to capture broadcast frames. 1345 */ 1346 if (ifp->if_flags & IFF_BROADCAST) { 1347 CSR_WRITE_4(sc, LGE_MODE1, 1348 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1349 } else { 1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1351 } 1352 1353 /* Packet padding workaround? */ 1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1355 1356 /* No error frames */ 1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1358 1359 /* Receive large frames */ 1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1361 1362 /* Workaround: disable RX/TX flow control */ 1363 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1364 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1365 1366 /* Make sure to strip CRC from received frames */ 1367 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1368 1369 /* Turn off magic packet mode */ 1370 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1371 1372 /* Turn off all VLAN stuff */ 1373 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1374 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1375 1376 /* Workarond: FIFO overflow */ 1377 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1378 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1379 1380 /* 1381 * Load the multicast filter. 1382 */ 1383 lge_setmulti(sc); 1384 1385 /* 1386 * Enable hardware checksum validation for all received IPv4 1387 * packets, do not reject packets with bad checksums. 1388 */ 1389 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1390 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1391 LGE_MODE2_RX_ERRCSUM); 1392 1393 /* 1394 * Enable the delivery of PHY interrupts based on 1395 * link/speed/duplex status chalges. 1396 */ 1397 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1398 1399 /* Enable receiver and transmitter. */ 1400 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1401 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1402 1403 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1404 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1405 1406 /* 1407 * Enable interrupts. 1408 */ 1409 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1410 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1411 1412 lge_ifmedia_upd(ifp); 1413 1414 ifp->if_flags |= IFF_RUNNING; 1415 ifp->if_flags &= ~IFF_OACTIVE; 1416 1417 (void)splx(s); 1418 1419 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1420 1421 return; 1422} 1423 1424/* 1425 * Set media options. 1426 */ 1427static int 1428lge_ifmedia_upd(ifp) 1429 struct ifnet *ifp; 1430{ 1431 struct lge_softc *sc; 1432 struct mii_data *mii; 1433 1434 sc = ifp->if_softc; 1435 1436 mii = device_get_softc(sc->lge_miibus); 1437 sc->lge_link = 0; 1438 if (mii->mii_instance) { 1439 struct mii_softc *miisc; 1440 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1441 miisc = LIST_NEXT(miisc, mii_list)) 1442 mii_phy_reset(miisc); 1443 } 1444 mii_mediachg(mii); 1445 1446 return(0); 1447} 1448 1449/* 1450 * Report current media status. 1451 */ 1452static void 1453lge_ifmedia_sts(ifp, ifmr) 1454 struct ifnet *ifp; 1455 struct ifmediareq *ifmr; 1456{ 1457 struct lge_softc *sc; 1458 struct mii_data *mii; 1459 1460 sc = ifp->if_softc; 1461 1462 mii = device_get_softc(sc->lge_miibus); 1463 mii_pollstat(mii); 1464 ifmr->ifm_active = mii->mii_media_active; 1465 ifmr->ifm_status = mii->mii_media_status; 1466 1467 return; 1468} 1469 1470static int 1471lge_ioctl(ifp, command, data) 1472 struct ifnet *ifp; 1473 u_long command; 1474 caddr_t data; 1475{ 1476 struct lge_softc *sc = ifp->if_softc; 1477 struct ifreq *ifr = (struct ifreq *) data; 1478 struct mii_data *mii; 1479 int s, error = 0; 1480 1481 s = splimp(); 1482 1483 switch(command) { 1484 case SIOCSIFMTU: 1485 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1486 error = EINVAL; 1487 else 1488 ifp->if_mtu = ifr->ifr_mtu; 1489 break; 1490 case SIOCSIFFLAGS: 1491 if (ifp->if_flags & IFF_UP) { 1492 if (ifp->if_flags & IFF_RUNNING && 1493 ifp->if_flags & IFF_PROMISC && 1494 !(sc->lge_if_flags & IFF_PROMISC)) { 1495 CSR_WRITE_4(sc, LGE_MODE1, 1496 LGE_MODE1_SETRST_CTL1| 1497 LGE_MODE1_RX_PROMISC); 1498 } else if (ifp->if_flags & IFF_RUNNING && 1499 !(ifp->if_flags & IFF_PROMISC) && 1500 sc->lge_if_flags & IFF_PROMISC) { 1501 CSR_WRITE_4(sc, LGE_MODE1, 1502 LGE_MODE1_RX_PROMISC); 1503 } else { 1504 ifp->if_flags &= ~IFF_RUNNING; 1505 lge_init(sc); 1506 } 1507 } else { 1508 if (ifp->if_flags & IFF_RUNNING) 1509 lge_stop(sc); 1510 } 1511 sc->lge_if_flags = ifp->if_flags; 1512 error = 0; 1513 break; 1514 case SIOCADDMULTI: 1515 case SIOCDELMULTI: 1516 lge_setmulti(sc); 1517 error = 0; 1518 break; 1519 case SIOCGIFMEDIA: 1520 case SIOCSIFMEDIA: 1521 mii = device_get_softc(sc->lge_miibus); 1522 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1523 break; 1524 default: 1525 error = ether_ioctl(ifp, command, data); 1526 break; 1527 } 1528 1529 (void)splx(s); 1530 1531 return(error); 1532} 1533 1534static void 1535lge_watchdog(ifp) 1536 struct ifnet *ifp; 1537{ 1538 struct lge_softc *sc; 1539 1540 sc = ifp->if_softc; 1541 1542 ifp->if_oerrors++; 1543 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1544 1545 lge_stop(sc); 1546 lge_reset(sc); 1547 ifp->if_flags &= ~IFF_RUNNING; 1548 lge_init(sc); 1549 1550 if (ifp->if_snd.ifq_head != NULL) 1551 lge_start(ifp); 1552 1553 return; 1554} 1555 1556/* 1557 * Stop the adapter and free any mbufs allocated to the 1558 * RX and TX lists. 1559 */ 1560static void 1561lge_stop(sc) 1562 struct lge_softc *sc; 1563{ 1564 register int i; 1565 struct ifnet *ifp; 1566 1567 ifp = &sc->arpcom.ac_if; 1568 ifp->if_timer = 0; 1569 untimeout(lge_tick, sc, sc->lge_stat_ch); 1570 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1571 1572 /* Disable receiver and transmitter. */ 1573 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1574 sc->lge_link = 0; 1575 1576 /* 1577 * Free data in the RX lists. 1578 */ 1579 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1580 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1581 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1582 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1583 } 1584 } 1585 bzero((char *)&sc->lge_ldata->lge_rx_list, 1586 sizeof(sc->lge_ldata->lge_rx_list)); 1587 1588 /* 1589 * Free the TX list buffers. 1590 */ 1591 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1592 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1593 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1594 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1595 } 1596 } 1597 1598 bzero((char *)&sc->lge_ldata->lge_tx_list, 1599 sizeof(sc->lge_ldata->lge_tx_list)); 1600 1601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1602 1603 return; 1604} 1605 1606/* 1607 * Stop all chip I/O so that the kernel's probe routines don't 1608 * get confused by errant DMAs when rebooting. 1609 */ 1610static void 1611lge_shutdown(dev) 1612 device_t dev; 1613{ 1614 struct lge_softc *sc; 1615 1616 sc = device_get_softc(dev); 1617 1618 lge_reset(sc); 1619 lge_stop(sc); 1620 1621 return; 1622} 1623