if_ixl.c revision 279255
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/if_ixl.c 279255 2015-02-24 22:17:12Z adrian $*/ 34 35#ifndef IXL_STANDALONE_BUILD 36#include "opt_inet.h" 37#include "opt_inet6.h" 38#include "opt_rss.h" 39#endif 40 41#include "ixl.h" 42#include "ixl_pf.h" 43 44#ifdef RSS 45#include <net/rss_config.h> 46#endif 47 48/********************************************************************* 49 * Driver version 50 *********************************************************************/ 51char ixl_driver_version[] = "1.3.6"; 52 53/********************************************************************* 54 * PCI Device ID Table 55 * 56 * Used by probe to select devices to load on 57 * Last field stores an index into ixl_strings 58 * Last entry must be all 0s 59 * 60 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 61 *********************************************************************/ 62 63static ixl_vendor_info_t ixl_vendor_info_array[] = 64{ 65 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710, 0, 0, 0}, 66 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A, 0, 0, 0}, 67 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B, 0, 0, 0}, 68 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C, 0, 0, 0}, 69 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A, 0, 0, 0}, 70 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B, 0, 0, 0}, 71 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0}, 72 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0}, 73 /* required last entry */ 74 {0, 0, 0, 0, 0} 75}; 76 77/********************************************************************* 78 * Table of branding strings 79 *********************************************************************/ 80 81static char *ixl_strings[] = { 82 "Intel(R) Ethernet Connection XL710 Driver" 83}; 84 85 86/********************************************************************* 87 * Function prototypes 88 *********************************************************************/ 89static int ixl_probe(device_t); 90static int ixl_attach(device_t); 91static int ixl_detach(device_t); 92static int ixl_shutdown(device_t); 93static int ixl_get_hw_capabilities(struct ixl_pf *); 94static void ixl_cap_txcsum_tso(struct ixl_vsi *, struct ifnet *, int); 95static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 96static void ixl_init(void *); 97static void ixl_init_locked(struct ixl_pf *); 98static void ixl_stop(struct ixl_pf *); 99static void ixl_media_status(struct ifnet *, struct ifmediareq *); 100static int ixl_media_change(struct ifnet *); 101static void ixl_update_link_status(struct ixl_pf *); 102static int ixl_allocate_pci_resources(struct ixl_pf *); 103static u16 ixl_get_bus_info(struct i40e_hw *, device_t); 104static int ixl_setup_stations(struct ixl_pf *); 105static int ixl_switch_config(struct ixl_pf *); 106static int ixl_initialize_vsi(struct ixl_vsi *); 107static int ixl_assign_vsi_msix(struct ixl_pf *); 108static int ixl_assign_vsi_legacy(struct ixl_pf *); 109static int ixl_init_msix(struct ixl_pf *); 110static void ixl_configure_msix(struct ixl_pf *); 111static void ixl_configure_itr(struct ixl_pf *); 112static void ixl_configure_legacy(struct ixl_pf *); 113static void ixl_free_pci_resources(struct ixl_pf *); 114static void ixl_local_timer(void *); 115static int ixl_setup_interface(device_t, struct ixl_vsi *); 116static bool ixl_config_link(struct i40e_hw *); 117static void ixl_config_rss(struct ixl_vsi *); 118static void ixl_set_queue_rx_itr(struct ixl_queue *); 119static void ixl_set_queue_tx_itr(struct ixl_queue *); 120static int ixl_set_advertised_speeds(struct ixl_pf *, int); 121 122static void ixl_enable_rings(struct ixl_vsi *); 123static void ixl_disable_rings(struct ixl_vsi *); 124static void ixl_enable_intr(struct ixl_vsi *); 125static void ixl_disable_intr(struct ixl_vsi *); 126 127static void ixl_enable_adminq(struct i40e_hw *); 128static void ixl_disable_adminq(struct i40e_hw *); 129static void ixl_enable_queue(struct i40e_hw *, int); 130static void ixl_disable_queue(struct i40e_hw *, int); 131static void ixl_enable_legacy(struct i40e_hw *); 132static void ixl_disable_legacy(struct i40e_hw *); 133 134static void ixl_set_promisc(struct ixl_vsi *); 135static void ixl_add_multi(struct ixl_vsi *); 136static void ixl_del_multi(struct ixl_vsi *); 137static void ixl_register_vlan(void *, struct ifnet *, u16); 138static void ixl_unregister_vlan(void *, struct ifnet *, u16); 139static void ixl_setup_vlan_filters(struct ixl_vsi *); 140 141static void ixl_init_filters(struct ixl_vsi *); 142static void ixl_add_filter(struct ixl_vsi *, u8 *, s16 vlan); 143static void ixl_del_filter(struct ixl_vsi *, u8 *, s16 vlan); 144static void ixl_add_hw_filters(struct ixl_vsi *, int, int); 145static void ixl_del_hw_filters(struct ixl_vsi *, int); 146static struct ixl_mac_filter * 147 ixl_find_filter(struct ixl_vsi *, u8 *, s16); 148static void ixl_add_mc_filter(struct ixl_vsi *, u8 *); 149 150/* Sysctl debug interface */ 151static int ixl_debug_info(SYSCTL_HANDLER_ARGS); 152static void ixl_print_debug_info(struct ixl_pf *); 153 154/* The MSI/X Interrupt handlers */ 155static void ixl_intr(void *); 156static void ixl_msix_que(void *); 157static void ixl_msix_adminq(void *); 158static void ixl_handle_mdd_event(struct ixl_pf *); 159 160/* Deferred interrupt tasklets */ 161static void ixl_do_adminq(void *, int); 162 163/* Sysctl handlers */ 164static int ixl_set_flowcntl(SYSCTL_HANDLER_ARGS); 165static int ixl_set_advertise(SYSCTL_HANDLER_ARGS); 166static int ixl_current_speed(SYSCTL_HANDLER_ARGS); 167static int ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS); 168 169/* Statistics */ 170static void ixl_add_hw_stats(struct ixl_pf *); 171static void ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *, 172 struct sysctl_oid_list *, struct i40e_hw_port_stats *); 173static void ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *, 174 struct sysctl_oid_list *, 175 struct i40e_eth_stats *); 176static void ixl_update_stats_counters(struct ixl_pf *); 177static void ixl_update_eth_stats(struct ixl_vsi *); 178static void ixl_pf_reset_stats(struct ixl_pf *); 179static void ixl_vsi_reset_stats(struct ixl_vsi *); 180static void ixl_stat_update48(struct i40e_hw *, u32, u32, bool, 181 u64 *, u64 *); 182static void ixl_stat_update32(struct i40e_hw *, u32, bool, 183 u64 *, u64 *); 184 185#ifdef IXL_DEBUG_SYSCTL 186static int ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS); 187static int ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS); 188static int ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS); 189static int ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS); 190static int ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS); 191static int ixl_sysctl_dump_txd(SYSCTL_HANDLER_ARGS); 192#endif 193 194/********************************************************************* 195 * FreeBSD Device Interface Entry Points 196 *********************************************************************/ 197 198static device_method_t ixl_methods[] = { 199 /* Device interface */ 200 DEVMETHOD(device_probe, ixl_probe), 201 DEVMETHOD(device_attach, ixl_attach), 202 DEVMETHOD(device_detach, ixl_detach), 203 DEVMETHOD(device_shutdown, ixl_shutdown), 204 {0, 0} 205}; 206 207static driver_t ixl_driver = { 208 "ixl", ixl_methods, sizeof(struct ixl_pf), 209}; 210 211devclass_t ixl_devclass; 212DRIVER_MODULE(ixl, pci, ixl_driver, ixl_devclass, 0, 0); 213 214MODULE_DEPEND(ixl, pci, 1, 1, 1); 215MODULE_DEPEND(ixl, ether, 1, 1, 1); 216#ifdef DEV_NETMAP 217MODULE_DEPEND(ixl, netmap, 1, 1, 1); 218#endif /* DEV_NETMAP */ 219 220/* 221** Global reset mutex 222*/ 223static struct mtx ixl_reset_mtx; 224 225/* 226** TUNEABLE PARAMETERS: 227*/ 228 229static SYSCTL_NODE(_hw, OID_AUTO, ixl, CTLFLAG_RD, 0, 230 "IXL driver parameters"); 231 232/* 233 * MSIX should be the default for best performance, 234 * but this allows it to be forced off for testing. 235 */ 236static int ixl_enable_msix = 1; 237TUNABLE_INT("hw.ixl.enable_msix", &ixl_enable_msix); 238SYSCTL_INT(_hw_ixl, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixl_enable_msix, 0, 239 "Enable MSI-X interrupts"); 240 241/* 242** Number of descriptors per ring: 243** - TX and RX are the same size 244*/ 245static int ixl_ringsz = DEFAULT_RING; 246TUNABLE_INT("hw.ixl.ringsz", &ixl_ringsz); 247SYSCTL_INT(_hw_ixl, OID_AUTO, ring_size, CTLFLAG_RDTUN, 248 &ixl_ringsz, 0, "Descriptor Ring Size"); 249 250/* 251** This can be set manually, if left as 0 the 252** number of queues will be calculated based 253** on cpus and msix vectors available. 254*/ 255int ixl_max_queues = 0; 256TUNABLE_INT("hw.ixl.max_queues", &ixl_max_queues); 257SYSCTL_INT(_hw_ixl, OID_AUTO, max_queues, CTLFLAG_RDTUN, 258 &ixl_max_queues, 0, "Number of Queues"); 259 260/* 261** Controls for Interrupt Throttling 262** - true/false for dynamic adjustment 263** - default values for static ITR 264*/ 265int ixl_dynamic_rx_itr = 0; 266TUNABLE_INT("hw.ixl.dynamic_rx_itr", &ixl_dynamic_rx_itr); 267SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_rx_itr, CTLFLAG_RDTUN, 268 &ixl_dynamic_rx_itr, 0, "Dynamic RX Interrupt Rate"); 269 270int ixl_dynamic_tx_itr = 0; 271TUNABLE_INT("hw.ixl.dynamic_tx_itr", &ixl_dynamic_tx_itr); 272SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_tx_itr, CTLFLAG_RDTUN, 273 &ixl_dynamic_tx_itr, 0, "Dynamic TX Interrupt Rate"); 274 275int ixl_rx_itr = IXL_ITR_8K; 276TUNABLE_INT("hw.ixl.rx_itr", &ixl_rx_itr); 277SYSCTL_INT(_hw_ixl, OID_AUTO, rx_itr, CTLFLAG_RDTUN, 278 &ixl_rx_itr, 0, "RX Interrupt Rate"); 279 280int ixl_tx_itr = IXL_ITR_4K; 281TUNABLE_INT("hw.ixl.tx_itr", &ixl_tx_itr); 282SYSCTL_INT(_hw_ixl, OID_AUTO, tx_itr, CTLFLAG_RDTUN, 283 &ixl_tx_itr, 0, "TX Interrupt Rate"); 284 285#ifdef IXL_FDIR 286static int ixl_enable_fdir = 1; 287TUNABLE_INT("hw.ixl.enable_fdir", &ixl_enable_fdir); 288/* Rate at which we sample */ 289int ixl_atr_rate = 20; 290TUNABLE_INT("hw.ixl.atr_rate", &ixl_atr_rate); 291#endif 292 293#ifdef DEV_NETMAP 294#define NETMAP_IXL_MAIN /* only bring in one part of the netmap code */ 295#include <dev/netmap/if_ixl_netmap.h> 296#endif /* DEV_NETMAP */ 297 298static char *ixl_fc_string[6] = { 299 "None", 300 "Rx", 301 "Tx", 302 "Full", 303 "Priority", 304 "Default" 305}; 306 307 308/********************************************************************* 309 * Device identification routine 310 * 311 * ixl_probe determines if the driver should be loaded on 312 * the hardware based on PCI vendor/device id of the device. 313 * 314 * return BUS_PROBE_DEFAULT on success, positive on failure 315 *********************************************************************/ 316 317static int 318ixl_probe(device_t dev) 319{ 320 ixl_vendor_info_t *ent; 321 322 u16 pci_vendor_id, pci_device_id; 323 u16 pci_subvendor_id, pci_subdevice_id; 324 char device_name[256]; 325 static bool lock_init = FALSE; 326 327 INIT_DEBUGOUT("ixl_probe: begin"); 328 329 pci_vendor_id = pci_get_vendor(dev); 330 if (pci_vendor_id != I40E_INTEL_VENDOR_ID) 331 return (ENXIO); 332 333 pci_device_id = pci_get_device(dev); 334 pci_subvendor_id = pci_get_subvendor(dev); 335 pci_subdevice_id = pci_get_subdevice(dev); 336 337 ent = ixl_vendor_info_array; 338 while (ent->vendor_id != 0) { 339 if ((pci_vendor_id == ent->vendor_id) && 340 (pci_device_id == ent->device_id) && 341 342 ((pci_subvendor_id == ent->subvendor_id) || 343 (ent->subvendor_id == 0)) && 344 345 ((pci_subdevice_id == ent->subdevice_id) || 346 (ent->subdevice_id == 0))) { 347 sprintf(device_name, "%s, Version - %s", 348 ixl_strings[ent->index], 349 ixl_driver_version); 350 device_set_desc_copy(dev, device_name); 351 /* One shot mutex init */ 352 if (lock_init == FALSE) { 353 lock_init = TRUE; 354 mtx_init(&ixl_reset_mtx, 355 "ixl_reset", 356 "IXL RESET Lock", MTX_DEF); 357 } 358 return (BUS_PROBE_DEFAULT); 359 } 360 ent++; 361 } 362 return (ENXIO); 363} 364 365/********************************************************************* 366 * Device initialization routine 367 * 368 * The attach entry point is called when the driver is being loaded. 369 * This routine identifies the type of hardware, allocates all resources 370 * and initializes the hardware. 371 * 372 * return 0 on success, positive on failure 373 *********************************************************************/ 374 375static int 376ixl_attach(device_t dev) 377{ 378 struct ixl_pf *pf; 379 struct i40e_hw *hw; 380 struct ixl_vsi *vsi; 381 u16 bus; 382 int error = 0; 383 384 INIT_DEBUGOUT("ixl_attach: begin"); 385 386 /* Allocate, clear, and link in our primary soft structure */ 387 pf = device_get_softc(dev); 388 pf->dev = pf->osdep.dev = dev; 389 hw = &pf->hw; 390 391 /* 392 ** Note this assumes we have a single embedded VSI, 393 ** this could be enhanced later to allocate multiple 394 */ 395 vsi = &pf->vsi; 396 vsi->dev = pf->dev; 397 398 /* Core Lock Init*/ 399 IXL_PF_LOCK_INIT(pf, device_get_nameunit(dev)); 400 401 /* Set up the timer callout */ 402 callout_init_mtx(&pf->timer, &pf->pf_mtx, 0); 403 404 /* Set up sysctls */ 405 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 406 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 407 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW, 408 pf, 0, ixl_set_flowcntl, "I", "Flow Control"); 409 410 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 411 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 412 OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW, 413 pf, 0, ixl_set_advertise, "I", "Advertised Speed"); 414 415 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 416 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 417 OID_AUTO, "current_speed", CTLTYPE_STRING | CTLFLAG_RD, 418 pf, 0, ixl_current_speed, "A", "Current Port Speed"); 419 420 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 421 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 422 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 423 pf, 0, ixl_sysctl_show_fw, "A", "Firmware version"); 424 425 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 426 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 427 OID_AUTO, "rx_itr", CTLFLAG_RW, 428 &ixl_rx_itr, IXL_ITR_8K, "RX ITR"); 429 430 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 431 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 432 OID_AUTO, "dynamic_rx_itr", CTLFLAG_RW, 433 &ixl_dynamic_rx_itr, 0, "Dynamic RX ITR"); 434 435 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 436 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 437 OID_AUTO, "tx_itr", CTLFLAG_RW, 438 &ixl_tx_itr, IXL_ITR_4K, "TX ITR"); 439 440 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 441 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 442 OID_AUTO, "dynamic_tx_itr", CTLFLAG_RW, 443 &ixl_dynamic_tx_itr, 0, "Dynamic TX ITR"); 444 445#ifdef IXL_DEBUG_SYSCTL 446 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 447 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 448 OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD, 449 pf, 0, ixl_sysctl_link_status, "A", "Current Link Status"); 450 451 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 452 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 453 OID_AUTO, "phy_abilities", CTLTYPE_STRING | CTLFLAG_RD, 454 pf, 0, ixl_sysctl_phy_abilities, "A", "PHY Abilities"); 455 456 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 457 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 458 OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD, 459 pf, 0, ixl_sysctl_sw_filter_list, "A", "SW Filter List"); 460 461 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 462 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 463 OID_AUTO, "hw_res_alloc", CTLTYPE_STRING | CTLFLAG_RD, 464 pf, 0, ixl_sysctl_hw_res_alloc, "A", "HW Resource Allocation"); 465 466 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 467 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 468 OID_AUTO, "switch_config", CTLTYPE_STRING | CTLFLAG_RD, 469 pf, 0, ixl_sysctl_switch_config, "A", "HW Switch Configuration"); 470 471 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 472 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 473 OID_AUTO, "dump_desc", CTLTYPE_INT | CTLFLAG_WR, 474 pf, 0, ixl_sysctl_dump_txd, "I", "Desc dump"); 475#endif 476 477 /* Save off the PCI information */ 478 hw->vendor_id = pci_get_vendor(dev); 479 hw->device_id = pci_get_device(dev); 480 hw->revision_id = pci_read_config(dev, PCIR_REVID, 1); 481 hw->subsystem_vendor_id = 482 pci_read_config(dev, PCIR_SUBVEND_0, 2); 483 hw->subsystem_device_id = 484 pci_read_config(dev, PCIR_SUBDEV_0, 2); 485 486 hw->bus.device = pci_get_slot(dev); 487 hw->bus.func = pci_get_function(dev); 488 489 /* Do PCI setup - map BAR0, etc */ 490 if (ixl_allocate_pci_resources(pf)) { 491 device_printf(dev, "Allocation of PCI resources failed\n"); 492 error = ENXIO; 493 goto err_out; 494 } 495 496 /* Create for initial debugging use */ 497 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 498 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 499 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0, 500 ixl_debug_info, "I", "Debug Information"); 501 502 503 /* Establish a clean starting point */ 504 i40e_clear_hw(hw); 505 error = i40e_pf_reset(hw); 506 if (error) { 507 device_printf(dev,"PF reset failure %x\n", error); 508 error = EIO; 509 goto err_out; 510 } 511 512 /* Set admin queue parameters */ 513 hw->aq.num_arq_entries = IXL_AQ_LEN; 514 hw->aq.num_asq_entries = IXL_AQ_LEN; 515 hw->aq.arq_buf_size = IXL_AQ_BUFSZ; 516 hw->aq.asq_buf_size = IXL_AQ_BUFSZ; 517 518 /* Initialize the shared code */ 519 error = i40e_init_shared_code(hw); 520 if (error) { 521 device_printf(dev,"Unable to initialize the shared code\n"); 522 error = EIO; 523 goto err_out; 524 } 525 526 /* Set up the admin queue */ 527 error = i40e_init_adminq(hw); 528 if (error) { 529 device_printf(dev, "The driver for the device stopped " 530 "because the NVM image is newer than expected.\n" 531 "You must install the most recent version of " 532 " the network driver.\n"); 533 goto err_out; 534 } 535 device_printf(dev, "%s\n", ixl_fw_version_str(hw)); 536 537 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 538 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) 539 device_printf(dev, "The driver for the device detected " 540 "a newer version of the NVM image than expected.\n" 541 "Please install the most recent version of the network driver.\n"); 542 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || 543 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) 544 device_printf(dev, "The driver for the device detected " 545 "an older version of the NVM image than expected.\n" 546 "Please update the NVM image.\n"); 547 548 /* Clear PXE mode */ 549 i40e_clear_pxe_mode(hw); 550 551 /* Get capabilities from the device */ 552 error = ixl_get_hw_capabilities(pf); 553 if (error) { 554 device_printf(dev, "HW capabilities failure!\n"); 555 goto err_get_cap; 556 } 557 558 /* Set up host memory cache */ 559 error = i40e_init_lan_hmc(hw, vsi->num_queues, vsi->num_queues, 0, 0); 560 if (error) { 561 device_printf(dev, "init_lan_hmc failed: %d\n", error); 562 goto err_get_cap; 563 } 564 565 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 566 if (error) { 567 device_printf(dev, "configure_lan_hmc failed: %d\n", error); 568 goto err_mac_hmc; 569 } 570 571 /* Disable LLDP from the firmware */ 572 i40e_aq_stop_lldp(hw, TRUE, NULL); 573 574 i40e_get_mac_addr(hw, hw->mac.addr); 575 error = i40e_validate_mac_addr(hw->mac.addr); 576 if (error) { 577 device_printf(dev, "validate_mac_addr failed: %d\n", error); 578 goto err_mac_hmc; 579 } 580 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN); 581 i40e_get_port_mac_addr(hw, hw->mac.port_addr); 582 583 /* Set up VSI and queues */ 584 if (ixl_setup_stations(pf) != 0) { 585 device_printf(dev, "setup stations failed!\n"); 586 error = ENOMEM; 587 goto err_mac_hmc; 588 } 589 590 /* Initialize mac filter list for VSI */ 591 SLIST_INIT(&vsi->ftl); 592 593 /* Set up interrupt routing here */ 594 if (pf->msix > 1) 595 error = ixl_assign_vsi_msix(pf); 596 else 597 error = ixl_assign_vsi_legacy(pf); 598 if (error) 599 goto err_late; 600 601 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || 602 (hw->aq.fw_maj_ver < 4)) { 603 i40e_msec_delay(75); 604 error = i40e_aq_set_link_restart_an(hw, TRUE, NULL); 605 if (error) 606 device_printf(dev, "link restart failed, aq_err=%d\n", 607 pf->hw.aq.asq_last_status); 608 } 609 610 /* Determine link state */ 611 vsi->link_up = ixl_config_link(hw); 612 613 /* Report if Unqualified modules are found */ 614 if ((vsi->link_up == FALSE) && 615 (pf->hw.phy.link_info.link_info & 616 I40E_AQ_MEDIA_AVAILABLE) && 617 (!(pf->hw.phy.link_info.an_info & 618 I40E_AQ_QUALIFIED_MODULE))) 619 device_printf(dev, "Link failed because " 620 "an unqualified module was detected\n"); 621 622 /* Setup OS specific network interface */ 623 if (ixl_setup_interface(dev, vsi) != 0) { 624 device_printf(dev, "interface setup failed!\n"); 625 error = EIO; 626 goto err_late; 627 } 628 629 error = ixl_switch_config(pf); 630 if (error) { 631 device_printf(dev, "Initial switch config failed: %d\n", error); 632 goto err_mac_hmc; 633 } 634 635 /* Limit phy interrupts to link and modules failure */ 636 error = i40e_aq_set_phy_int_mask(hw, 637 I40E_AQ_EVENT_LINK_UPDOWN | I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL); 638 if (error) 639 device_printf(dev, "set phy mask failed: %d\n", error); 640 641 /* Get the bus configuration and set the shared code */ 642 bus = ixl_get_bus_info(hw, dev); 643 i40e_set_pci_config_data(hw, bus); 644 645 /* Initialize statistics */ 646 ixl_pf_reset_stats(pf); 647 ixl_update_stats_counters(pf); 648 ixl_add_hw_stats(pf); 649 650 /* Register for VLAN events */ 651 vsi->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 652 ixl_register_vlan, vsi, EVENTHANDLER_PRI_FIRST); 653 vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 654 ixl_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST); 655 656 657#ifdef DEV_NETMAP 658 ixl_netmap_attach(vsi); 659#endif /* DEV_NETMAP */ 660 INIT_DEBUGOUT("ixl_attach: end"); 661 return (0); 662 663err_late: 664 if (vsi->ifp != NULL) 665 if_free(vsi->ifp); 666err_mac_hmc: 667 i40e_shutdown_lan_hmc(hw); 668err_get_cap: 669 i40e_shutdown_adminq(hw); 670err_out: 671 ixl_free_pci_resources(pf); 672 ixl_free_vsi(vsi); 673 IXL_PF_LOCK_DESTROY(pf); 674 return (error); 675} 676 677/********************************************************************* 678 * Device removal routine 679 * 680 * The detach entry point is called when the driver is being removed. 681 * This routine stops the adapter and deallocates all the resources 682 * that were allocated for driver operation. 683 * 684 * return 0 on success, positive on failure 685 *********************************************************************/ 686 687static int 688ixl_detach(device_t dev) 689{ 690 struct ixl_pf *pf = device_get_softc(dev); 691 struct i40e_hw *hw = &pf->hw; 692 struct ixl_vsi *vsi = &pf->vsi; 693 struct ixl_queue *que = vsi->queues; 694 i40e_status status; 695 696 INIT_DEBUGOUT("ixl_detach: begin"); 697 698 /* Make sure VLANS are not using driver */ 699 if (vsi->ifp->if_vlantrunk != NULL) { 700 device_printf(dev,"Vlan in use, detach first\n"); 701 return (EBUSY); 702 } 703 704 ether_ifdetach(vsi->ifp); 705 if (vsi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 706 IXL_PF_LOCK(pf); 707 ixl_stop(pf); 708 IXL_PF_UNLOCK(pf); 709 } 710 711 for (int i = 0; i < vsi->num_queues; i++, que++) { 712 if (que->tq) { 713 taskqueue_drain(que->tq, &que->task); 714 taskqueue_drain(que->tq, &que->tx_task); 715 taskqueue_free(que->tq); 716 } 717 } 718 719 /* Shutdown LAN HMC */ 720 status = i40e_shutdown_lan_hmc(hw); 721 if (status) 722 device_printf(dev, 723 "Shutdown LAN HMC failed with code %d\n", status); 724 725 /* Shutdown admin queue */ 726 status = i40e_shutdown_adminq(hw); 727 if (status) 728 device_printf(dev, 729 "Shutdown Admin queue failed with code %d\n", status); 730 731 /* Unregister VLAN events */ 732 if (vsi->vlan_attach != NULL) 733 EVENTHANDLER_DEREGISTER(vlan_config, vsi->vlan_attach); 734 if (vsi->vlan_detach != NULL) 735 EVENTHANDLER_DEREGISTER(vlan_unconfig, vsi->vlan_detach); 736 737 callout_drain(&pf->timer); 738#ifdef DEV_NETMAP 739 netmap_detach(vsi->ifp); 740#endif /* DEV_NETMAP */ 741 742 743 ixl_free_pci_resources(pf); 744 bus_generic_detach(dev); 745 if_free(vsi->ifp); 746 ixl_free_vsi(vsi); 747 IXL_PF_LOCK_DESTROY(pf); 748 return (0); 749} 750 751/********************************************************************* 752 * 753 * Shutdown entry point 754 * 755 **********************************************************************/ 756 757static int 758ixl_shutdown(device_t dev) 759{ 760 struct ixl_pf *pf = device_get_softc(dev); 761 IXL_PF_LOCK(pf); 762 ixl_stop(pf); 763 IXL_PF_UNLOCK(pf); 764 return (0); 765} 766 767 768/********************************************************************* 769 * 770 * Get the hardware capabilities 771 * 772 **********************************************************************/ 773 774static int 775ixl_get_hw_capabilities(struct ixl_pf *pf) 776{ 777 struct i40e_aqc_list_capabilities_element_resp *buf; 778 struct i40e_hw *hw = &pf->hw; 779 device_t dev = pf->dev; 780 int error, len; 781 u16 needed; 782 bool again = TRUE; 783 784 len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 785retry: 786 if (!(buf = (struct i40e_aqc_list_capabilities_element_resp *) 787 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO))) { 788 device_printf(dev, "Unable to allocate cap memory\n"); 789 return (ENOMEM); 790 } 791 792 /* This populates the hw struct */ 793 error = i40e_aq_discover_capabilities(hw, buf, len, 794 &needed, i40e_aqc_opc_list_func_capabilities, NULL); 795 free(buf, M_DEVBUF); 796 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) && 797 (again == TRUE)) { 798 /* retry once with a larger buffer */ 799 again = FALSE; 800 len = needed; 801 goto retry; 802 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { 803 device_printf(dev, "capability discovery failed: %d\n", 804 pf->hw.aq.asq_last_status); 805 return (ENODEV); 806 } 807 808 /* Capture this PF's starting queue pair */ 809 pf->qbase = hw->func_caps.base_queue; 810 811#ifdef IXL_DEBUG 812 device_printf(dev,"pf_id=%d, num_vfs=%d, msix_pf=%d, " 813 "msix_vf=%d, fd_g=%d, fd_b=%d, tx_qp=%d rx_qp=%d qbase=%d\n", 814 hw->pf_id, hw->func_caps.num_vfs, 815 hw->func_caps.num_msix_vectors, 816 hw->func_caps.num_msix_vectors_vf, 817 hw->func_caps.fd_filters_guaranteed, 818 hw->func_caps.fd_filters_best_effort, 819 hw->func_caps.num_tx_qp, 820 hw->func_caps.num_rx_qp, 821 hw->func_caps.base_queue); 822#endif 823 return (error); 824} 825 826static void 827ixl_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask) 828{ 829 device_t dev = vsi->dev; 830 831 /* Enable/disable TXCSUM/TSO4 */ 832 if (!(ifp->if_capenable & IFCAP_TXCSUM) 833 && !(ifp->if_capenable & IFCAP_TSO4)) { 834 if (mask & IFCAP_TXCSUM) { 835 ifp->if_capenable |= IFCAP_TXCSUM; 836 /* enable TXCSUM, restore TSO if previously enabled */ 837 if (vsi->flags & IXL_FLAGS_KEEP_TSO4) { 838 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 839 ifp->if_capenable |= IFCAP_TSO4; 840 } 841 } 842 else if (mask & IFCAP_TSO4) { 843 ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4); 844 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 845 device_printf(dev, 846 "TSO4 requires txcsum, enabling both...\n"); 847 } 848 } else if((ifp->if_capenable & IFCAP_TXCSUM) 849 && !(ifp->if_capenable & IFCAP_TSO4)) { 850 if (mask & IFCAP_TXCSUM) 851 ifp->if_capenable &= ~IFCAP_TXCSUM; 852 else if (mask & IFCAP_TSO4) 853 ifp->if_capenable |= IFCAP_TSO4; 854 } else if((ifp->if_capenable & IFCAP_TXCSUM) 855 && (ifp->if_capenable & IFCAP_TSO4)) { 856 if (mask & IFCAP_TXCSUM) { 857 vsi->flags |= IXL_FLAGS_KEEP_TSO4; 858 ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4); 859 device_printf(dev, 860 "TSO4 requires txcsum, disabling both...\n"); 861 } else if (mask & IFCAP_TSO4) 862 ifp->if_capenable &= ~IFCAP_TSO4; 863 } 864 865 /* Enable/disable TXCSUM_IPV6/TSO6 */ 866 if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6) 867 && !(ifp->if_capenable & IFCAP_TSO6)) { 868 if (mask & IFCAP_TXCSUM_IPV6) { 869 ifp->if_capenable |= IFCAP_TXCSUM_IPV6; 870 if (vsi->flags & IXL_FLAGS_KEEP_TSO6) { 871 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 872 ifp->if_capenable |= IFCAP_TSO6; 873 } 874 } else if (mask & IFCAP_TSO6) { 875 ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 876 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 877 device_printf(dev, 878 "TSO6 requires txcsum6, enabling both...\n"); 879 } 880 } else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 881 && !(ifp->if_capenable & IFCAP_TSO6)) { 882 if (mask & IFCAP_TXCSUM_IPV6) 883 ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6; 884 else if (mask & IFCAP_TSO6) 885 ifp->if_capenable |= IFCAP_TSO6; 886 } else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 887 && (ifp->if_capenable & IFCAP_TSO6)) { 888 if (mask & IFCAP_TXCSUM_IPV6) { 889 vsi->flags |= IXL_FLAGS_KEEP_TSO6; 890 ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 891 device_printf(dev, 892 "TSO6 requires txcsum6, disabling both...\n"); 893 } else if (mask & IFCAP_TSO6) 894 ifp->if_capenable &= ~IFCAP_TSO6; 895 } 896} 897 898/********************************************************************* 899 * Ioctl entry point 900 * 901 * ixl_ioctl is called when the user wants to configure the 902 * interface. 903 * 904 * return 0 on success, positive on failure 905 **********************************************************************/ 906 907static int 908ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 909{ 910 struct ixl_vsi *vsi = ifp->if_softc; 911 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 912 struct ifreq *ifr = (struct ifreq *) data; 913#if defined(INET) || defined(INET6) 914 struct ifaddr *ifa = (struct ifaddr *)data; 915 bool avoid_reset = FALSE; 916#endif 917 int error = 0; 918 919 switch (command) { 920 921 case SIOCSIFADDR: 922#ifdef INET 923 if (ifa->ifa_addr->sa_family == AF_INET) 924 avoid_reset = TRUE; 925#endif 926#ifdef INET6 927 if (ifa->ifa_addr->sa_family == AF_INET6) 928 avoid_reset = TRUE; 929#endif 930#if defined(INET) || defined(INET6) 931 /* 932 ** Calling init results in link renegotiation, 933 ** so we avoid doing it when possible. 934 */ 935 if (avoid_reset) { 936 ifp->if_flags |= IFF_UP; 937 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 938 ixl_init(pf); 939#ifdef INET 940 if (!(ifp->if_flags & IFF_NOARP)) 941 arp_ifinit(ifp, ifa); 942#endif 943 } else 944 error = ether_ioctl(ifp, command, data); 945 break; 946#endif 947 case SIOCSIFMTU: 948 IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)"); 949 if (ifr->ifr_mtu > IXL_MAX_FRAME - 950 ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) { 951 error = EINVAL; 952 } else { 953 IXL_PF_LOCK(pf); 954 ifp->if_mtu = ifr->ifr_mtu; 955 vsi->max_frame_size = 956 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 957 + ETHER_VLAN_ENCAP_LEN; 958 ixl_init_locked(pf); 959 IXL_PF_UNLOCK(pf); 960 } 961 break; 962 case SIOCSIFFLAGS: 963 IOCTL_DEBUGOUT("ioctl: SIOCSIFFLAGS (Set Interface Flags)"); 964 IXL_PF_LOCK(pf); 965 if (ifp->if_flags & IFF_UP) { 966 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 967 if ((ifp->if_flags ^ pf->if_flags) & 968 (IFF_PROMISC | IFF_ALLMULTI)) { 969 ixl_set_promisc(vsi); 970 } 971 } else 972 ixl_init_locked(pf); 973 } else 974 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 975 ixl_stop(pf); 976 pf->if_flags = ifp->if_flags; 977 IXL_PF_UNLOCK(pf); 978 break; 979 case SIOCADDMULTI: 980 IOCTL_DEBUGOUT("ioctl: SIOCADDMULTI"); 981 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 982 IXL_PF_LOCK(pf); 983 ixl_disable_intr(vsi); 984 ixl_add_multi(vsi); 985 ixl_enable_intr(vsi); 986 IXL_PF_UNLOCK(pf); 987 } 988 break; 989 case SIOCDELMULTI: 990 IOCTL_DEBUGOUT("ioctl: SIOCDELMULTI"); 991 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 992 IXL_PF_LOCK(pf); 993 ixl_disable_intr(vsi); 994 ixl_del_multi(vsi); 995 ixl_enable_intr(vsi); 996 IXL_PF_UNLOCK(pf); 997 } 998 break; 999 case SIOCSIFMEDIA: 1000 case SIOCGIFMEDIA: 1001 IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)"); 1002 error = ifmedia_ioctl(ifp, ifr, &vsi->media, command); 1003 break; 1004 case SIOCSIFCAP: 1005 { 1006 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1007 IOCTL_DEBUGOUT("ioctl: SIOCSIFCAP (Set Capabilities)"); 1008 1009 ixl_cap_txcsum_tso(vsi, ifp, mask); 1010 1011 if (mask & IFCAP_RXCSUM) 1012 ifp->if_capenable ^= IFCAP_RXCSUM; 1013 if (mask & IFCAP_RXCSUM_IPV6) 1014 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1015 if (mask & IFCAP_LRO) 1016 ifp->if_capenable ^= IFCAP_LRO; 1017 if (mask & IFCAP_VLAN_HWTAGGING) 1018 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1019 if (mask & IFCAP_VLAN_HWFILTER) 1020 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 1021 if (mask & IFCAP_VLAN_HWTSO) 1022 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1023 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1024 IXL_PF_LOCK(pf); 1025 ixl_init_locked(pf); 1026 IXL_PF_UNLOCK(pf); 1027 } 1028 VLAN_CAPABILITIES(ifp); 1029 1030 break; 1031 } 1032 1033 default: 1034 IOCTL_DEBUGOUT("ioctl: UNKNOWN (0x%X)\n", (int)command); 1035 error = ether_ioctl(ifp, command, data); 1036 break; 1037 } 1038 1039 return (error); 1040} 1041 1042 1043/********************************************************************* 1044 * Init entry point 1045 * 1046 * This routine is used in two ways. It is used by the stack as 1047 * init entry point in network interface structure. It is also used 1048 * by the driver as a hw/sw initialization routine to get to a 1049 * consistent state. 1050 * 1051 * return 0 on success, positive on failure 1052 **********************************************************************/ 1053 1054static void 1055ixl_init_locked(struct ixl_pf *pf) 1056{ 1057 struct i40e_hw *hw = &pf->hw; 1058 struct ixl_vsi *vsi = &pf->vsi; 1059 struct ifnet *ifp = vsi->ifp; 1060 device_t dev = pf->dev; 1061 struct i40e_filter_control_settings filter; 1062 u8 tmpaddr[ETHER_ADDR_LEN]; 1063 int ret; 1064 1065 mtx_assert(&pf->pf_mtx, MA_OWNED); 1066 INIT_DEBUGOUT("ixl_init: begin"); 1067 ixl_stop(pf); 1068 1069 /* Get the latest mac address... User might use a LAA */ 1070 bcopy(IF_LLADDR(vsi->ifp), tmpaddr, 1071 I40E_ETH_LENGTH_OF_ADDRESS); 1072 if (!cmp_etheraddr(hw->mac.addr, tmpaddr) && 1073 i40e_validate_mac_addr(tmpaddr)) { 1074 bcopy(tmpaddr, hw->mac.addr, 1075 I40E_ETH_LENGTH_OF_ADDRESS); 1076 ret = i40e_aq_mac_address_write(hw, 1077 I40E_AQC_WRITE_TYPE_LAA_ONLY, 1078 hw->mac.addr, NULL); 1079 if (ret) { 1080 device_printf(dev, "LLA address" 1081 "change failed!!\n"); 1082 return; 1083 } 1084 } 1085 1086 /* Set the various hardware offload abilities */ 1087 ifp->if_hwassist = 0; 1088 if (ifp->if_capenable & IFCAP_TSO) 1089 ifp->if_hwassist |= CSUM_TSO; 1090 if (ifp->if_capenable & IFCAP_TXCSUM) 1091 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1092 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 1093 ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6); 1094 1095 /* Set up the device filtering */ 1096 bzero(&filter, sizeof(filter)); 1097 filter.enable_ethtype = TRUE; 1098 filter.enable_macvlan = TRUE; 1099#ifdef IXL_FDIR 1100 filter.enable_fdir = TRUE; 1101#endif 1102 if (i40e_set_filter_control(hw, &filter)) 1103 device_printf(dev, "set_filter_control() failed\n"); 1104 1105 /* Set up RSS */ 1106 ixl_config_rss(vsi); 1107 1108 /* 1109 ** Prepare the VSI: rings, hmc contexts, etc... 1110 */ 1111 if (ixl_initialize_vsi(vsi)) { 1112 device_printf(dev, "initialize vsi failed!!\n"); 1113 return; 1114 } 1115 1116 /* Add protocol filters to list */ 1117 ixl_init_filters(vsi); 1118 1119 /* Setup vlan's if needed */ 1120 ixl_setup_vlan_filters(vsi); 1121 1122 /* Start the local timer */ 1123 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1124 1125 /* Set up MSI/X routing and the ITR settings */ 1126 if (ixl_enable_msix) { 1127 ixl_configure_msix(pf); 1128 ixl_configure_itr(pf); 1129 } else 1130 ixl_configure_legacy(pf); 1131 1132 ixl_enable_rings(vsi); 1133 1134 i40e_aq_set_default_vsi(hw, vsi->seid, NULL); 1135 1136 /* Set MTU in hardware*/ 1137 int aq_error = i40e_aq_set_mac_config(hw, vsi->max_frame_size, 1138 TRUE, 0, NULL); 1139 if (aq_error) 1140 device_printf(vsi->dev, 1141 "aq_set_mac_config in init error, code %d\n", 1142 aq_error); 1143 1144 /* And now turn on interrupts */ 1145 ixl_enable_intr(vsi); 1146 1147 /* Now inform the stack we're ready */ 1148 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1149 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1150 1151 return; 1152} 1153 1154static void 1155ixl_init(void *arg) 1156{ 1157 struct ixl_pf *pf = arg; 1158 1159 IXL_PF_LOCK(pf); 1160 ixl_init_locked(pf); 1161 IXL_PF_UNLOCK(pf); 1162 return; 1163} 1164 1165/* 1166** 1167** MSIX Interrupt Handlers and Tasklets 1168** 1169*/ 1170static void 1171ixl_handle_que(void *context, int pending) 1172{ 1173 struct ixl_queue *que = context; 1174 struct ixl_vsi *vsi = que->vsi; 1175 struct i40e_hw *hw = vsi->hw; 1176 struct tx_ring *txr = &que->txr; 1177 struct ifnet *ifp = vsi->ifp; 1178 bool more; 1179 1180 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1181 more = ixl_rxeof(que, IXL_RX_LIMIT); 1182 IXL_TX_LOCK(txr); 1183 ixl_txeof(que); 1184 if (!drbr_empty(ifp, txr->br)) 1185 ixl_mq_start_locked(ifp, txr); 1186 IXL_TX_UNLOCK(txr); 1187 if (more) { 1188 taskqueue_enqueue(que->tq, &que->task); 1189 return; 1190 } 1191 } 1192 1193 /* Reenable this interrupt - hmmm */ 1194 ixl_enable_queue(hw, que->me); 1195 return; 1196} 1197 1198 1199/********************************************************************* 1200 * 1201 * Legacy Interrupt Service routine 1202 * 1203 **********************************************************************/ 1204void 1205ixl_intr(void *arg) 1206{ 1207 struct ixl_pf *pf = arg; 1208 struct i40e_hw *hw = &pf->hw; 1209 struct ixl_vsi *vsi = &pf->vsi; 1210 struct ixl_queue *que = vsi->queues; 1211 struct ifnet *ifp = vsi->ifp; 1212 struct tx_ring *txr = &que->txr; 1213 u32 reg, icr0, mask; 1214 bool more_tx, more_rx; 1215 1216 ++que->irqs; 1217 1218 /* Protect against spurious interrupts */ 1219 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1220 return; 1221 1222 icr0 = rd32(hw, I40E_PFINT_ICR0); 1223 1224 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1225 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1226 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1227 1228 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1229 1230 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 1231 taskqueue_enqueue(pf->tq, &pf->adminq); 1232 return; 1233 } 1234 1235 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1236 1237 IXL_TX_LOCK(txr); 1238 more_tx = ixl_txeof(que); 1239 if (!drbr_empty(vsi->ifp, txr->br)) 1240 more_tx = 1; 1241 IXL_TX_UNLOCK(txr); 1242 1243 /* re-enable other interrupt causes */ 1244 wr32(hw, I40E_PFINT_ICR0_ENA, mask); 1245 1246 /* And now the queues */ 1247 reg = rd32(hw, I40E_QINT_RQCTL(0)); 1248 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1249 wr32(hw, I40E_QINT_RQCTL(0), reg); 1250 1251 reg = rd32(hw, I40E_QINT_TQCTL(0)); 1252 reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1253 reg &= ~I40E_PFINT_ICR0_INTEVENT_MASK; 1254 wr32(hw, I40E_QINT_TQCTL(0), reg); 1255 1256 ixl_enable_legacy(hw); 1257 1258 return; 1259} 1260 1261 1262/********************************************************************* 1263 * 1264 * MSIX VSI Interrupt Service routine 1265 * 1266 **********************************************************************/ 1267void 1268ixl_msix_que(void *arg) 1269{ 1270 struct ixl_queue *que = arg; 1271 struct ixl_vsi *vsi = que->vsi; 1272 struct i40e_hw *hw = vsi->hw; 1273 struct tx_ring *txr = &que->txr; 1274 bool more_tx, more_rx; 1275 1276 /* Protect against spurious interrupts */ 1277 if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING)) 1278 return; 1279 1280 ++que->irqs; 1281 1282 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1283 1284 IXL_TX_LOCK(txr); 1285 more_tx = ixl_txeof(que); 1286 /* 1287 ** Make certain that if the stack 1288 ** has anything queued the task gets 1289 ** scheduled to handle it. 1290 */ 1291 if (!drbr_empty(vsi->ifp, txr->br)) 1292 more_tx = 1; 1293 IXL_TX_UNLOCK(txr); 1294 1295 ixl_set_queue_rx_itr(que); 1296 ixl_set_queue_tx_itr(que); 1297 1298 if (more_tx || more_rx) 1299 taskqueue_enqueue(que->tq, &que->task); 1300 else 1301 ixl_enable_queue(hw, que->me); 1302 1303 return; 1304} 1305 1306 1307/********************************************************************* 1308 * 1309 * MSIX Admin Queue Interrupt Service routine 1310 * 1311 **********************************************************************/ 1312static void 1313ixl_msix_adminq(void *arg) 1314{ 1315 struct ixl_pf *pf = arg; 1316 struct i40e_hw *hw = &pf->hw; 1317 u32 reg, mask; 1318 1319 ++pf->admin_irq; 1320 1321 reg = rd32(hw, I40E_PFINT_ICR0); 1322 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1323 1324 /* Check on the cause */ 1325 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) 1326 mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 1327 1328 if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 1329 ixl_handle_mdd_event(pf); 1330 mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 1331 } 1332 1333 if (reg & I40E_PFINT_ICR0_VFLR_MASK) 1334 mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; 1335 1336 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1337 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1338 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1339 1340 taskqueue_enqueue(pf->tq, &pf->adminq); 1341 return; 1342} 1343 1344/********************************************************************* 1345 * 1346 * Media Ioctl callback 1347 * 1348 * This routine is called whenever the user queries the status of 1349 * the interface using ifconfig. 1350 * 1351 **********************************************************************/ 1352static void 1353ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr) 1354{ 1355 struct ixl_vsi *vsi = ifp->if_softc; 1356 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 1357 struct i40e_hw *hw = &pf->hw; 1358 1359 INIT_DEBUGOUT("ixl_media_status: begin"); 1360 IXL_PF_LOCK(pf); 1361 1362 ixl_update_link_status(pf); 1363 1364 ifmr->ifm_status = IFM_AVALID; 1365 ifmr->ifm_active = IFM_ETHER; 1366 1367 if (!vsi->link_up) { 1368 IXL_PF_UNLOCK(pf); 1369 return; 1370 } 1371 1372 ifmr->ifm_status |= IFM_ACTIVE; 1373 /* Hardware is always full-duplex */ 1374 ifmr->ifm_active |= IFM_FDX; 1375 1376 switch (hw->phy.link_info.phy_type) { 1377 /* 100 M */ 1378 case I40E_PHY_TYPE_100BASE_TX: 1379 ifmr->ifm_active |= IFM_100_TX; 1380 break; 1381 /* 1 G */ 1382 case I40E_PHY_TYPE_1000BASE_T: 1383 ifmr->ifm_active |= IFM_1000_T; 1384 break; 1385 case I40E_PHY_TYPE_1000BASE_SX: 1386 ifmr->ifm_active |= IFM_1000_SX; 1387 break; 1388 case I40E_PHY_TYPE_1000BASE_LX: 1389 ifmr->ifm_active |= IFM_1000_LX; 1390 break; 1391 /* 10 G */ 1392 case I40E_PHY_TYPE_10GBASE_CR1: 1393 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1394 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1395 /* Using this until a real KR media type */ 1396 case I40E_PHY_TYPE_10GBASE_KR: 1397 case I40E_PHY_TYPE_10GBASE_KX4: 1398 ifmr->ifm_active |= IFM_10G_TWINAX; 1399 break; 1400 case I40E_PHY_TYPE_10GBASE_SR: 1401 ifmr->ifm_active |= IFM_10G_SR; 1402 break; 1403 case I40E_PHY_TYPE_10GBASE_LR: 1404 ifmr->ifm_active |= IFM_10G_LR; 1405 break; 1406 case I40E_PHY_TYPE_10GBASE_T: 1407 ifmr->ifm_active |= IFM_10G_T; 1408 break; 1409 /* 40 G */ 1410 case I40E_PHY_TYPE_40GBASE_CR4: 1411 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1412 ifmr->ifm_active |= IFM_40G_CR4; 1413 break; 1414 case I40E_PHY_TYPE_40GBASE_SR4: 1415 ifmr->ifm_active |= IFM_40G_SR4; 1416 break; 1417 case I40E_PHY_TYPE_40GBASE_LR4: 1418 ifmr->ifm_active |= IFM_40G_LR4; 1419 break; 1420 /* 1421 ** Set these to CR4 because OS does not 1422 ** have types available yet. 1423 */ 1424 case I40E_PHY_TYPE_40GBASE_KR4: 1425 case I40E_PHY_TYPE_XLAUI: 1426 case I40E_PHY_TYPE_XLPPI: 1427 case I40E_PHY_TYPE_40GBASE_AOC: 1428 ifmr->ifm_active |= IFM_40G_CR4; 1429 break; 1430 default: 1431 ifmr->ifm_active |= IFM_UNKNOWN; 1432 break; 1433 } 1434 /* Report flow control status as well */ 1435 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) 1436 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 1437 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) 1438 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 1439 1440 IXL_PF_UNLOCK(pf); 1441 1442 return; 1443} 1444 1445/********************************************************************* 1446 * 1447 * Media Ioctl callback 1448 * 1449 * This routine is called when the user changes speed/duplex using 1450 * media/mediopt option with ifconfig. 1451 * 1452 **********************************************************************/ 1453static int 1454ixl_media_change(struct ifnet * ifp) 1455{ 1456 struct ixl_vsi *vsi = ifp->if_softc; 1457 struct ifmedia *ifm = &vsi->media; 1458 1459 INIT_DEBUGOUT("ixl_media_change: begin"); 1460 1461 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1462 return (EINVAL); 1463 1464 if_printf(ifp, "Media change is currently not supported.\n"); 1465 1466 return (ENODEV); 1467} 1468 1469 1470#ifdef IXL_FDIR 1471/* 1472** ATR: Application Targetted Receive - creates a filter 1473** based on TX flow info that will keep the receive 1474** portion of the flow on the same queue. Based on the 1475** implementation this is only available for TCP connections 1476*/ 1477void 1478ixl_atr(struct ixl_queue *que, struct tcphdr *th, int etype) 1479{ 1480 struct ixl_vsi *vsi = que->vsi; 1481 struct tx_ring *txr = &que->txr; 1482 struct i40e_filter_program_desc *FDIR; 1483 u32 ptype, dtype; 1484 int idx; 1485 1486 /* check if ATR is enabled and sample rate */ 1487 if ((!ixl_enable_fdir) || (!txr->atr_rate)) 1488 return; 1489 /* 1490 ** We sample all TCP SYN/FIN packets, 1491 ** or at the selected sample rate 1492 */ 1493 txr->atr_count++; 1494 if (((th->th_flags & (TH_FIN | TH_SYN)) == 0) && 1495 (txr->atr_count < txr->atr_rate)) 1496 return; 1497 txr->atr_count = 0; 1498 1499 /* Get a descriptor to use */ 1500 idx = txr->next_avail; 1501 FDIR = (struct i40e_filter_program_desc *) &txr->base[idx]; 1502 if (++idx == que->num_desc) 1503 idx = 0; 1504 txr->avail--; 1505 txr->next_avail = idx; 1506 1507 ptype = (que->me << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 1508 I40E_TXD_FLTR_QW0_QINDEX_MASK; 1509 1510 ptype |= (etype == ETHERTYPE_IP) ? 1511 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 1512 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 1513 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 1514 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 1515 1516 ptype |= vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 1517 1518 dtype = I40E_TX_DESC_DTYPE_FILTER_PROG; 1519 1520 /* 1521 ** We use the TCP TH_FIN as a trigger to remove 1522 ** the filter, otherwise its an update. 1523 */ 1524 dtype |= (th->th_flags & TH_FIN) ? 1525 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 1526 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 1527 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 1528 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 1529 1530 dtype |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 1531 I40E_TXD_FLTR_QW1_DEST_SHIFT; 1532 1533 dtype |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 1534 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 1535 1536 FDIR->qindex_flex_ptype_vsi = htole32(ptype); 1537 FDIR->dtype_cmd_cntindex = htole32(dtype); 1538 return; 1539} 1540#endif 1541 1542 1543static void 1544ixl_set_promisc(struct ixl_vsi *vsi) 1545{ 1546 struct ifnet *ifp = vsi->ifp; 1547 struct i40e_hw *hw = vsi->hw; 1548 int err, mcnt = 0; 1549 bool uni = FALSE, multi = FALSE; 1550 1551 if (ifp->if_flags & IFF_ALLMULTI) 1552 multi = TRUE; 1553 else { /* Need to count the multicast addresses */ 1554 struct ifmultiaddr *ifma; 1555 if_maddr_rlock(ifp); 1556 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1557 if (ifma->ifma_addr->sa_family != AF_LINK) 1558 continue; 1559 if (mcnt == MAX_MULTICAST_ADDR) 1560 break; 1561 mcnt++; 1562 } 1563 if_maddr_runlock(ifp); 1564 } 1565 1566 if (mcnt >= MAX_MULTICAST_ADDR) 1567 multi = TRUE; 1568 if (ifp->if_flags & IFF_PROMISC) 1569 uni = TRUE; 1570 1571 err = i40e_aq_set_vsi_unicast_promiscuous(hw, 1572 vsi->seid, uni, NULL); 1573 err = i40e_aq_set_vsi_multicast_promiscuous(hw, 1574 vsi->seid, multi, NULL); 1575 return; 1576} 1577 1578/********************************************************************* 1579 * Filter Routines 1580 * 1581 * Routines for multicast and vlan filter management. 1582 * 1583 *********************************************************************/ 1584static void 1585ixl_add_multi(struct ixl_vsi *vsi) 1586{ 1587 struct ifmultiaddr *ifma; 1588 struct ifnet *ifp = vsi->ifp; 1589 struct i40e_hw *hw = vsi->hw; 1590 int mcnt = 0, flags; 1591 1592 IOCTL_DEBUGOUT("ixl_add_multi: begin"); 1593 1594 if_maddr_rlock(ifp); 1595 /* 1596 ** First just get a count, to decide if we 1597 ** we simply use multicast promiscuous. 1598 */ 1599 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1600 if (ifma->ifma_addr->sa_family != AF_LINK) 1601 continue; 1602 mcnt++; 1603 } 1604 if_maddr_runlock(ifp); 1605 1606 if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) { 1607 /* delete existing MC filters */ 1608 ixl_del_hw_filters(vsi, mcnt); 1609 i40e_aq_set_vsi_multicast_promiscuous(hw, 1610 vsi->seid, TRUE, NULL); 1611 return; 1612 } 1613 1614 mcnt = 0; 1615 if_maddr_rlock(ifp); 1616 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1617 if (ifma->ifma_addr->sa_family != AF_LINK) 1618 continue; 1619 ixl_add_mc_filter(vsi, 1620 (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 1621 mcnt++; 1622 } 1623 if_maddr_runlock(ifp); 1624 if (mcnt > 0) { 1625 flags = (IXL_FILTER_ADD | IXL_FILTER_USED | IXL_FILTER_MC); 1626 ixl_add_hw_filters(vsi, flags, mcnt); 1627 } 1628 1629 IOCTL_DEBUGOUT("ixl_add_multi: end"); 1630 return; 1631} 1632 1633static void 1634ixl_del_multi(struct ixl_vsi *vsi) 1635{ 1636 struct ifnet *ifp = vsi->ifp; 1637 struct ifmultiaddr *ifma; 1638 struct ixl_mac_filter *f; 1639 int mcnt = 0; 1640 bool match = FALSE; 1641 1642 IOCTL_DEBUGOUT("ixl_del_multi: begin"); 1643 1644 /* Search for removed multicast addresses */ 1645 if_maddr_rlock(ifp); 1646 SLIST_FOREACH(f, &vsi->ftl, next) { 1647 if ((f->flags & IXL_FILTER_USED) && (f->flags & IXL_FILTER_MC)) { 1648 match = FALSE; 1649 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1650 if (ifma->ifma_addr->sa_family != AF_LINK) 1651 continue; 1652 u8 *mc_addr = (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1653 if (cmp_etheraddr(f->macaddr, mc_addr)) { 1654 match = TRUE; 1655 break; 1656 } 1657 } 1658 if (match == FALSE) { 1659 f->flags |= IXL_FILTER_DEL; 1660 mcnt++; 1661 } 1662 } 1663 } 1664 if_maddr_runlock(ifp); 1665 1666 if (mcnt > 0) 1667 ixl_del_hw_filters(vsi, mcnt); 1668} 1669 1670 1671/********************************************************************* 1672 * Timer routine 1673 * 1674 * This routine checks for link status,updates statistics, 1675 * and runs the watchdog check. 1676 * 1677 **********************************************************************/ 1678 1679static void 1680ixl_local_timer(void *arg) 1681{ 1682 struct ixl_pf *pf = arg; 1683 struct i40e_hw *hw = &pf->hw; 1684 struct ixl_vsi *vsi = &pf->vsi; 1685 struct ixl_queue *que = vsi->queues; 1686 device_t dev = pf->dev; 1687 int hung = 0; 1688 u32 mask; 1689 1690 mtx_assert(&pf->pf_mtx, MA_OWNED); 1691 1692 /* Fire off the adminq task */ 1693 taskqueue_enqueue(pf->tq, &pf->adminq); 1694 1695 /* Update stats */ 1696 ixl_update_stats_counters(pf); 1697 1698 /* 1699 ** Check status of the queues 1700 */ 1701 mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK | 1702 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK); 1703 1704 for (int i = 0; i < vsi->num_queues; i++,que++) { 1705 /* Any queues with outstanding work get a sw irq */ 1706 if (que->busy) 1707 wr32(hw, I40E_PFINT_DYN_CTLN(que->me), mask); 1708 /* 1709 ** Each time txeof runs without cleaning, but there 1710 ** are uncleaned descriptors it increments busy. If 1711 ** we get to 5 we declare it hung. 1712 */ 1713 if (que->busy == IXL_QUEUE_HUNG) { 1714 ++hung; 1715 /* Mark the queue as inactive */ 1716 vsi->active_queues &= ~((u64)1 << que->me); 1717 continue; 1718 } else { 1719 /* Check if we've come back from hung */ 1720 if ((vsi->active_queues & ((u64)1 << que->me)) == 0) 1721 vsi->active_queues |= ((u64)1 << que->me); 1722 } 1723 if (que->busy >= IXL_MAX_TX_BUSY) { 1724#ifdef IXL_DEBUG 1725 device_printf(dev,"Warning queue %d " 1726 "appears to be hung!\n", i); 1727#endif 1728 que->busy = IXL_QUEUE_HUNG; 1729 ++hung; 1730 } 1731 } 1732 /* Only reinit if all queues show hung */ 1733 if (hung == vsi->num_queues) 1734 goto hung; 1735 1736 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1737 return; 1738 1739hung: 1740 device_printf(dev, "Local Timer: HANG DETECT - Resetting!!\n"); 1741 ixl_init_locked(pf); 1742} 1743 1744/* 1745** Note: this routine updates the OS on the link state 1746** the real check of the hardware only happens with 1747** a link interrupt. 1748*/ 1749static void 1750ixl_update_link_status(struct ixl_pf *pf) 1751{ 1752 struct ixl_vsi *vsi = &pf->vsi; 1753 struct i40e_hw *hw = &pf->hw; 1754 struct ifnet *ifp = vsi->ifp; 1755 device_t dev = pf->dev; 1756 1757 1758 if (vsi->link_up){ 1759 if (vsi->link_active == FALSE) { 1760 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1761 pf->fc = hw->fc.current_mode; 1762 if (bootverbose) { 1763 device_printf(dev,"Link is up %d Gbps %s," 1764 " Flow Control: %s\n", 1765 ((vsi->link_speed == I40E_LINK_SPEED_40GB)? 40:10), 1766 "Full Duplex", ixl_fc_string[pf->fc]); 1767 } 1768 vsi->link_active = TRUE; 1769 /* 1770 ** Warn user if link speed on NPAR enabled 1771 ** partition is not at least 10GB 1772 */ 1773 if (hw->func_caps.npar_enable && 1774 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB || 1775 hw->phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) 1776 device_printf(dev, "The partition detected link" 1777 "speed that is less than 10Gbps\n"); 1778 if_link_state_change(ifp, LINK_STATE_UP); 1779 } 1780 } else { /* Link down */ 1781 if (vsi->link_active == TRUE) { 1782 if (bootverbose) 1783 device_printf(dev,"Link is Down\n"); 1784 if_link_state_change(ifp, LINK_STATE_DOWN); 1785 vsi->link_active = FALSE; 1786 } 1787 } 1788 1789 return; 1790} 1791 1792/********************************************************************* 1793 * 1794 * This routine disables all traffic on the adapter by issuing a 1795 * global reset on the MAC and deallocates TX/RX buffers. 1796 * 1797 **********************************************************************/ 1798 1799static void 1800ixl_stop(struct ixl_pf *pf) 1801{ 1802 struct ixl_vsi *vsi = &pf->vsi; 1803 struct ifnet *ifp = vsi->ifp; 1804 1805 mtx_assert(&pf->pf_mtx, MA_OWNED); 1806 1807 INIT_DEBUGOUT("ixl_stop: begin\n"); 1808 ixl_disable_intr(vsi); 1809 ixl_disable_rings(vsi); 1810 1811 /* Tell the stack that the interface is no longer active */ 1812 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1813 1814 /* Stop the local timer */ 1815 callout_stop(&pf->timer); 1816 1817 return; 1818} 1819 1820 1821/********************************************************************* 1822 * 1823 * Setup MSIX Interrupt resources and handlers for the VSI 1824 * 1825 **********************************************************************/ 1826static int 1827ixl_assign_vsi_legacy(struct ixl_pf *pf) 1828{ 1829 device_t dev = pf->dev; 1830 struct ixl_vsi *vsi = &pf->vsi; 1831 struct ixl_queue *que = vsi->queues; 1832 int error, rid = 0; 1833 1834 if (pf->msix == 1) 1835 rid = 1; 1836 pf->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1837 &rid, RF_SHAREABLE | RF_ACTIVE); 1838 if (pf->res == NULL) { 1839 device_printf(dev,"Unable to allocate" 1840 " bus resource: vsi legacy/msi interrupt\n"); 1841 return (ENXIO); 1842 } 1843 1844 /* Set the handler function */ 1845 error = bus_setup_intr(dev, pf->res, 1846 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1847 ixl_intr, pf, &pf->tag); 1848 if (error) { 1849 pf->res = NULL; 1850 device_printf(dev, "Failed to register legacy/msi handler"); 1851 return (error); 1852 } 1853 bus_describe_intr(dev, pf->res, pf->tag, "irq0"); 1854 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1855 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1856 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1857 taskqueue_thread_enqueue, &que->tq); 1858 taskqueue_start_threads(&que->tq, 1, PI_NET, "%s que", 1859 device_get_nameunit(dev)); 1860 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1861 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1862 taskqueue_thread_enqueue, &pf->tq); 1863 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1864 device_get_nameunit(dev)); 1865 1866 return (0); 1867} 1868 1869 1870/********************************************************************* 1871 * 1872 * Setup MSIX Interrupt resources and handlers for the VSI 1873 * 1874 **********************************************************************/ 1875static int 1876ixl_assign_vsi_msix(struct ixl_pf *pf) 1877{ 1878 device_t dev = pf->dev; 1879 struct ixl_vsi *vsi = &pf->vsi; 1880 struct ixl_queue *que = vsi->queues; 1881 struct tx_ring *txr; 1882 int error, rid, vector = 0; 1883#ifdef RSS 1884 cpuset_t cpu_mask; 1885#endif 1886 1887 /* Admin Que is vector 0*/ 1888 rid = vector + 1; 1889 pf->res = bus_alloc_resource_any(dev, 1890 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 1891 if (!pf->res) { 1892 device_printf(dev,"Unable to allocate" 1893 " bus resource: Adminq interrupt [%d]\n", rid); 1894 return (ENXIO); 1895 } 1896 /* Set the adminq vector and handler */ 1897 error = bus_setup_intr(dev, pf->res, 1898 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1899 ixl_msix_adminq, pf, &pf->tag); 1900 if (error) { 1901 pf->res = NULL; 1902 device_printf(dev, "Failed to register Admin que handler"); 1903 return (error); 1904 } 1905 bus_describe_intr(dev, pf->res, pf->tag, "aq"); 1906 pf->admvec = vector; 1907 /* Tasklet for Admin Queue */ 1908 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1909 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1910 taskqueue_thread_enqueue, &pf->tq); 1911 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1912 device_get_nameunit(pf->dev)); 1913 ++vector; 1914 1915 /* Now set up the stations */ 1916 for (int i = 0; i < vsi->num_queues; i++, vector++, que++) { 1917 int cpu_id = i; 1918 rid = vector + 1; 1919 txr = &que->txr; 1920 que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1921 RF_SHAREABLE | RF_ACTIVE); 1922 if (que->res == NULL) { 1923 device_printf(dev,"Unable to allocate" 1924 " bus resource: que interrupt [%d]\n", vector); 1925 return (ENXIO); 1926 } 1927 /* Set the handler function */ 1928 error = bus_setup_intr(dev, que->res, 1929 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1930 ixl_msix_que, que, &que->tag); 1931 if (error) { 1932 que->res = NULL; 1933 device_printf(dev, "Failed to register que handler"); 1934 return (error); 1935 } 1936 bus_describe_intr(dev, que->res, que->tag, "q%d", i); 1937 /* Bind the vector to a CPU */ 1938#ifdef RSS 1939 cpu_id = rss_getcpu(i % rss_getnumbuckets()); 1940#endif 1941 bus_bind_intr(dev, que->res, cpu_id); 1942 que->msix = vector; 1943 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1944 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1945 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1946 taskqueue_thread_enqueue, &que->tq); 1947#ifdef RSS 1948 CPU_ZERO(&cpu_mask); 1949 CPU_SET(cpu_id, &cpu_mask); 1950 taskqueue_start_threads_cpuset(&que->tq, 1, PI_NET, 1951 &cpu_mask, "%s (bucket %d)", 1952 device_get_nameunit(dev), cpu_id); 1953#else 1954 taskqueue_start_threads(&que->tq, 1, PI_NET, 1955 "%s que", device_get_nameunit(dev)); 1956#endif 1957 } 1958 1959 return (0); 1960} 1961 1962 1963/* 1964 * Allocate MSI/X vectors 1965 */ 1966static int 1967ixl_init_msix(struct ixl_pf *pf) 1968{ 1969 device_t dev = pf->dev; 1970 int rid, want, vectors, queues, available; 1971 1972 /* Override by tuneable */ 1973 if (ixl_enable_msix == 0) 1974 goto msi; 1975 1976 /* 1977 ** When used in a virtualized environment 1978 ** PCI BUSMASTER capability may not be set 1979 ** so explicity set it here and rewrite 1980 ** the ENABLE in the MSIX control register 1981 ** at this point to cause the host to 1982 ** successfully initialize us. 1983 */ 1984 { 1985 u16 pci_cmd_word; 1986 int msix_ctrl; 1987 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1988 pci_cmd_word |= PCIM_CMD_BUSMASTEREN; 1989 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); 1990 pci_find_cap(dev, PCIY_MSIX, &rid); 1991 rid += PCIR_MSIX_CTRL; 1992 msix_ctrl = pci_read_config(dev, rid, 2); 1993 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1994 pci_write_config(dev, rid, msix_ctrl, 2); 1995 } 1996 1997 /* First try MSI/X */ 1998 rid = PCIR_BAR(IXL_BAR); 1999 pf->msix_mem = bus_alloc_resource_any(dev, 2000 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2001 if (!pf->msix_mem) { 2002 /* May not be enabled */ 2003 device_printf(pf->dev, 2004 "Unable to map MSIX table \n"); 2005 goto msi; 2006 } 2007 2008 available = pci_msix_count(dev); 2009 if (available == 0) { /* system has msix disabled */ 2010 bus_release_resource(dev, SYS_RES_MEMORY, 2011 rid, pf->msix_mem); 2012 pf->msix_mem = NULL; 2013 goto msi; 2014 } 2015 2016 /* Figure out a reasonable auto config value */ 2017 queues = (mp_ncpus > (available - 1)) ? (available - 1) : mp_ncpus; 2018 2019 /* Override with hardcoded value if sane */ 2020 if ((ixl_max_queues != 0) && (ixl_max_queues <= queues)) 2021 queues = ixl_max_queues; 2022 2023#ifdef RSS 2024 /* If we're doing RSS, clamp at the number of RSS buckets */ 2025 if (queues > rss_getnumbuckets()) 2026 queues = rss_getnumbuckets(); 2027#endif 2028 2029 /* 2030 ** Want one vector (RX/TX pair) per queue 2031 ** plus an additional for the admin queue. 2032 */ 2033 want = queues + 1; 2034 if (want <= available) /* Have enough */ 2035 vectors = want; 2036 else { 2037 device_printf(pf->dev, 2038 "MSIX Configuration Problem, " 2039 "%d vectors available but %d wanted!\n", 2040 available, want); 2041 return (0); /* Will go to Legacy setup */ 2042 } 2043 2044 if (pci_alloc_msix(dev, &vectors) == 0) { 2045 device_printf(pf->dev, 2046 "Using MSIX interrupts with %d vectors\n", vectors); 2047 pf->msix = vectors; 2048 pf->vsi.num_queues = queues; 2049#ifdef RSS 2050 /* 2051 * If we're doing RSS, the number of queues needs to 2052 * match the number of RSS buckets that are configured. 2053 * 2054 * + If there's more queues than RSS buckets, we'll end 2055 * up with queues that get no traffic. 2056 * 2057 * + If there's more RSS buckets than queues, we'll end 2058 * up having multiple RSS buckets map to the same queue, 2059 * so there'll be some contention. 2060 */ 2061 if (queues != rss_getnumbuckets()) { 2062 device_printf(dev, 2063 "%s: queues (%d) != RSS buckets (%d)" 2064 "; performance will be impacted.\n", 2065 __func__, queues, rss_getnumbuckets()); 2066 } 2067#endif 2068 return (vectors); 2069 } 2070msi: 2071 vectors = pci_msi_count(dev); 2072 pf->vsi.num_queues = 1; 2073 pf->msix = 1; 2074 ixl_max_queues = 1; 2075 ixl_enable_msix = 0; 2076 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) 2077 device_printf(pf->dev,"Using an MSI interrupt\n"); 2078 else { 2079 pf->msix = 0; 2080 device_printf(pf->dev,"Using a Legacy interrupt\n"); 2081 } 2082 return (vectors); 2083} 2084 2085 2086/* 2087 * Plumb MSI/X vectors 2088 */ 2089static void 2090ixl_configure_msix(struct ixl_pf *pf) 2091{ 2092 struct i40e_hw *hw = &pf->hw; 2093 struct ixl_vsi *vsi = &pf->vsi; 2094 u32 reg; 2095 u16 vector = 1; 2096 2097 /* First set up the adminq - vector 0 */ 2098 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 2099 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ 2100 2101 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 2102 I40E_PFINT_ICR0_ENA_GRST_MASK | 2103 I40E_PFINT_ICR0_HMC_ERR_MASK | 2104 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 2105 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 2106 I40E_PFINT_ICR0_ENA_VFLR_MASK | 2107 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK; 2108 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2109 2110 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 2111 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x003E); 2112 2113 wr32(hw, I40E_PFINT_DYN_CTL0, 2114 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | 2115 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); 2116 2117 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2118 2119 /* Next configure the queues */ 2120 for (int i = 0; i < vsi->num_queues; i++, vector++) { 2121 wr32(hw, I40E_PFINT_DYN_CTLN(i), i); 2122 wr32(hw, I40E_PFINT_LNKLSTN(i), i); 2123 2124 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 2125 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2126 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2127 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2128 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); 2129 wr32(hw, I40E_QINT_RQCTL(i), reg); 2130 2131 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 2132 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2133 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2134 ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2135 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2136 if (i == (vsi->num_queues - 1)) 2137 reg |= (IXL_QUEUE_EOL 2138 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2139 wr32(hw, I40E_QINT_TQCTL(i), reg); 2140 } 2141} 2142 2143/* 2144 * Configure for MSI single vector operation 2145 */ 2146static void 2147ixl_configure_legacy(struct ixl_pf *pf) 2148{ 2149 struct i40e_hw *hw = &pf->hw; 2150 u32 reg; 2151 2152 2153 wr32(hw, I40E_PFINT_ITR0(0), 0); 2154 wr32(hw, I40E_PFINT_ITR0(1), 0); 2155 2156 2157 /* Setup "other" causes */ 2158 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK 2159 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK 2160 | I40E_PFINT_ICR0_ENA_GRST_MASK 2161 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK 2162 | I40E_PFINT_ICR0_ENA_GPIO_MASK 2163 | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK 2164 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK 2165 | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK 2166 | I40E_PFINT_ICR0_ENA_VFLR_MASK 2167 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK 2168 ; 2169 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2170 2171 /* SW_ITR_IDX = 0, but don't change INTENA */ 2172 wr32(hw, I40E_PFINT_DYN_CTL0, 2173 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK | 2174 I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK); 2175 /* SW_ITR_IDX = 0, OTHER_ITR_IDX = 0 */ 2176 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2177 2178 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ 2179 wr32(hw, I40E_PFINT_LNKLST0, 0); 2180 2181 /* Associate the queue pair to the vector and enable the q int */ 2182 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK 2183 | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 2184 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2185 wr32(hw, I40E_QINT_RQCTL(0), reg); 2186 2187 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK 2188 | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 2189 | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2190 wr32(hw, I40E_QINT_TQCTL(0), reg); 2191 2192 /* Next enable the queue pair */ 2193 reg = rd32(hw, I40E_QTX_ENA(0)); 2194 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 2195 wr32(hw, I40E_QTX_ENA(0), reg); 2196 2197 reg = rd32(hw, I40E_QRX_ENA(0)); 2198 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 2199 wr32(hw, I40E_QRX_ENA(0), reg); 2200} 2201 2202 2203/* 2204 * Set the Initial ITR state 2205 */ 2206static void 2207ixl_configure_itr(struct ixl_pf *pf) 2208{ 2209 struct i40e_hw *hw = &pf->hw; 2210 struct ixl_vsi *vsi = &pf->vsi; 2211 struct ixl_queue *que = vsi->queues; 2212 2213 vsi->rx_itr_setting = ixl_rx_itr; 2214 if (ixl_dynamic_rx_itr) 2215 vsi->rx_itr_setting |= IXL_ITR_DYNAMIC; 2216 vsi->tx_itr_setting = ixl_tx_itr; 2217 if (ixl_dynamic_tx_itr) 2218 vsi->tx_itr_setting |= IXL_ITR_DYNAMIC; 2219 2220 for (int i = 0; i < vsi->num_queues; i++, que++) { 2221 struct tx_ring *txr = &que->txr; 2222 struct rx_ring *rxr = &que->rxr; 2223 2224 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), 2225 vsi->rx_itr_setting); 2226 rxr->itr = vsi->rx_itr_setting; 2227 rxr->latency = IXL_AVE_LATENCY; 2228 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), 2229 vsi->tx_itr_setting); 2230 txr->itr = vsi->tx_itr_setting; 2231 txr->latency = IXL_AVE_LATENCY; 2232 } 2233} 2234 2235 2236static int 2237ixl_allocate_pci_resources(struct ixl_pf *pf) 2238{ 2239 int rid; 2240 device_t dev = pf->dev; 2241 2242 rid = PCIR_BAR(0); 2243 pf->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2244 &rid, RF_ACTIVE); 2245 2246 if (!(pf->pci_mem)) { 2247 device_printf(dev,"Unable to allocate bus resource: memory\n"); 2248 return (ENXIO); 2249 } 2250 2251 pf->osdep.mem_bus_space_tag = 2252 rman_get_bustag(pf->pci_mem); 2253 pf->osdep.mem_bus_space_handle = 2254 rman_get_bushandle(pf->pci_mem); 2255 pf->osdep.mem_bus_space_size = rman_get_size(pf->pci_mem); 2256 pf->osdep.flush_reg = I40E_GLGEN_STAT; 2257 pf->hw.hw_addr = (u8 *) &pf->osdep.mem_bus_space_handle; 2258 2259 pf->hw.back = &pf->osdep; 2260 2261 /* 2262 ** Now setup MSI or MSI/X, should 2263 ** return us the number of supported 2264 ** vectors. (Will be 1 for MSI) 2265 */ 2266 pf->msix = ixl_init_msix(pf); 2267 return (0); 2268} 2269 2270static void 2271ixl_free_pci_resources(struct ixl_pf * pf) 2272{ 2273 struct ixl_vsi *vsi = &pf->vsi; 2274 struct ixl_queue *que = vsi->queues; 2275 device_t dev = pf->dev; 2276 int rid, memrid; 2277 2278 memrid = PCIR_BAR(IXL_BAR); 2279 2280 /* We may get here before stations are setup */ 2281 if ((!ixl_enable_msix) || (que == NULL)) 2282 goto early; 2283 2284 /* 2285 ** Release all msix VSI resources: 2286 */ 2287 for (int i = 0; i < vsi->num_queues; i++, que++) { 2288 rid = que->msix + 1; 2289 if (que->tag != NULL) { 2290 bus_teardown_intr(dev, que->res, que->tag); 2291 que->tag = NULL; 2292 } 2293 if (que->res != NULL) 2294 bus_release_resource(dev, SYS_RES_IRQ, rid, que->res); 2295 } 2296 2297early: 2298 /* Clean the AdminQ interrupt last */ 2299 if (pf->admvec) /* we are doing MSIX */ 2300 rid = pf->admvec + 1; 2301 else 2302 (pf->msix != 0) ? (rid = 1):(rid = 0); 2303 2304 if (pf->tag != NULL) { 2305 bus_teardown_intr(dev, pf->res, pf->tag); 2306 pf->tag = NULL; 2307 } 2308 if (pf->res != NULL) 2309 bus_release_resource(dev, SYS_RES_IRQ, rid, pf->res); 2310 2311 if (pf->msix) 2312 pci_release_msi(dev); 2313 2314 if (pf->msix_mem != NULL) 2315 bus_release_resource(dev, SYS_RES_MEMORY, 2316 memrid, pf->msix_mem); 2317 2318 if (pf->pci_mem != NULL) 2319 bus_release_resource(dev, SYS_RES_MEMORY, 2320 PCIR_BAR(0), pf->pci_mem); 2321 2322 return; 2323} 2324 2325static void 2326ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type) 2327{ 2328 /* Display supported media types */ 2329 if (phy_type & (1 << I40E_PHY_TYPE_100BASE_TX)) 2330 ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2331 2332 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_T)) 2333 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2334 2335 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) || 2336 phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4) || 2337 phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR) || 2338 phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) || 2339 phy_type & (1 << I40E_PHY_TYPE_XAUI) || 2340 phy_type & (1 << I40E_PHY_TYPE_XFI) || 2341 phy_type & (1 << I40E_PHY_TYPE_SFI) || 2342 phy_type & (1 << I40E_PHY_TYPE_10GBASE_SFPP_CU)) 2343 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2344 2345 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_SR)) 2346 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2347 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_LR)) 2348 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 2349 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_T)) 2350 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_T, 0, NULL); 2351 2352 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4) || 2353 phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4_CU) || 2354 phy_type & (1 << I40E_PHY_TYPE_40GBASE_AOC) || 2355 phy_type & (1 << I40E_PHY_TYPE_XLAUI) || 2356 phy_type & (1 << I40E_PHY_TYPE_XLPPI) || 2357 /* KR4 uses CR4 until the OS has the real media type */ 2358 phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2359 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2360 2361 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_SR4)) 2362 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2363 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_LR4)) 2364 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL); 2365} 2366 2367/********************************************************************* 2368 * 2369 * Setup networking device structure and register an interface. 2370 * 2371 **********************************************************************/ 2372static int 2373ixl_setup_interface(device_t dev, struct ixl_vsi *vsi) 2374{ 2375 struct ifnet *ifp; 2376 struct i40e_hw *hw = vsi->hw; 2377 struct ixl_queue *que = vsi->queues; 2378 struct i40e_aq_get_phy_abilities_resp abilities; 2379 enum i40e_status_code aq_error = 0; 2380 2381 INIT_DEBUGOUT("ixl_setup_interface: begin"); 2382 2383 ifp = vsi->ifp = if_alloc(IFT_ETHER); 2384 if (ifp == NULL) { 2385 device_printf(dev, "can not allocate ifnet structure\n"); 2386 return (-1); 2387 } 2388 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2389 ifp->if_mtu = ETHERMTU; 2390 ifp->if_baudrate = 4000000000; // ?? 2391 ifp->if_init = ixl_init; 2392 ifp->if_softc = vsi; 2393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2394 ifp->if_ioctl = ixl_ioctl; 2395 2396#if __FreeBSD_version >= 1100036 2397 if_setgetcounterfn(ifp, ixl_get_counter); 2398#endif 2399 2400 ifp->if_transmit = ixl_mq_start; 2401 2402 ifp->if_qflush = ixl_qflush; 2403 2404 ifp->if_snd.ifq_maxlen = que->num_desc - 2; 2405 2406 vsi->max_frame_size = 2407 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 2408 + ETHER_VLAN_ENCAP_LEN; 2409 2410 /* 2411 * Tell the upper layer(s) we support long frames. 2412 */ 2413 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2414 2415 ifp->if_capabilities |= IFCAP_HWCSUM; 2416 ifp->if_capabilities |= IFCAP_HWCSUM_IPV6; 2417 ifp->if_capabilities |= IFCAP_TSO; 2418 ifp->if_capabilities |= IFCAP_JUMBO_MTU; 2419 ifp->if_capabilities |= IFCAP_LRO; 2420 2421 /* VLAN capabilties */ 2422 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING 2423 | IFCAP_VLAN_HWTSO 2424 | IFCAP_VLAN_MTU 2425 | IFCAP_VLAN_HWCSUM; 2426 ifp->if_capenable = ifp->if_capabilities; 2427 2428 /* 2429 ** Don't turn this on by default, if vlans are 2430 ** created on another pseudo device (eg. lagg) 2431 ** then vlan events are not passed thru, breaking 2432 ** operation, but with HW FILTER off it works. If 2433 ** using vlans directly on the ixl driver you can 2434 ** enable this and get full hardware tag filtering. 2435 */ 2436 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER; 2437 2438 /* 2439 * Specify the media types supported by this adapter and register 2440 * callbacks to update media and link information 2441 */ 2442 ifmedia_init(&vsi->media, IFM_IMASK, ixl_media_change, 2443 ixl_media_status); 2444 2445 aq_error = i40e_aq_get_phy_capabilities(hw, 2446 FALSE, TRUE, &abilities, NULL); 2447 /* May need delay to detect fiber correctly */ 2448 if (aq_error == I40E_ERR_UNKNOWN_PHY) { 2449 i40e_msec_delay(200); 2450 aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, 2451 TRUE, &abilities, NULL); 2452 } 2453 if (aq_error) { 2454 if (aq_error == I40E_ERR_UNKNOWN_PHY) 2455 device_printf(dev, "Unknown PHY type detected!\n"); 2456 else 2457 device_printf(dev, 2458 "Error getting supported media types, err %d," 2459 " AQ error %d\n", aq_error, hw->aq.asq_last_status); 2460 return (0); 2461 } 2462 2463 ixl_add_ifmedia(vsi, abilities.phy_type); 2464 2465 /* Use autoselect media by default */ 2466 ifmedia_add(&vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2467 ifmedia_set(&vsi->media, IFM_ETHER | IFM_AUTO); 2468 2469 ether_ifattach(ifp, hw->mac.addr); 2470 2471 return (0); 2472} 2473 2474static bool 2475ixl_config_link(struct i40e_hw *hw) 2476{ 2477 bool check; 2478 2479 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2480 check = i40e_get_link_status(hw); 2481#ifdef IXL_DEBUG 2482 printf("Link is %s\n", check ? "up":"down"); 2483#endif 2484 return (check); 2485} 2486 2487/********************************************************************* 2488 * 2489 * Get Firmware Switch configuration 2490 * - this will need to be more robust when more complex 2491 * switch configurations are enabled. 2492 * 2493 **********************************************************************/ 2494static int 2495ixl_switch_config(struct ixl_pf *pf) 2496{ 2497 struct i40e_hw *hw = &pf->hw; 2498 struct ixl_vsi *vsi = &pf->vsi; 2499 device_t dev = vsi->dev; 2500 struct i40e_aqc_get_switch_config_resp *sw_config; 2501 u8 aq_buf[I40E_AQ_LARGE_BUF]; 2502 int ret = I40E_SUCCESS; 2503 u16 next = 0; 2504 2505 memset(&aq_buf, 0, sizeof(aq_buf)); 2506 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 2507 ret = i40e_aq_get_switch_config(hw, sw_config, 2508 sizeof(aq_buf), &next, NULL); 2509 if (ret) { 2510 device_printf(dev,"aq_get_switch_config failed!!\n"); 2511 return (ret); 2512 } 2513#ifdef IXL_DEBUG 2514 printf("Switch config: header reported: %d in structure, %d total\n", 2515 sw_config->header.num_reported, sw_config->header.num_total); 2516 printf("type=%d seid=%d uplink=%d downlink=%d\n", 2517 sw_config->element[0].element_type, 2518 sw_config->element[0].seid, 2519 sw_config->element[0].uplink_seid, 2520 sw_config->element[0].downlink_seid); 2521#endif 2522 /* Simplified due to a single VSI at the moment */ 2523 vsi->seid = sw_config->element[0].seid; 2524 return (ret); 2525} 2526 2527/********************************************************************* 2528 * 2529 * Initialize the VSI: this handles contexts, which means things 2530 * like the number of descriptors, buffer size, 2531 * plus we init the rings thru this function. 2532 * 2533 **********************************************************************/ 2534static int 2535ixl_initialize_vsi(struct ixl_vsi *vsi) 2536{ 2537 struct ixl_queue *que = vsi->queues; 2538 device_t dev = vsi->dev; 2539 struct i40e_hw *hw = vsi->hw; 2540 struct i40e_vsi_context ctxt; 2541 int err = 0; 2542 2543 memset(&ctxt, 0, sizeof(ctxt)); 2544 ctxt.seid = vsi->seid; 2545 ctxt.pf_num = hw->pf_id; 2546 err = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 2547 if (err) { 2548 device_printf(dev,"get vsi params failed %x!!\n", err); 2549 return (err); 2550 } 2551#ifdef IXL_DEBUG 2552 printf("get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, " 2553 "vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, " 2554 "pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid, 2555 ctxt.uplink_seid, ctxt.vsi_number, 2556 ctxt.vsis_allocated, ctxt.vsis_unallocated, 2557 ctxt.flags, ctxt.pf_num, ctxt.vf_num, 2558 ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits); 2559#endif 2560 /* 2561 ** Set the queue and traffic class bits 2562 ** - when multiple traffic classes are supported 2563 ** this will need to be more robust. 2564 */ 2565 ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; 2566 ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG; 2567 ctxt.info.queue_mapping[0] = 0; 2568 ctxt.info.tc_mapping[0] = 0x0800; 2569 2570 /* Set VLAN receive stripping mode */ 2571 ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID; 2572 ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL; 2573 if (vsi->ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2574 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 2575 else 2576 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 2577 2578 /* Keep copy of VSI info in VSI for statistic counters */ 2579 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 2580 2581 /* Reset VSI statistics */ 2582 ixl_vsi_reset_stats(vsi); 2583 vsi->hw_filters_add = 0; 2584 vsi->hw_filters_del = 0; 2585 2586 err = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 2587 if (err) { 2588 device_printf(dev,"update vsi params failed %x!!\n", 2589 hw->aq.asq_last_status); 2590 return (err); 2591 } 2592 2593 for (int i = 0; i < vsi->num_queues; i++, que++) { 2594 struct tx_ring *txr = &que->txr; 2595 struct rx_ring *rxr = &que->rxr; 2596 struct i40e_hmc_obj_txq tctx; 2597 struct i40e_hmc_obj_rxq rctx; 2598 u32 txctl; 2599 u16 size; 2600 2601 2602 /* Setup the HMC TX Context */ 2603 size = que->num_desc * sizeof(struct i40e_tx_desc); 2604 memset(&tctx, 0, sizeof(struct i40e_hmc_obj_txq)); 2605 tctx.new_context = 1; 2606 tctx.base = (txr->dma.pa/128); 2607 tctx.qlen = que->num_desc; 2608 tctx.fc_ena = 0; 2609 tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */ 2610 /* Enable HEAD writeback */ 2611 tctx.head_wb_ena = 1; 2612 tctx.head_wb_addr = txr->dma.pa + 2613 (que->num_desc * sizeof(struct i40e_tx_desc)); 2614 tctx.rdylist_act = 0; 2615 err = i40e_clear_lan_tx_queue_context(hw, i); 2616 if (err) { 2617 device_printf(dev, "Unable to clear TX context\n"); 2618 break; 2619 } 2620 err = i40e_set_lan_tx_queue_context(hw, i, &tctx); 2621 if (err) { 2622 device_printf(dev, "Unable to set TX context\n"); 2623 break; 2624 } 2625 /* Associate the ring with this PF */ 2626 txctl = I40E_QTX_CTL_PF_QUEUE; 2627 txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 2628 I40E_QTX_CTL_PF_INDX_MASK); 2629 wr32(hw, I40E_QTX_CTL(i), txctl); 2630 ixl_flush(hw); 2631 2632 /* Do ring (re)init */ 2633 ixl_init_tx_ring(que); 2634 2635 /* Next setup the HMC RX Context */ 2636 if (vsi->max_frame_size <= 2048) 2637 rxr->mbuf_sz = MCLBYTES; 2638 else 2639 rxr->mbuf_sz = MJUMPAGESIZE; 2640 2641 u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len; 2642 2643 /* Set up an RX context for the HMC */ 2644 memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq)); 2645 rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT; 2646 /* ignore header split for now */ 2647 rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT; 2648 rctx.rxmax = (vsi->max_frame_size < max_rxmax) ? 2649 vsi->max_frame_size : max_rxmax; 2650 rctx.dtype = 0; 2651 rctx.dsize = 1; /* do 32byte descriptors */ 2652 rctx.hsplit_0 = 0; /* no HDR split initially */ 2653 rctx.base = (rxr->dma.pa/128); 2654 rctx.qlen = que->num_desc; 2655 rctx.tphrdesc_ena = 1; 2656 rctx.tphwdesc_ena = 1; 2657 rctx.tphdata_ena = 0; 2658 rctx.tphhead_ena = 0; 2659 rctx.lrxqthresh = 2; 2660 rctx.crcstrip = 1; 2661 rctx.l2tsel = 1; 2662 rctx.showiv = 1; 2663 rctx.fc_ena = 0; 2664 rctx.prefena = 1; 2665 2666 err = i40e_clear_lan_rx_queue_context(hw, i); 2667 if (err) { 2668 device_printf(dev, 2669 "Unable to clear RX context %d\n", i); 2670 break; 2671 } 2672 err = i40e_set_lan_rx_queue_context(hw, i, &rctx); 2673 if (err) { 2674 device_printf(dev, "Unable to set RX context %d\n", i); 2675 break; 2676 } 2677 err = ixl_init_rx_ring(que); 2678 if (err) { 2679 device_printf(dev, "Fail in init_rx_ring %d\n", i); 2680 break; 2681 } 2682 wr32(vsi->hw, I40E_QRX_TAIL(que->me), 0); 2683#ifdef DEV_NETMAP 2684 /* preserve queue */ 2685 if (vsi->ifp->if_capenable & IFCAP_NETMAP) { 2686 struct netmap_adapter *na = NA(vsi->ifp); 2687 struct netmap_kring *kring = &na->rx_rings[i]; 2688 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 2689 wr32(vsi->hw, I40E_QRX_TAIL(que->me), t); 2690 } else 2691#endif /* DEV_NETMAP */ 2692 wr32(vsi->hw, I40E_QRX_TAIL(que->me), que->num_desc - 1); 2693 } 2694 return (err); 2695} 2696 2697 2698/********************************************************************* 2699 * 2700 * Free all VSI structs. 2701 * 2702 **********************************************************************/ 2703void 2704ixl_free_vsi(struct ixl_vsi *vsi) 2705{ 2706 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 2707 struct ixl_queue *que = vsi->queues; 2708 struct ixl_mac_filter *f; 2709 2710 /* Free station queues */ 2711 for (int i = 0; i < vsi->num_queues; i++, que++) { 2712 struct tx_ring *txr = &que->txr; 2713 struct rx_ring *rxr = &que->rxr; 2714 2715 if (!mtx_initialized(&txr->mtx)) /* uninitialized */ 2716 continue; 2717 IXL_TX_LOCK(txr); 2718 ixl_free_que_tx(que); 2719 if (txr->base) 2720 i40e_free_dma_mem(&pf->hw, &txr->dma); 2721 IXL_TX_UNLOCK(txr); 2722 IXL_TX_LOCK_DESTROY(txr); 2723 2724 if (!mtx_initialized(&rxr->mtx)) /* uninitialized */ 2725 continue; 2726 IXL_RX_LOCK(rxr); 2727 ixl_free_que_rx(que); 2728 if (rxr->base) 2729 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2730 IXL_RX_UNLOCK(rxr); 2731 IXL_RX_LOCK_DESTROY(rxr); 2732 2733 } 2734 free(vsi->queues, M_DEVBUF); 2735 2736 /* Free VSI filter list */ 2737 while (!SLIST_EMPTY(&vsi->ftl)) { 2738 f = SLIST_FIRST(&vsi->ftl); 2739 SLIST_REMOVE_HEAD(&vsi->ftl, next); 2740 free(f, M_DEVBUF); 2741 } 2742} 2743 2744 2745/********************************************************************* 2746 * 2747 * Allocate memory for the VSI (virtual station interface) and their 2748 * associated queues, rings and the descriptors associated with each, 2749 * called only once at attach. 2750 * 2751 **********************************************************************/ 2752static int 2753ixl_setup_stations(struct ixl_pf *pf) 2754{ 2755 device_t dev = pf->dev; 2756 struct ixl_vsi *vsi; 2757 struct ixl_queue *que; 2758 struct tx_ring *txr; 2759 struct rx_ring *rxr; 2760 int rsize, tsize; 2761 int error = I40E_SUCCESS; 2762 2763 vsi = &pf->vsi; 2764 vsi->back = (void *)pf; 2765 vsi->hw = &pf->hw; 2766 vsi->id = 0; 2767 vsi->num_vlans = 0; 2768 2769 /* Get memory for the station queues */ 2770 if (!(vsi->queues = 2771 (struct ixl_queue *) malloc(sizeof(struct ixl_queue) * 2772 vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2773 device_printf(dev, "Unable to allocate queue memory\n"); 2774 error = ENOMEM; 2775 goto early; 2776 } 2777 2778 for (int i = 0; i < vsi->num_queues; i++) { 2779 que = &vsi->queues[i]; 2780 que->num_desc = ixl_ringsz; 2781 que->me = i; 2782 que->vsi = vsi; 2783 /* mark the queue as active */ 2784 vsi->active_queues |= (u64)1 << que->me; 2785 txr = &que->txr; 2786 txr->que = que; 2787 txr->tail = I40E_QTX_TAIL(que->me); 2788 2789 /* Initialize the TX lock */ 2790 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 2791 device_get_nameunit(dev), que->me); 2792 mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF); 2793 /* Create the TX descriptor ring */ 2794 tsize = roundup2((que->num_desc * 2795 sizeof(struct i40e_tx_desc)) + 2796 sizeof(u32), DBA_ALIGN); 2797 if (i40e_allocate_dma_mem(&pf->hw, 2798 &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) { 2799 device_printf(dev, 2800 "Unable to allocate TX Descriptor memory\n"); 2801 error = ENOMEM; 2802 goto fail; 2803 } 2804 txr->base = (struct i40e_tx_desc *)txr->dma.va; 2805 bzero((void *)txr->base, tsize); 2806 /* Now allocate transmit soft structs for the ring */ 2807 if (ixl_allocate_tx_data(que)) { 2808 device_printf(dev, 2809 "Critical Failure setting up TX structures\n"); 2810 error = ENOMEM; 2811 goto fail; 2812 } 2813 /* Allocate a buf ring */ 2814 txr->br = buf_ring_alloc(4096, M_DEVBUF, 2815 M_WAITOK, &txr->mtx); 2816 if (txr->br == NULL) { 2817 device_printf(dev, 2818 "Critical Failure setting up TX buf ring\n"); 2819 error = ENOMEM; 2820 goto fail; 2821 } 2822 2823 /* 2824 * Next the RX queues... 2825 */ 2826 rsize = roundup2(que->num_desc * 2827 sizeof(union i40e_rx_desc), DBA_ALIGN); 2828 rxr = &que->rxr; 2829 rxr->que = que; 2830 rxr->tail = I40E_QRX_TAIL(que->me); 2831 2832 /* Initialize the RX side lock */ 2833 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 2834 device_get_nameunit(dev), que->me); 2835 mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF); 2836 2837 if (i40e_allocate_dma_mem(&pf->hw, 2838 &rxr->dma, i40e_mem_reserved, rsize, 4096)) { 2839 device_printf(dev, 2840 "Unable to allocate RX Descriptor memory\n"); 2841 error = ENOMEM; 2842 goto fail; 2843 } 2844 rxr->base = (union i40e_rx_desc *)rxr->dma.va; 2845 bzero((void *)rxr->base, rsize); 2846 2847 /* Allocate receive soft structs for the ring*/ 2848 if (ixl_allocate_rx_data(que)) { 2849 device_printf(dev, 2850 "Critical Failure setting up receive structs\n"); 2851 error = ENOMEM; 2852 goto fail; 2853 } 2854 } 2855 2856 return (0); 2857 2858fail: 2859 for (int i = 0; i < vsi->num_queues; i++) { 2860 que = &vsi->queues[i]; 2861 rxr = &que->rxr; 2862 txr = &que->txr; 2863 if (rxr->base) 2864 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2865 if (txr->base) 2866 i40e_free_dma_mem(&pf->hw, &txr->dma); 2867 } 2868 2869early: 2870 return (error); 2871} 2872 2873/* 2874** Provide a update to the queue RX 2875** interrupt moderation value. 2876*/ 2877static void 2878ixl_set_queue_rx_itr(struct ixl_queue *que) 2879{ 2880 struct ixl_vsi *vsi = que->vsi; 2881 struct i40e_hw *hw = vsi->hw; 2882 struct rx_ring *rxr = &que->rxr; 2883 u16 rx_itr; 2884 u16 rx_latency = 0; 2885 int rx_bytes; 2886 2887 2888 /* Idle, do nothing */ 2889 if (rxr->bytes == 0) 2890 return; 2891 2892 if (ixl_dynamic_rx_itr) { 2893 rx_bytes = rxr->bytes/rxr->itr; 2894 rx_itr = rxr->itr; 2895 2896 /* Adjust latency range */ 2897 switch (rxr->latency) { 2898 case IXL_LOW_LATENCY: 2899 if (rx_bytes > 10) { 2900 rx_latency = IXL_AVE_LATENCY; 2901 rx_itr = IXL_ITR_20K; 2902 } 2903 break; 2904 case IXL_AVE_LATENCY: 2905 if (rx_bytes > 20) { 2906 rx_latency = IXL_BULK_LATENCY; 2907 rx_itr = IXL_ITR_8K; 2908 } else if (rx_bytes <= 10) { 2909 rx_latency = IXL_LOW_LATENCY; 2910 rx_itr = IXL_ITR_100K; 2911 } 2912 break; 2913 case IXL_BULK_LATENCY: 2914 if (rx_bytes <= 20) { 2915 rx_latency = IXL_AVE_LATENCY; 2916 rx_itr = IXL_ITR_20K; 2917 } 2918 break; 2919 } 2920 2921 rxr->latency = rx_latency; 2922 2923 if (rx_itr != rxr->itr) { 2924 /* do an exponential smoothing */ 2925 rx_itr = (10 * rx_itr * rxr->itr) / 2926 ((9 * rx_itr) + rxr->itr); 2927 rxr->itr = rx_itr & IXL_MAX_ITR; 2928 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 2929 que->me), rxr->itr); 2930 } 2931 } else { /* We may have have toggled to non-dynamic */ 2932 if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC) 2933 vsi->rx_itr_setting = ixl_rx_itr; 2934 /* Update the hardware if needed */ 2935 if (rxr->itr != vsi->rx_itr_setting) { 2936 rxr->itr = vsi->rx_itr_setting; 2937 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 2938 que->me), rxr->itr); 2939 } 2940 } 2941 rxr->bytes = 0; 2942 rxr->packets = 0; 2943 return; 2944} 2945 2946 2947/* 2948** Provide a update to the queue TX 2949** interrupt moderation value. 2950*/ 2951static void 2952ixl_set_queue_tx_itr(struct ixl_queue *que) 2953{ 2954 struct ixl_vsi *vsi = que->vsi; 2955 struct i40e_hw *hw = vsi->hw; 2956 struct tx_ring *txr = &que->txr; 2957 u16 tx_itr; 2958 u16 tx_latency = 0; 2959 int tx_bytes; 2960 2961 2962 /* Idle, do nothing */ 2963 if (txr->bytes == 0) 2964 return; 2965 2966 if (ixl_dynamic_tx_itr) { 2967 tx_bytes = txr->bytes/txr->itr; 2968 tx_itr = txr->itr; 2969 2970 switch (txr->latency) { 2971 case IXL_LOW_LATENCY: 2972 if (tx_bytes > 10) { 2973 tx_latency = IXL_AVE_LATENCY; 2974 tx_itr = IXL_ITR_20K; 2975 } 2976 break; 2977 case IXL_AVE_LATENCY: 2978 if (tx_bytes > 20) { 2979 tx_latency = IXL_BULK_LATENCY; 2980 tx_itr = IXL_ITR_8K; 2981 } else if (tx_bytes <= 10) { 2982 tx_latency = IXL_LOW_LATENCY; 2983 tx_itr = IXL_ITR_100K; 2984 } 2985 break; 2986 case IXL_BULK_LATENCY: 2987 if (tx_bytes <= 20) { 2988 tx_latency = IXL_AVE_LATENCY; 2989 tx_itr = IXL_ITR_20K; 2990 } 2991 break; 2992 } 2993 2994 txr->latency = tx_latency; 2995 2996 if (tx_itr != txr->itr) { 2997 /* do an exponential smoothing */ 2998 tx_itr = (10 * tx_itr * txr->itr) / 2999 ((9 * tx_itr) + txr->itr); 3000 txr->itr = tx_itr & IXL_MAX_ITR; 3001 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3002 que->me), txr->itr); 3003 } 3004 3005 } else { /* We may have have toggled to non-dynamic */ 3006 if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC) 3007 vsi->tx_itr_setting = ixl_tx_itr; 3008 /* Update the hardware if needed */ 3009 if (txr->itr != vsi->tx_itr_setting) { 3010 txr->itr = vsi->tx_itr_setting; 3011 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3012 que->me), txr->itr); 3013 } 3014 } 3015 txr->bytes = 0; 3016 txr->packets = 0; 3017 return; 3018} 3019 3020 3021static void 3022ixl_add_hw_stats(struct ixl_pf *pf) 3023{ 3024 device_t dev = pf->dev; 3025 struct ixl_vsi *vsi = &pf->vsi; 3026 struct ixl_queue *queues = vsi->queues; 3027 struct i40e_eth_stats *vsi_stats = &vsi->eth_stats; 3028 struct i40e_hw_port_stats *pf_stats = &pf->stats; 3029 3030 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3031 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3032 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3033 3034 struct sysctl_oid *vsi_node, *queue_node; 3035 struct sysctl_oid_list *vsi_list, *queue_list; 3036 3037 struct tx_ring *txr; 3038 struct rx_ring *rxr; 3039 3040 /* Driver statistics */ 3041 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 3042 CTLFLAG_RD, &pf->watchdog_events, 3043 "Watchdog timeouts"); 3044 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq", 3045 CTLFLAG_RD, &pf->admin_irq, 3046 "Admin Queue IRQ Handled"); 3047 3048 /* VSI statistics */ 3049#define QUEUE_NAME_LEN 32 3050 char queue_namebuf[QUEUE_NAME_LEN]; 3051 3052 // ERJ: Only one vsi now, re-do when >1 VSI enabled 3053 // snprintf(vsi_namebuf, QUEUE_NAME_LEN, "vsi%d", vsi->info.stat_counter_idx); 3054 vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "vsi", 3055 CTLFLAG_RD, NULL, "VSI-specific stats"); 3056 vsi_list = SYSCTL_CHILDREN(vsi_node); 3057 3058 ixl_add_sysctls_eth_stats(ctx, vsi_list, vsi_stats); 3059 3060 /* Queue statistics */ 3061 for (int q = 0; q < vsi->num_queues; q++) { 3062 snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q); 3063 queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, OID_AUTO, queue_namebuf, 3064 CTLFLAG_RD, NULL, "Queue #"); 3065 queue_list = SYSCTL_CHILDREN(queue_node); 3066 3067 txr = &(queues[q].txr); 3068 rxr = &(queues[q].rxr); 3069 3070 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed", 3071 CTLFLAG_RD, &(queues[q].mbuf_defrag_failed), 3072 "m_defrag() failed"); 3073 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "dropped", 3074 CTLFLAG_RD, &(queues[q].dropped_pkts), 3075 "Driver dropped packets"); 3076 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 3077 CTLFLAG_RD, &(queues[q].irqs), 3078 "irqs on this queue"); 3079 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 3080 CTLFLAG_RD, &(queues[q].tso), 3081 "TSO"); 3082 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dma_setup", 3083 CTLFLAG_RD, &(queues[q].tx_dma_setup), 3084 "Driver tx dma failure in xmit"); 3085 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail", 3086 CTLFLAG_RD, &(txr->no_desc), 3087 "Queue No Descriptor Available"); 3088 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 3089 CTLFLAG_RD, &(txr->total_packets), 3090 "Queue Packets Transmitted"); 3091 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes", 3092 CTLFLAG_RD, &(txr->tx_bytes), 3093 "Queue Bytes Transmitted"); 3094 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 3095 CTLFLAG_RD, &(rxr->rx_packets), 3096 "Queue Packets Received"); 3097 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 3098 CTLFLAG_RD, &(rxr->rx_bytes), 3099 "Queue Bytes Received"); 3100 } 3101 3102 /* MAC stats */ 3103 ixl_add_sysctls_mac_stats(ctx, child, pf_stats); 3104} 3105 3106static void 3107ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, 3108 struct sysctl_oid_list *child, 3109 struct i40e_eth_stats *eth_stats) 3110{ 3111 struct ixl_sysctl_info ctls[] = 3112 { 3113 {ð_stats->rx_bytes, "good_octets_rcvd", "Good Octets Received"}, 3114 {ð_stats->rx_unicast, "ucast_pkts_rcvd", 3115 "Unicast Packets Received"}, 3116 {ð_stats->rx_multicast, "mcast_pkts_rcvd", 3117 "Multicast Packets Received"}, 3118 {ð_stats->rx_broadcast, "bcast_pkts_rcvd", 3119 "Broadcast Packets Received"}, 3120 {ð_stats->rx_discards, "rx_discards", "Discarded RX packets"}, 3121 {ð_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"}, 3122 {ð_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"}, 3123 {ð_stats->tx_multicast, "mcast_pkts_txd", 3124 "Multicast Packets Transmitted"}, 3125 {ð_stats->tx_broadcast, "bcast_pkts_txd", 3126 "Broadcast Packets Transmitted"}, 3127 // end 3128 {0,0,0} 3129 }; 3130 3131 struct ixl_sysctl_info *entry = ctls; 3132 while (entry->stat != 0) 3133 { 3134 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, entry->name, 3135 CTLFLAG_RD, entry->stat, 3136 entry->description); 3137 entry++; 3138 } 3139} 3140 3141static void 3142ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx, 3143 struct sysctl_oid_list *child, 3144 struct i40e_hw_port_stats *stats) 3145{ 3146 struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac", 3147 CTLFLAG_RD, NULL, "Mac Statistics"); 3148 struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node); 3149 3150 struct i40e_eth_stats *eth_stats = &stats->eth; 3151 ixl_add_sysctls_eth_stats(ctx, stat_list, eth_stats); 3152 3153 struct ixl_sysctl_info ctls[] = 3154 { 3155 {&stats->crc_errors, "crc_errors", "CRC Errors"}, 3156 {&stats->illegal_bytes, "illegal_bytes", "Illegal Byte Errors"}, 3157 {&stats->mac_local_faults, "local_faults", "MAC Local Faults"}, 3158 {&stats->mac_remote_faults, "remote_faults", "MAC Remote Faults"}, 3159 {&stats->rx_length_errors, "rx_length_errors", "Receive Length Errors"}, 3160 /* Packet Reception Stats */ 3161 {&stats->rx_size_64, "rx_frames_64", "64 byte frames received"}, 3162 {&stats->rx_size_127, "rx_frames_65_127", "65-127 byte frames received"}, 3163 {&stats->rx_size_255, "rx_frames_128_255", "128-255 byte frames received"}, 3164 {&stats->rx_size_511, "rx_frames_256_511", "256-511 byte frames received"}, 3165 {&stats->rx_size_1023, "rx_frames_512_1023", "512-1023 byte frames received"}, 3166 {&stats->rx_size_1522, "rx_frames_1024_1522", "1024-1522 byte frames received"}, 3167 {&stats->rx_size_big, "rx_frames_big", "1523-9522 byte frames received"}, 3168 {&stats->rx_undersize, "rx_undersize", "Undersized packets received"}, 3169 {&stats->rx_fragments, "rx_fragmented", "Fragmented packets received"}, 3170 {&stats->rx_oversize, "rx_oversized", "Oversized packets received"}, 3171 {&stats->rx_jabber, "rx_jabber", "Received Jabber"}, 3172 {&stats->checksum_error, "checksum_errors", "Checksum Errors"}, 3173 /* Packet Transmission Stats */ 3174 {&stats->tx_size_64, "tx_frames_64", "64 byte frames transmitted"}, 3175 {&stats->tx_size_127, "tx_frames_65_127", "65-127 byte frames transmitted"}, 3176 {&stats->tx_size_255, "tx_frames_128_255", "128-255 byte frames transmitted"}, 3177 {&stats->tx_size_511, "tx_frames_256_511", "256-511 byte frames transmitted"}, 3178 {&stats->tx_size_1023, "tx_frames_512_1023", "512-1023 byte frames transmitted"}, 3179 {&stats->tx_size_1522, "tx_frames_1024_1522", "1024-1522 byte frames transmitted"}, 3180 {&stats->tx_size_big, "tx_frames_big", "1523-9522 byte frames transmitted"}, 3181 /* Flow control */ 3182 {&stats->link_xon_tx, "xon_txd", "Link XON transmitted"}, 3183 {&stats->link_xon_rx, "xon_recvd", "Link XON received"}, 3184 {&stats->link_xoff_tx, "xoff_txd", "Link XOFF transmitted"}, 3185 {&stats->link_xoff_rx, "xoff_recvd", "Link XOFF received"}, 3186 /* End */ 3187 {0,0,0} 3188 }; 3189 3190 struct ixl_sysctl_info *entry = ctls; 3191 while (entry->stat != 0) 3192 { 3193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, entry->name, 3194 CTLFLAG_RD, entry->stat, 3195 entry->description); 3196 entry++; 3197 } 3198} 3199 3200/* 3201** ixl_config_rss - setup RSS 3202** - note this is done for the single vsi 3203*/ 3204static void ixl_config_rss(struct ixl_vsi *vsi) 3205{ 3206 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3207 struct i40e_hw *hw = vsi->hw; 3208 u32 lut = 0; 3209 u64 set_hena = 0, hena; 3210 int i, j, que_id; 3211#ifdef RSS 3212 u32 rss_hash_config; 3213 u32 rss_seed[IXL_KEYSZ]; 3214#else 3215 u32 rss_seed[IXL_KEYSZ] = {0x41b01687, 3216 0x183cfd8c, 0xce880440, 0x580cbc3c, 3217 0x35897377, 0x328b25e1, 0x4fa98922, 3218 0xb7d90c14, 0xd5bad70d, 0xcd15a2c1}; 3219#endif 3220 3221#ifdef RSS 3222 /* Fetch the configured RSS key */ 3223 rss_getkey((uint8_t *) &rss_seed); 3224#endif 3225 3226 /* Fill out hash function seed */ 3227 for (i = 0; i < IXL_KEYSZ; i++) 3228 wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]); 3229 3230 /* Enable PCTYPES for RSS: */ 3231#ifdef RSS 3232 rss_hash_config = rss_gethashconfig(); 3233 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 3234 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER); 3235 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 3236 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP); 3237 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 3238 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP); 3239 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 3240 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER); 3241 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 3242 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6); 3243 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 3244 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP); 3245 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 3246 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP); 3247#else 3248 set_hena = 3249 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | 3250 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | 3251 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | 3252 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | 3253 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | 3254 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | 3255 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | 3256 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | 3257 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | 3258 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | 3259 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD); 3260#endif 3261 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | 3262 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); 3263 hena |= set_hena; 3264 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); 3265 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 3266 3267 /* Populate the LUT with max no. of queues in round robin fashion */ 3268 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) { 3269 if (j == vsi->num_queues) 3270 j = 0; 3271#ifdef RSS 3272 /* 3273 * Fetch the RSS bucket id for the given indirection entry. 3274 * Cap it at the number of configured buckets (which is 3275 * num_queues.) 3276 */ 3277 que_id = rss_get_indirection_to_bucket(i); 3278 que_id = que_id % vsi->num_queues; 3279#else 3280 que_id = j; 3281#endif 3282 /* lut = 4-byte sliding window of 4 lut entries */ 3283 lut = (lut << 8) | (que_id & 3284 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1)); 3285 /* On i = 3, we have 4 entries in lut; write to the register */ 3286 if ((i & 3) == 3) 3287 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut); 3288 } 3289 ixl_flush(hw); 3290} 3291 3292 3293/* 3294** This routine is run via an vlan config EVENT, 3295** it enables us to use the HW Filter table since 3296** we can get the vlan id. This just creates the 3297** entry in the soft version of the VFTA, init will 3298** repopulate the real table. 3299*/ 3300static void 3301ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3302{ 3303 struct ixl_vsi *vsi = ifp->if_softc; 3304 struct i40e_hw *hw = vsi->hw; 3305 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3306 3307 if (ifp->if_softc != arg) /* Not our event */ 3308 return; 3309 3310 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3311 return; 3312 3313 IXL_PF_LOCK(pf); 3314 ++vsi->num_vlans; 3315 ixl_add_filter(vsi, hw->mac.addr, vtag); 3316 IXL_PF_UNLOCK(pf); 3317} 3318 3319/* 3320** This routine is run via an vlan 3321** unconfig EVENT, remove our entry 3322** in the soft vfta. 3323*/ 3324static void 3325ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3326{ 3327 struct ixl_vsi *vsi = ifp->if_softc; 3328 struct i40e_hw *hw = vsi->hw; 3329 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3330 3331 if (ifp->if_softc != arg) 3332 return; 3333 3334 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3335 return; 3336 3337 IXL_PF_LOCK(pf); 3338 --vsi->num_vlans; 3339 ixl_del_filter(vsi, hw->mac.addr, vtag); 3340 IXL_PF_UNLOCK(pf); 3341} 3342 3343/* 3344** This routine updates vlan filters, called by init 3345** it scans the filter table and then updates the hw 3346** after a soft reset. 3347*/ 3348static void 3349ixl_setup_vlan_filters(struct ixl_vsi *vsi) 3350{ 3351 struct ixl_mac_filter *f; 3352 int cnt = 0, flags; 3353 3354 if (vsi->num_vlans == 0) 3355 return; 3356 /* 3357 ** Scan the filter list for vlan entries, 3358 ** mark them for addition and then call 3359 ** for the AQ update. 3360 */ 3361 SLIST_FOREACH(f, &vsi->ftl, next) { 3362 if (f->flags & IXL_FILTER_VLAN) { 3363 f->flags |= 3364 (IXL_FILTER_ADD | 3365 IXL_FILTER_USED); 3366 cnt++; 3367 } 3368 } 3369 if (cnt == 0) { 3370 printf("setup vlan: no filters found!\n"); 3371 return; 3372 } 3373 flags = IXL_FILTER_VLAN; 3374 flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3375 ixl_add_hw_filters(vsi, flags, cnt); 3376 return; 3377} 3378 3379/* 3380** Initialize filter list and add filters that the hardware 3381** needs to know about. 3382*/ 3383static void 3384ixl_init_filters(struct ixl_vsi *vsi) 3385{ 3386 /* Add broadcast address */ 3387 u8 bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 3388 ixl_add_filter(vsi, bc, IXL_VLAN_ANY); 3389} 3390 3391/* 3392** This routine adds mulicast filters 3393*/ 3394static void 3395ixl_add_mc_filter(struct ixl_vsi *vsi, u8 *macaddr) 3396{ 3397 struct ixl_mac_filter *f; 3398 3399 /* Does one already exist */ 3400 f = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3401 if (f != NULL) 3402 return; 3403 3404 f = ixl_get_filter(vsi); 3405 if (f == NULL) { 3406 printf("WARNING: no filter available!!\n"); 3407 return; 3408 } 3409 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3410 f->vlan = IXL_VLAN_ANY; 3411 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED 3412 | IXL_FILTER_MC); 3413 3414 return; 3415} 3416 3417/* 3418** This routine adds macvlan filters 3419*/ 3420static void 3421ixl_add_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3422{ 3423 struct ixl_mac_filter *f, *tmp; 3424 device_t dev = vsi->dev; 3425 3426 DEBUGOUT("ixl_add_filter: begin"); 3427 3428 /* Does one already exist */ 3429 f = ixl_find_filter(vsi, macaddr, vlan); 3430 if (f != NULL) 3431 return; 3432 /* 3433 ** Is this the first vlan being registered, if so we 3434 ** need to remove the ANY filter that indicates we are 3435 ** not in a vlan, and replace that with a 0 filter. 3436 */ 3437 if ((vlan != IXL_VLAN_ANY) && (vsi->num_vlans == 1)) { 3438 tmp = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3439 if (tmp != NULL) { 3440 ixl_del_filter(vsi, macaddr, IXL_VLAN_ANY); 3441 ixl_add_filter(vsi, macaddr, 0); 3442 } 3443 } 3444 3445 f = ixl_get_filter(vsi); 3446 if (f == NULL) { 3447 device_printf(dev, "WARNING: no filter available!!\n"); 3448 return; 3449 } 3450 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3451 f->vlan = vlan; 3452 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3453 if (f->vlan != IXL_VLAN_ANY) 3454 f->flags |= IXL_FILTER_VLAN; 3455 3456 ixl_add_hw_filters(vsi, f->flags, 1); 3457 return; 3458} 3459 3460static void 3461ixl_del_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3462{ 3463 struct ixl_mac_filter *f; 3464 3465 f = ixl_find_filter(vsi, macaddr, vlan); 3466 if (f == NULL) 3467 return; 3468 3469 f->flags |= IXL_FILTER_DEL; 3470 ixl_del_hw_filters(vsi, 1); 3471 3472 /* Check if this is the last vlan removal */ 3473 if (vlan != IXL_VLAN_ANY && vsi->num_vlans == 0) { 3474 /* Switch back to a non-vlan filter */ 3475 ixl_del_filter(vsi, macaddr, 0); 3476 ixl_add_filter(vsi, macaddr, IXL_VLAN_ANY); 3477 } 3478 return; 3479} 3480 3481/* 3482** Find the filter with both matching mac addr and vlan id 3483*/ 3484static struct ixl_mac_filter * 3485ixl_find_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3486{ 3487 struct ixl_mac_filter *f; 3488 bool match = FALSE; 3489 3490 SLIST_FOREACH(f, &vsi->ftl, next) { 3491 if (!cmp_etheraddr(f->macaddr, macaddr)) 3492 continue; 3493 if (f->vlan == vlan) { 3494 match = TRUE; 3495 break; 3496 } 3497 } 3498 3499 if (!match) 3500 f = NULL; 3501 return (f); 3502} 3503 3504/* 3505** This routine takes additions to the vsi filter 3506** table and creates an Admin Queue call to create 3507** the filters in the hardware. 3508*/ 3509static void 3510ixl_add_hw_filters(struct ixl_vsi *vsi, int flags, int cnt) 3511{ 3512 struct i40e_aqc_add_macvlan_element_data *a, *b; 3513 struct ixl_mac_filter *f; 3514 struct i40e_hw *hw = vsi->hw; 3515 device_t dev = vsi->dev; 3516 int err, j = 0; 3517 3518 a = malloc(sizeof(struct i40e_aqc_add_macvlan_element_data) * cnt, 3519 M_DEVBUF, M_NOWAIT | M_ZERO); 3520 if (a == NULL) { 3521 device_printf(dev, "add_hw_filters failed to get memory\n"); 3522 return; 3523 } 3524 3525 /* 3526 ** Scan the filter list, each time we find one 3527 ** we add it to the admin queue array and turn off 3528 ** the add bit. 3529 */ 3530 SLIST_FOREACH(f, &vsi->ftl, next) { 3531 if (f->flags == flags) { 3532 b = &a[j]; // a pox on fvl long names :) 3533 bcopy(f->macaddr, b->mac_addr, ETHER_ADDR_LEN); 3534 b->vlan_tag = 3535 (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3536 b->flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 3537 f->flags &= ~IXL_FILTER_ADD; 3538 j++; 3539 } 3540 if (j == cnt) 3541 break; 3542 } 3543 if (j > 0) { 3544 err = i40e_aq_add_macvlan(hw, vsi->seid, a, j, NULL); 3545 if (err) 3546 device_printf(dev, "aq_add_macvlan err %d, " 3547 "aq_error %d\n", err, hw->aq.asq_last_status); 3548 else 3549 vsi->hw_filters_add += j; 3550 } 3551 free(a, M_DEVBUF); 3552 return; 3553} 3554 3555/* 3556** This routine takes removals in the vsi filter 3557** table and creates an Admin Queue call to delete 3558** the filters in the hardware. 3559*/ 3560static void 3561ixl_del_hw_filters(struct ixl_vsi *vsi, int cnt) 3562{ 3563 struct i40e_aqc_remove_macvlan_element_data *d, *e; 3564 struct i40e_hw *hw = vsi->hw; 3565 device_t dev = vsi->dev; 3566 struct ixl_mac_filter *f, *f_temp; 3567 int err, j = 0; 3568 3569 DEBUGOUT("ixl_del_hw_filters: begin\n"); 3570 3571 d = malloc(sizeof(struct i40e_aqc_remove_macvlan_element_data) * cnt, 3572 M_DEVBUF, M_NOWAIT | M_ZERO); 3573 if (d == NULL) { 3574 printf("del hw filter failed to get memory\n"); 3575 return; 3576 } 3577 3578 SLIST_FOREACH_SAFE(f, &vsi->ftl, next, f_temp) { 3579 if (f->flags & IXL_FILTER_DEL) { 3580 e = &d[j]; // a pox on fvl long names :) 3581 bcopy(f->macaddr, e->mac_addr, ETHER_ADDR_LEN); 3582 e->vlan_tag = (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3583 e->flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 3584 /* delete entry from vsi list */ 3585 SLIST_REMOVE(&vsi->ftl, f, ixl_mac_filter, next); 3586 free(f, M_DEVBUF); 3587 j++; 3588 } 3589 if (j == cnt) 3590 break; 3591 } 3592 if (j > 0) { 3593 err = i40e_aq_remove_macvlan(hw, vsi->seid, d, j, NULL); 3594 /* NOTE: returns ENOENT every time but seems to work fine, 3595 so we'll ignore that specific error. */ 3596 // TODO: Does this still occur on current firmwares? 3597 if (err && hw->aq.asq_last_status != I40E_AQ_RC_ENOENT) { 3598 int sc = 0; 3599 for (int i = 0; i < j; i++) 3600 sc += (!d[i].error_code); 3601 vsi->hw_filters_del += sc; 3602 device_printf(dev, 3603 "Failed to remove %d/%d filters, aq error %d\n", 3604 j - sc, j, hw->aq.asq_last_status); 3605 } else 3606 vsi->hw_filters_del += j; 3607 } 3608 free(d, M_DEVBUF); 3609 3610 DEBUGOUT("ixl_del_hw_filters: end\n"); 3611 return; 3612} 3613 3614 3615static void 3616ixl_enable_rings(struct ixl_vsi *vsi) 3617{ 3618 struct i40e_hw *hw = vsi->hw; 3619 u32 reg; 3620 3621 for (int i = 0; i < vsi->num_queues; i++) { 3622 i40e_pre_tx_queue_cfg(hw, i, TRUE); 3623 3624 reg = rd32(hw, I40E_QTX_ENA(i)); 3625 reg |= I40E_QTX_ENA_QENA_REQ_MASK | 3626 I40E_QTX_ENA_QENA_STAT_MASK; 3627 wr32(hw, I40E_QTX_ENA(i), reg); 3628 /* Verify the enable took */ 3629 for (int j = 0; j < 10; j++) { 3630 reg = rd32(hw, I40E_QTX_ENA(i)); 3631 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3632 break; 3633 i40e_msec_delay(10); 3634 } 3635 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) 3636 printf("TX queue %d disabled!\n", i); 3637 3638 reg = rd32(hw, I40E_QRX_ENA(i)); 3639 reg |= I40E_QRX_ENA_QENA_REQ_MASK | 3640 I40E_QRX_ENA_QENA_STAT_MASK; 3641 wr32(hw, I40E_QRX_ENA(i), reg); 3642 /* Verify the enable took */ 3643 for (int j = 0; j < 10; j++) { 3644 reg = rd32(hw, I40E_QRX_ENA(i)); 3645 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3646 break; 3647 i40e_msec_delay(10); 3648 } 3649 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3650 printf("RX queue %d disabled!\n", i); 3651 } 3652} 3653 3654static void 3655ixl_disable_rings(struct ixl_vsi *vsi) 3656{ 3657 struct i40e_hw *hw = vsi->hw; 3658 u32 reg; 3659 3660 for (int i = 0; i < vsi->num_queues; i++) { 3661 i40e_pre_tx_queue_cfg(hw, i, FALSE); 3662 i40e_usec_delay(500); 3663 3664 reg = rd32(hw, I40E_QTX_ENA(i)); 3665 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 3666 wr32(hw, I40E_QTX_ENA(i), reg); 3667 /* Verify the disable took */ 3668 for (int j = 0; j < 10; j++) { 3669 reg = rd32(hw, I40E_QTX_ENA(i)); 3670 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3671 break; 3672 i40e_msec_delay(10); 3673 } 3674 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3675 printf("TX queue %d still enabled!\n", i); 3676 3677 reg = rd32(hw, I40E_QRX_ENA(i)); 3678 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 3679 wr32(hw, I40E_QRX_ENA(i), reg); 3680 /* Verify the disable took */ 3681 for (int j = 0; j < 10; j++) { 3682 reg = rd32(hw, I40E_QRX_ENA(i)); 3683 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3684 break; 3685 i40e_msec_delay(10); 3686 } 3687 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3688 printf("RX queue %d still enabled!\n", i); 3689 } 3690} 3691 3692/** 3693 * ixl_handle_mdd_event 3694 * 3695 * Called from interrupt handler to identify possibly malicious vfs 3696 * (But also detects events from the PF, as well) 3697 **/ 3698static void ixl_handle_mdd_event(struct ixl_pf *pf) 3699{ 3700 struct i40e_hw *hw = &pf->hw; 3701 device_t dev = pf->dev; 3702 bool mdd_detected = false; 3703 bool pf_mdd_detected = false; 3704 u32 reg; 3705 3706 /* find what triggered the MDD event */ 3707 reg = rd32(hw, I40E_GL_MDET_TX); 3708 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 3709 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 3710 I40E_GL_MDET_TX_PF_NUM_SHIFT; 3711 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 3712 I40E_GL_MDET_TX_EVENT_SHIFT; 3713 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 3714 I40E_GL_MDET_TX_QUEUE_SHIFT; 3715 device_printf(dev, 3716 "Malicious Driver Detection event 0x%02x" 3717 " on TX queue %d pf number 0x%02x\n", 3718 event, queue, pf_num); 3719 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 3720 mdd_detected = true; 3721 } 3722 reg = rd32(hw, I40E_GL_MDET_RX); 3723 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 3724 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 3725 I40E_GL_MDET_RX_FUNCTION_SHIFT; 3726 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 3727 I40E_GL_MDET_RX_EVENT_SHIFT; 3728 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 3729 I40E_GL_MDET_RX_QUEUE_SHIFT; 3730 device_printf(dev, 3731 "Malicious Driver Detection event 0x%02x" 3732 " on RX queue %d of function 0x%02x\n", 3733 event, queue, func); 3734 wr32(hw, I40E_GL_MDET_RX, 0xffffffff); 3735 mdd_detected = true; 3736 } 3737 3738 if (mdd_detected) { 3739 reg = rd32(hw, I40E_PF_MDET_TX); 3740 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 3741 wr32(hw, I40E_PF_MDET_TX, 0xFFFF); 3742 device_printf(dev, 3743 "MDD TX event is for this function 0x%08x", 3744 reg); 3745 pf_mdd_detected = true; 3746 } 3747 reg = rd32(hw, I40E_PF_MDET_RX); 3748 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 3749 wr32(hw, I40E_PF_MDET_RX, 0xFFFF); 3750 device_printf(dev, 3751 "MDD RX event is for this function 0x%08x", 3752 reg); 3753 pf_mdd_detected = true; 3754 } 3755 } 3756 3757 /* re-enable mdd interrupt cause */ 3758 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 3759 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 3760 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 3761 ixl_flush(hw); 3762} 3763 3764static void 3765ixl_enable_intr(struct ixl_vsi *vsi) 3766{ 3767 struct i40e_hw *hw = vsi->hw; 3768 struct ixl_queue *que = vsi->queues; 3769 3770 if (ixl_enable_msix) { 3771 ixl_enable_adminq(hw); 3772 for (int i = 0; i < vsi->num_queues; i++, que++) 3773 ixl_enable_queue(hw, que->me); 3774 } else 3775 ixl_enable_legacy(hw); 3776} 3777 3778static void 3779ixl_disable_intr(struct ixl_vsi *vsi) 3780{ 3781 struct i40e_hw *hw = vsi->hw; 3782 struct ixl_queue *que = vsi->queues; 3783 3784 if (ixl_enable_msix) { 3785 ixl_disable_adminq(hw); 3786 for (int i = 0; i < vsi->num_queues; i++, que++) 3787 ixl_disable_queue(hw, que->me); 3788 } else 3789 ixl_disable_legacy(hw); 3790} 3791 3792static void 3793ixl_enable_adminq(struct i40e_hw *hw) 3794{ 3795 u32 reg; 3796 3797 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 3798 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 3799 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 3800 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3801 ixl_flush(hw); 3802 return; 3803} 3804 3805static void 3806ixl_disable_adminq(struct i40e_hw *hw) 3807{ 3808 u32 reg; 3809 3810 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 3811 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3812 3813 return; 3814} 3815 3816static void 3817ixl_enable_queue(struct i40e_hw *hw, int id) 3818{ 3819 u32 reg; 3820 3821 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | 3822 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 3823 (IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 3824 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 3825} 3826 3827static void 3828ixl_disable_queue(struct i40e_hw *hw, int id) 3829{ 3830 u32 reg; 3831 3832 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 3833 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 3834 3835 return; 3836} 3837 3838static void 3839ixl_enable_legacy(struct i40e_hw *hw) 3840{ 3841 u32 reg; 3842 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 3843 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 3844 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 3845 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3846} 3847 3848static void 3849ixl_disable_legacy(struct i40e_hw *hw) 3850{ 3851 u32 reg; 3852 3853 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 3854 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3855 3856 return; 3857} 3858 3859static void 3860ixl_update_stats_counters(struct ixl_pf *pf) 3861{ 3862 struct i40e_hw *hw = &pf->hw; 3863 struct ixl_vsi *vsi = &pf->vsi; 3864 3865 struct i40e_hw_port_stats *nsd = &pf->stats; 3866 struct i40e_hw_port_stats *osd = &pf->stats_offsets; 3867 3868 /* Update hw stats */ 3869 ixl_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), 3870 pf->stat_offsets_loaded, 3871 &osd->crc_errors, &nsd->crc_errors); 3872 ixl_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), 3873 pf->stat_offsets_loaded, 3874 &osd->illegal_bytes, &nsd->illegal_bytes); 3875 ixl_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), 3876 I40E_GLPRT_GORCL(hw->port), 3877 pf->stat_offsets_loaded, 3878 &osd->eth.rx_bytes, &nsd->eth.rx_bytes); 3879 ixl_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), 3880 I40E_GLPRT_GOTCL(hw->port), 3881 pf->stat_offsets_loaded, 3882 &osd->eth.tx_bytes, &nsd->eth.tx_bytes); 3883 ixl_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), 3884 pf->stat_offsets_loaded, 3885 &osd->eth.rx_discards, 3886 &nsd->eth.rx_discards); 3887 ixl_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), 3888 I40E_GLPRT_UPRCL(hw->port), 3889 pf->stat_offsets_loaded, 3890 &osd->eth.rx_unicast, 3891 &nsd->eth.rx_unicast); 3892 ixl_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), 3893 I40E_GLPRT_UPTCL(hw->port), 3894 pf->stat_offsets_loaded, 3895 &osd->eth.tx_unicast, 3896 &nsd->eth.tx_unicast); 3897 ixl_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), 3898 I40E_GLPRT_MPRCL(hw->port), 3899 pf->stat_offsets_loaded, 3900 &osd->eth.rx_multicast, 3901 &nsd->eth.rx_multicast); 3902 ixl_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), 3903 I40E_GLPRT_MPTCL(hw->port), 3904 pf->stat_offsets_loaded, 3905 &osd->eth.tx_multicast, 3906 &nsd->eth.tx_multicast); 3907 ixl_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), 3908 I40E_GLPRT_BPRCL(hw->port), 3909 pf->stat_offsets_loaded, 3910 &osd->eth.rx_broadcast, 3911 &nsd->eth.rx_broadcast); 3912 ixl_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), 3913 I40E_GLPRT_BPTCL(hw->port), 3914 pf->stat_offsets_loaded, 3915 &osd->eth.tx_broadcast, 3916 &nsd->eth.tx_broadcast); 3917 3918 ixl_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), 3919 pf->stat_offsets_loaded, 3920 &osd->tx_dropped_link_down, 3921 &nsd->tx_dropped_link_down); 3922 ixl_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), 3923 pf->stat_offsets_loaded, 3924 &osd->mac_local_faults, 3925 &nsd->mac_local_faults); 3926 ixl_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), 3927 pf->stat_offsets_loaded, 3928 &osd->mac_remote_faults, 3929 &nsd->mac_remote_faults); 3930 ixl_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), 3931 pf->stat_offsets_loaded, 3932 &osd->rx_length_errors, 3933 &nsd->rx_length_errors); 3934 3935 /* Flow control (LFC) stats */ 3936 ixl_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), 3937 pf->stat_offsets_loaded, 3938 &osd->link_xon_rx, &nsd->link_xon_rx); 3939 ixl_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), 3940 pf->stat_offsets_loaded, 3941 &osd->link_xon_tx, &nsd->link_xon_tx); 3942 ixl_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 3943 pf->stat_offsets_loaded, 3944 &osd->link_xoff_rx, &nsd->link_xoff_rx); 3945 ixl_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 3946 pf->stat_offsets_loaded, 3947 &osd->link_xoff_tx, &nsd->link_xoff_tx); 3948 3949 /* Packet size stats rx */ 3950 ixl_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), 3951 I40E_GLPRT_PRC64L(hw->port), 3952 pf->stat_offsets_loaded, 3953 &osd->rx_size_64, &nsd->rx_size_64); 3954 ixl_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), 3955 I40E_GLPRT_PRC127L(hw->port), 3956 pf->stat_offsets_loaded, 3957 &osd->rx_size_127, &nsd->rx_size_127); 3958 ixl_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), 3959 I40E_GLPRT_PRC255L(hw->port), 3960 pf->stat_offsets_loaded, 3961 &osd->rx_size_255, &nsd->rx_size_255); 3962 ixl_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), 3963 I40E_GLPRT_PRC511L(hw->port), 3964 pf->stat_offsets_loaded, 3965 &osd->rx_size_511, &nsd->rx_size_511); 3966 ixl_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), 3967 I40E_GLPRT_PRC1023L(hw->port), 3968 pf->stat_offsets_loaded, 3969 &osd->rx_size_1023, &nsd->rx_size_1023); 3970 ixl_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), 3971 I40E_GLPRT_PRC1522L(hw->port), 3972 pf->stat_offsets_loaded, 3973 &osd->rx_size_1522, &nsd->rx_size_1522); 3974 ixl_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), 3975 I40E_GLPRT_PRC9522L(hw->port), 3976 pf->stat_offsets_loaded, 3977 &osd->rx_size_big, &nsd->rx_size_big); 3978 3979 /* Packet size stats tx */ 3980 ixl_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), 3981 I40E_GLPRT_PTC64L(hw->port), 3982 pf->stat_offsets_loaded, 3983 &osd->tx_size_64, &nsd->tx_size_64); 3984 ixl_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), 3985 I40E_GLPRT_PTC127L(hw->port), 3986 pf->stat_offsets_loaded, 3987 &osd->tx_size_127, &nsd->tx_size_127); 3988 ixl_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), 3989 I40E_GLPRT_PTC255L(hw->port), 3990 pf->stat_offsets_loaded, 3991 &osd->tx_size_255, &nsd->tx_size_255); 3992 ixl_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), 3993 I40E_GLPRT_PTC511L(hw->port), 3994 pf->stat_offsets_loaded, 3995 &osd->tx_size_511, &nsd->tx_size_511); 3996 ixl_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), 3997 I40E_GLPRT_PTC1023L(hw->port), 3998 pf->stat_offsets_loaded, 3999 &osd->tx_size_1023, &nsd->tx_size_1023); 4000 ixl_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), 4001 I40E_GLPRT_PTC1522L(hw->port), 4002 pf->stat_offsets_loaded, 4003 &osd->tx_size_1522, &nsd->tx_size_1522); 4004 ixl_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), 4005 I40E_GLPRT_PTC9522L(hw->port), 4006 pf->stat_offsets_loaded, 4007 &osd->tx_size_big, &nsd->tx_size_big); 4008 4009 ixl_stat_update32(hw, I40E_GLPRT_RUC(hw->port), 4010 pf->stat_offsets_loaded, 4011 &osd->rx_undersize, &nsd->rx_undersize); 4012 ixl_stat_update32(hw, I40E_GLPRT_RFC(hw->port), 4013 pf->stat_offsets_loaded, 4014 &osd->rx_fragments, &nsd->rx_fragments); 4015 ixl_stat_update32(hw, I40E_GLPRT_ROC(hw->port), 4016 pf->stat_offsets_loaded, 4017 &osd->rx_oversize, &nsd->rx_oversize); 4018 ixl_stat_update32(hw, I40E_GLPRT_RJC(hw->port), 4019 pf->stat_offsets_loaded, 4020 &osd->rx_jabber, &nsd->rx_jabber); 4021 pf->stat_offsets_loaded = true; 4022 /* End hw stats */ 4023 4024 /* Update vsi stats */ 4025 ixl_update_eth_stats(vsi); 4026 4027 /* OS statistics */ 4028 // ERJ - these are per-port, update all vsis? 4029 IXL_SET_IERRORS(vsi, nsd->crc_errors + nsd->illegal_bytes); 4030} 4031 4032/* 4033** Tasklet handler for MSIX Adminq interrupts 4034** - do outside interrupt since it might sleep 4035*/ 4036static void 4037ixl_do_adminq(void *context, int pending) 4038{ 4039 struct ixl_pf *pf = context; 4040 struct i40e_hw *hw = &pf->hw; 4041 struct ixl_vsi *vsi = &pf->vsi; 4042 struct i40e_arq_event_info event; 4043 i40e_status ret; 4044 u32 reg, loop = 0; 4045 u16 opcode, result; 4046 4047 event.buf_len = IXL_AQ_BUF_SZ; 4048 event.msg_buf = malloc(event.buf_len, 4049 M_DEVBUF, M_NOWAIT | M_ZERO); 4050 if (!event.msg_buf) { 4051 printf("Unable to allocate adminq memory\n"); 4052 return; 4053 } 4054 4055 /* clean and process any events */ 4056 do { 4057 ret = i40e_clean_arq_element(hw, &event, &result); 4058 if (ret) 4059 break; 4060 opcode = LE16_TO_CPU(event.desc.opcode); 4061 switch (opcode) { 4062 case i40e_aqc_opc_get_link_status: 4063 vsi->link_up = ixl_config_link(hw); 4064 ixl_update_link_status(pf); 4065 break; 4066 case i40e_aqc_opc_send_msg_to_pf: 4067 /* process pf/vf communication here */ 4068 break; 4069 case i40e_aqc_opc_event_lan_overflow: 4070 break; 4071 default: 4072#ifdef IXL_DEBUG 4073 printf("AdminQ unknown event %x\n", opcode); 4074#endif 4075 break; 4076 } 4077 4078 } while (result && (loop++ < IXL_ADM_LIMIT)); 4079 4080 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4081 reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 4082 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4083 free(event.msg_buf, M_DEVBUF); 4084 4085 if (pf->msix > 1) 4086 ixl_enable_adminq(&pf->hw); 4087 else 4088 ixl_enable_intr(vsi); 4089} 4090 4091static int 4092ixl_debug_info(SYSCTL_HANDLER_ARGS) 4093{ 4094 struct ixl_pf *pf; 4095 int error, input = 0; 4096 4097 error = sysctl_handle_int(oidp, &input, 0, req); 4098 4099 if (error || !req->newptr) 4100 return (error); 4101 4102 if (input == 1) { 4103 pf = (struct ixl_pf *)arg1; 4104 ixl_print_debug_info(pf); 4105 } 4106 4107 return (error); 4108} 4109 4110static void 4111ixl_print_debug_info(struct ixl_pf *pf) 4112{ 4113 struct i40e_hw *hw = &pf->hw; 4114 struct ixl_vsi *vsi = &pf->vsi; 4115 struct ixl_queue *que = vsi->queues; 4116 struct rx_ring *rxr = &que->rxr; 4117 struct tx_ring *txr = &que->txr; 4118 u32 reg; 4119 4120 4121 printf("Queue irqs = %jx\n", (uintmax_t)que->irqs); 4122 printf("AdminQ irqs = %jx\n", (uintmax_t)pf->admin_irq); 4123 printf("RX next check = %x\n", rxr->next_check); 4124 printf("RX not ready = %jx\n", (uintmax_t)rxr->not_done); 4125 printf("RX packets = %jx\n", (uintmax_t)rxr->rx_packets); 4126 printf("TX desc avail = %x\n", txr->avail); 4127 4128 reg = rd32(hw, I40E_GLV_GORCL(0xc)); 4129 printf("RX Bytes = %x\n", reg); 4130 reg = rd32(hw, I40E_GLPRT_GORCL(hw->port)); 4131 printf("Port RX Bytes = %x\n", reg); 4132 reg = rd32(hw, I40E_GLV_RDPC(0xc)); 4133 printf("RX discard = %x\n", reg); 4134 reg = rd32(hw, I40E_GLPRT_RDPC(hw->port)); 4135 printf("Port RX discard = %x\n", reg); 4136 4137 reg = rd32(hw, I40E_GLV_TEPC(0xc)); 4138 printf("TX errors = %x\n", reg); 4139 reg = rd32(hw, I40E_GLV_GOTCL(0xc)); 4140 printf("TX Bytes = %x\n", reg); 4141 4142 reg = rd32(hw, I40E_GLPRT_RUC(hw->port)); 4143 printf("RX undersize = %x\n", reg); 4144 reg = rd32(hw, I40E_GLPRT_RFC(hw->port)); 4145 printf("RX fragments = %x\n", reg); 4146 reg = rd32(hw, I40E_GLPRT_ROC(hw->port)); 4147 printf("RX oversize = %x\n", reg); 4148 reg = rd32(hw, I40E_GLPRT_RLEC(hw->port)); 4149 printf("RX length error = %x\n", reg); 4150 reg = rd32(hw, I40E_GLPRT_MRFC(hw->port)); 4151 printf("mac remote fault = %x\n", reg); 4152 reg = rd32(hw, I40E_GLPRT_MLFC(hw->port)); 4153 printf("mac local fault = %x\n", reg); 4154} 4155 4156/** 4157 * Update VSI-specific ethernet statistics counters. 4158 **/ 4159void ixl_update_eth_stats(struct ixl_vsi *vsi) 4160{ 4161 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 4162 struct i40e_hw *hw = &pf->hw; 4163 struct i40e_eth_stats *es; 4164 struct i40e_eth_stats *oes; 4165 int i; 4166 uint64_t tx_discards; 4167 struct i40e_hw_port_stats *nsd; 4168 u16 stat_idx = vsi->info.stat_counter_idx; 4169 4170 es = &vsi->eth_stats; 4171 oes = &vsi->eth_stats_offsets; 4172 nsd = &pf->stats; 4173 4174 /* Gather up the stats that the hw collects */ 4175 ixl_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 4176 vsi->stat_offsets_loaded, 4177 &oes->tx_errors, &es->tx_errors); 4178 ixl_stat_update32(hw, I40E_GLV_RDPC(stat_idx), 4179 vsi->stat_offsets_loaded, 4180 &oes->rx_discards, &es->rx_discards); 4181 4182 ixl_stat_update48(hw, I40E_GLV_GORCH(stat_idx), 4183 I40E_GLV_GORCL(stat_idx), 4184 vsi->stat_offsets_loaded, 4185 &oes->rx_bytes, &es->rx_bytes); 4186 ixl_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), 4187 I40E_GLV_UPRCL(stat_idx), 4188 vsi->stat_offsets_loaded, 4189 &oes->rx_unicast, &es->rx_unicast); 4190 ixl_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), 4191 I40E_GLV_MPRCL(stat_idx), 4192 vsi->stat_offsets_loaded, 4193 &oes->rx_multicast, &es->rx_multicast); 4194 ixl_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), 4195 I40E_GLV_BPRCL(stat_idx), 4196 vsi->stat_offsets_loaded, 4197 &oes->rx_broadcast, &es->rx_broadcast); 4198 4199 ixl_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), 4200 I40E_GLV_GOTCL(stat_idx), 4201 vsi->stat_offsets_loaded, 4202 &oes->tx_bytes, &es->tx_bytes); 4203 ixl_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), 4204 I40E_GLV_UPTCL(stat_idx), 4205 vsi->stat_offsets_loaded, 4206 &oes->tx_unicast, &es->tx_unicast); 4207 ixl_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), 4208 I40E_GLV_MPTCL(stat_idx), 4209 vsi->stat_offsets_loaded, 4210 &oes->tx_multicast, &es->tx_multicast); 4211 ixl_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), 4212 I40E_GLV_BPTCL(stat_idx), 4213 vsi->stat_offsets_loaded, 4214 &oes->tx_broadcast, &es->tx_broadcast); 4215 vsi->stat_offsets_loaded = true; 4216 4217 tx_discards = es->tx_discards + nsd->tx_dropped_link_down; 4218 for (i = 0; i < vsi->num_queues; i++) 4219 tx_discards += vsi->queues[i].txr.br->br_drops; 4220 4221 /* Update ifnet stats */ 4222 IXL_SET_IPACKETS(vsi, es->rx_unicast + 4223 es->rx_multicast + 4224 es->rx_broadcast); 4225 IXL_SET_OPACKETS(vsi, es->tx_unicast + 4226 es->tx_multicast + 4227 es->tx_broadcast); 4228 IXL_SET_IBYTES(vsi, es->rx_bytes); 4229 IXL_SET_OBYTES(vsi, es->tx_bytes); 4230 IXL_SET_IMCASTS(vsi, es->rx_multicast); 4231 IXL_SET_OMCASTS(vsi, es->tx_multicast); 4232 4233 IXL_SET_OERRORS(vsi, es->tx_errors); 4234 IXL_SET_IQDROPS(vsi, es->rx_discards + nsd->eth.rx_discards); 4235 IXL_SET_OQDROPS(vsi, tx_discards); 4236 IXL_SET_NOPROTO(vsi, es->rx_unknown_protocol); 4237 IXL_SET_COLLISIONS(vsi, 0); 4238} 4239 4240/** 4241 * Reset all of the stats for the given pf 4242 **/ 4243void ixl_pf_reset_stats(struct ixl_pf *pf) 4244{ 4245 bzero(&pf->stats, sizeof(struct i40e_hw_port_stats)); 4246 bzero(&pf->stats_offsets, sizeof(struct i40e_hw_port_stats)); 4247 pf->stat_offsets_loaded = false; 4248} 4249 4250/** 4251 * Resets all stats of the given vsi 4252 **/ 4253void ixl_vsi_reset_stats(struct ixl_vsi *vsi) 4254{ 4255 bzero(&vsi->eth_stats, sizeof(struct i40e_eth_stats)); 4256 bzero(&vsi->eth_stats_offsets, sizeof(struct i40e_eth_stats)); 4257 vsi->stat_offsets_loaded = false; 4258} 4259 4260/** 4261 * Read and update a 48 bit stat from the hw 4262 * 4263 * Since the device stats are not reset at PFReset, they likely will not 4264 * be zeroed when the driver starts. We'll save the first values read 4265 * and use them as offsets to be subtracted from the raw values in order 4266 * to report stats that count from zero. 4267 **/ 4268static void 4269ixl_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, 4270 bool offset_loaded, u64 *offset, u64 *stat) 4271{ 4272 u64 new_data; 4273 4274#if defined(__FreeBSD__) && (__FreeBSD_version >= 1000000) && defined(__amd64__) 4275 new_data = rd64(hw, loreg); 4276#else 4277 /* 4278 * Use two rd32's instead of one rd64; FreeBSD versions before 4279 * 10 don't support 8 byte bus reads/writes. 4280 */ 4281 new_data = rd32(hw, loreg); 4282 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 4283#endif 4284 4285 if (!offset_loaded) 4286 *offset = new_data; 4287 if (new_data >= *offset) 4288 *stat = new_data - *offset; 4289 else 4290 *stat = (new_data + ((u64)1 << 48)) - *offset; 4291 *stat &= 0xFFFFFFFFFFFFULL; 4292} 4293 4294/** 4295 * Read and update a 32 bit stat from the hw 4296 **/ 4297static void 4298ixl_stat_update32(struct i40e_hw *hw, u32 reg, 4299 bool offset_loaded, u64 *offset, u64 *stat) 4300{ 4301 u32 new_data; 4302 4303 new_data = rd32(hw, reg); 4304 if (!offset_loaded) 4305 *offset = new_data; 4306 if (new_data >= *offset) 4307 *stat = (u32)(new_data - *offset); 4308 else 4309 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset); 4310} 4311 4312/* 4313** Set flow control using sysctl: 4314** 0 - off 4315** 1 - rx pause 4316** 2 - tx pause 4317** 3 - full 4318*/ 4319static int 4320ixl_set_flowcntl(SYSCTL_HANDLER_ARGS) 4321{ 4322 /* 4323 * TODO: ensure flow control is disabled if 4324 * priority flow control is enabled 4325 * 4326 * TODO: ensure tx CRC by hardware should be enabled 4327 * if tx flow control is enabled. 4328 */ 4329 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4330 struct i40e_hw *hw = &pf->hw; 4331 device_t dev = pf->dev; 4332 int error = 0; 4333 enum i40e_status_code aq_error = 0; 4334 u8 fc_aq_err = 0; 4335 4336 /* Get request */ 4337 error = sysctl_handle_int(oidp, &pf->fc, 0, req); 4338 if ((error) || (req->newptr == NULL)) 4339 return (error); 4340 if (pf->fc < 0 || pf->fc > 3) { 4341 device_printf(dev, 4342 "Invalid fc mode; valid modes are 0 through 3\n"); 4343 return (EINVAL); 4344 } 4345 4346 /* 4347 ** Changing flow control mode currently does not work on 4348 ** 40GBASE-CR4 PHYs 4349 */ 4350 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4 4351 || hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4_CU) { 4352 device_printf(dev, "Changing flow control mode unsupported" 4353 " on 40GBase-CR4 media.\n"); 4354 return (ENODEV); 4355 } 4356 4357 /* Set fc ability for port */ 4358 hw->fc.requested_mode = pf->fc; 4359 aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE); 4360 if (aq_error) { 4361 device_printf(dev, 4362 "%s: Error setting new fc mode %d; fc_err %#x\n", 4363 __func__, aq_error, fc_aq_err); 4364 return (EAGAIN); 4365 } 4366 4367 return (0); 4368} 4369 4370static int 4371ixl_current_speed(SYSCTL_HANDLER_ARGS) 4372{ 4373 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4374 struct i40e_hw *hw = &pf->hw; 4375 int error = 0, index = 0; 4376 4377 char *speeds[] = { 4378 "Unknown", 4379 "100M", 4380 "1G", 4381 "10G", 4382 "40G", 4383 "20G" 4384 }; 4385 4386 ixl_update_link_status(pf); 4387 4388 switch (hw->phy.link_info.link_speed) { 4389 case I40E_LINK_SPEED_100MB: 4390 index = 1; 4391 break; 4392 case I40E_LINK_SPEED_1GB: 4393 index = 2; 4394 break; 4395 case I40E_LINK_SPEED_10GB: 4396 index = 3; 4397 break; 4398 case I40E_LINK_SPEED_40GB: 4399 index = 4; 4400 break; 4401 case I40E_LINK_SPEED_20GB: 4402 index = 5; 4403 break; 4404 case I40E_LINK_SPEED_UNKNOWN: 4405 default: 4406 index = 0; 4407 break; 4408 } 4409 4410 error = sysctl_handle_string(oidp, speeds[index], 4411 strlen(speeds[index]), req); 4412 return (error); 4413} 4414 4415static int 4416ixl_set_advertised_speeds(struct ixl_pf *pf, int speeds) 4417{ 4418 struct i40e_hw *hw = &pf->hw; 4419 device_t dev = pf->dev; 4420 struct i40e_aq_get_phy_abilities_resp abilities; 4421 struct i40e_aq_set_phy_config config; 4422 enum i40e_status_code aq_error = 0; 4423 4424 /* Get current capability information */ 4425 aq_error = i40e_aq_get_phy_capabilities(hw, 4426 FALSE, FALSE, &abilities, NULL); 4427 if (aq_error) { 4428 device_printf(dev, 4429 "%s: Error getting phy capabilities %d," 4430 " aq error: %d\n", __func__, aq_error, 4431 hw->aq.asq_last_status); 4432 return (EAGAIN); 4433 } 4434 4435 /* Prepare new config */ 4436 bzero(&config, sizeof(config)); 4437 config.phy_type = abilities.phy_type; 4438 config.abilities = abilities.abilities 4439 | I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 4440 config.eee_capability = abilities.eee_capability; 4441 config.eeer = abilities.eeer_val; 4442 config.low_power_ctrl = abilities.d3_lpan; 4443 /* Translate into aq cmd link_speed */ 4444 if (speeds & 0x4) 4445 config.link_speed |= I40E_LINK_SPEED_10GB; 4446 if (speeds & 0x2) 4447 config.link_speed |= I40E_LINK_SPEED_1GB; 4448 if (speeds & 0x1) 4449 config.link_speed |= I40E_LINK_SPEED_100MB; 4450 4451 /* Do aq command & restart link */ 4452 aq_error = i40e_aq_set_phy_config(hw, &config, NULL); 4453 if (aq_error) { 4454 device_printf(dev, 4455 "%s: Error setting new phy config %d," 4456 " aq error: %d\n", __func__, aq_error, 4457 hw->aq.asq_last_status); 4458 return (EAGAIN); 4459 } 4460 4461 /* 4462 ** This seems a bit heavy handed, but we 4463 ** need to get a reinit on some devices 4464 */ 4465 IXL_PF_LOCK(pf); 4466 ixl_stop(pf); 4467 ixl_init_locked(pf); 4468 IXL_PF_UNLOCK(pf); 4469 4470 return (0); 4471} 4472 4473/* 4474** Control link advertise speed: 4475** Flags: 4476** 0x1 - advertise 100 Mb 4477** 0x2 - advertise 1G 4478** 0x4 - advertise 10G 4479** 4480** Does not work on 40G devices. 4481*/ 4482static int 4483ixl_set_advertise(SYSCTL_HANDLER_ARGS) 4484{ 4485 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4486 struct i40e_hw *hw = &pf->hw; 4487 device_t dev = pf->dev; 4488 int requested_ls = 0; 4489 int error = 0; 4490 4491 /* 4492 ** FW doesn't support changing advertised speed 4493 ** for 40G devices; speed is always 40G. 4494 */ 4495 if (i40e_is_40G_device(hw->device_id)) 4496 return (ENODEV); 4497 4498 /* Read in new mode */ 4499 requested_ls = pf->advertised_speed; 4500 error = sysctl_handle_int(oidp, &requested_ls, 0, req); 4501 if ((error) || (req->newptr == NULL)) 4502 return (error); 4503 if (requested_ls < 1 || requested_ls > 7) { 4504 device_printf(dev, 4505 "Invalid advertised speed; valid modes are 0x1 through 0x7\n"); 4506 return (EINVAL); 4507 } 4508 4509 /* Exit if no change */ 4510 if (pf->advertised_speed == requested_ls) 4511 return (0); 4512 4513 error = ixl_set_advertised_speeds(pf, requested_ls); 4514 if (error) 4515 return (error); 4516 4517 pf->advertised_speed = requested_ls; 4518 ixl_update_link_status(pf); 4519 return (0); 4520} 4521 4522/* 4523** Get the width and transaction speed of 4524** the bus this adapter is plugged into. 4525*/ 4526static u16 4527ixl_get_bus_info(struct i40e_hw *hw, device_t dev) 4528{ 4529 u16 link; 4530 u32 offset; 4531 4532 4533 /* Get the PCI Express Capabilities offset */ 4534 pci_find_cap(dev, PCIY_EXPRESS, &offset); 4535 4536 /* ...and read the Link Status Register */ 4537 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 4538 4539 switch (link & I40E_PCI_LINK_WIDTH) { 4540 case I40E_PCI_LINK_WIDTH_1: 4541 hw->bus.width = i40e_bus_width_pcie_x1; 4542 break; 4543 case I40E_PCI_LINK_WIDTH_2: 4544 hw->bus.width = i40e_bus_width_pcie_x2; 4545 break; 4546 case I40E_PCI_LINK_WIDTH_4: 4547 hw->bus.width = i40e_bus_width_pcie_x4; 4548 break; 4549 case I40E_PCI_LINK_WIDTH_8: 4550 hw->bus.width = i40e_bus_width_pcie_x8; 4551 break; 4552 default: 4553 hw->bus.width = i40e_bus_width_unknown; 4554 break; 4555 } 4556 4557 switch (link & I40E_PCI_LINK_SPEED) { 4558 case I40E_PCI_LINK_SPEED_2500: 4559 hw->bus.speed = i40e_bus_speed_2500; 4560 break; 4561 case I40E_PCI_LINK_SPEED_5000: 4562 hw->bus.speed = i40e_bus_speed_5000; 4563 break; 4564 case I40E_PCI_LINK_SPEED_8000: 4565 hw->bus.speed = i40e_bus_speed_8000; 4566 break; 4567 default: 4568 hw->bus.speed = i40e_bus_speed_unknown; 4569 break; 4570 } 4571 4572 4573 device_printf(dev,"PCI Express Bus: Speed %s %s\n", 4574 ((hw->bus.speed == i40e_bus_speed_8000) ? "8.0GT/s": 4575 (hw->bus.speed == i40e_bus_speed_5000) ? "5.0GT/s": 4576 (hw->bus.speed == i40e_bus_speed_2500) ? "2.5GT/s":"Unknown"), 4577 (hw->bus.width == i40e_bus_width_pcie_x8) ? "Width x8" : 4578 (hw->bus.width == i40e_bus_width_pcie_x4) ? "Width x4" : 4579 (hw->bus.width == i40e_bus_width_pcie_x1) ? "Width x1" : 4580 ("Unknown")); 4581 4582 if ((hw->bus.width <= i40e_bus_width_pcie_x8) && 4583 (hw->bus.speed < i40e_bus_speed_8000)) { 4584 device_printf(dev, "PCI-Express bandwidth available" 4585 " for this device\n is not sufficient for" 4586 " normal operation.\n"); 4587 device_printf(dev, "For expected performance a x8 " 4588 "PCIE Gen3 slot is required.\n"); 4589 } 4590 4591 return (link); 4592} 4593 4594static int 4595ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS) 4596{ 4597 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4598 struct i40e_hw *hw = &pf->hw; 4599 char buf[32]; 4600 4601 snprintf(buf, sizeof(buf), 4602 "f%d.%d a%d.%d n%02x.%02x e%08x", 4603 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 4604 hw->aq.api_maj_ver, hw->aq.api_min_ver, 4605 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> 4606 IXL_NVM_VERSION_HI_SHIFT, 4607 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> 4608 IXL_NVM_VERSION_LO_SHIFT, 4609 hw->nvm.eetrack); 4610 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4611} 4612 4613 4614#ifdef IXL_DEBUG_SYSCTL 4615static int 4616ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS) 4617{ 4618 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4619 struct i40e_hw *hw = &pf->hw; 4620 struct i40e_link_status link_status; 4621 char buf[512]; 4622 4623 enum i40e_status_code aq_error = 0; 4624 4625 aq_error = i40e_aq_get_link_info(hw, TRUE, &link_status, NULL); 4626 if (aq_error) { 4627 printf("i40e_aq_get_link_info() error %d\n", aq_error); 4628 return (EPERM); 4629 } 4630 4631 sprintf(buf, "\n" 4632 "PHY Type : %#04x\n" 4633 "Speed : %#04x\n" 4634 "Link info: %#04x\n" 4635 "AN info : %#04x\n" 4636 "Ext info : %#04x", 4637 link_status.phy_type, link_status.link_speed, 4638 link_status.link_info, link_status.an_info, 4639 link_status.ext_info); 4640 4641 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4642} 4643 4644static int 4645ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS) 4646{ 4647 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4648 struct i40e_hw *hw = &pf->hw; 4649 struct i40e_aq_get_phy_abilities_resp abilities_resp; 4650 char buf[512]; 4651 4652 enum i40e_status_code aq_error = 0; 4653 4654 // TODO: Print out list of qualified modules as well? 4655 aq_error = i40e_aq_get_phy_capabilities(hw, TRUE, FALSE, &abilities_resp, NULL); 4656 if (aq_error) { 4657 printf("i40e_aq_get_phy_capabilities() error %d\n", aq_error); 4658 return (EPERM); 4659 } 4660 4661 sprintf(buf, "\n" 4662 "PHY Type : %#010x\n" 4663 "Speed : %#04x\n" 4664 "Abilities: %#04x\n" 4665 "EEE cap : %#06x\n" 4666 "EEER reg : %#010x\n" 4667 "D3 Lpan : %#04x", 4668 abilities_resp.phy_type, abilities_resp.link_speed, 4669 abilities_resp.abilities, abilities_resp.eee_capability, 4670 abilities_resp.eeer_val, abilities_resp.d3_lpan); 4671 4672 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4673} 4674 4675static int 4676ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS) 4677{ 4678 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4679 struct ixl_vsi *vsi = &pf->vsi; 4680 struct ixl_mac_filter *f; 4681 char *buf, *buf_i; 4682 4683 int error = 0; 4684 int ftl_len = 0; 4685 int ftl_counter = 0; 4686 int buf_len = 0; 4687 int entry_len = 42; 4688 4689 SLIST_FOREACH(f, &vsi->ftl, next) { 4690 ftl_len++; 4691 } 4692 4693 if (ftl_len < 1) { 4694 sysctl_handle_string(oidp, "(none)", 6, req); 4695 return (0); 4696 } 4697 4698 buf_len = sizeof(char) * (entry_len + 1) * ftl_len + 2; 4699 buf = buf_i = malloc(buf_len, M_DEVBUF, M_NOWAIT); 4700 4701 sprintf(buf_i++, "\n"); 4702 SLIST_FOREACH(f, &vsi->ftl, next) { 4703 sprintf(buf_i, 4704 MAC_FORMAT ", vlan %4d, flags %#06x", 4705 MAC_FORMAT_ARGS(f->macaddr), f->vlan, f->flags); 4706 buf_i += entry_len; 4707 /* don't print '\n' for last entry */ 4708 if (++ftl_counter != ftl_len) { 4709 sprintf(buf_i, "\n"); 4710 buf_i++; 4711 } 4712 } 4713 4714 error = sysctl_handle_string(oidp, buf, strlen(buf), req); 4715 if (error) 4716 printf("sysctl error: %d\n", error); 4717 free(buf, M_DEVBUF); 4718 return error; 4719} 4720 4721#define IXL_SW_RES_SIZE 0x14 4722static int 4723ixl_res_alloc_cmp(const void *a, const void *b) 4724{ 4725 const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two; 4726 one = (struct i40e_aqc_switch_resource_alloc_element_resp *)a; 4727 two = (struct i40e_aqc_switch_resource_alloc_element_resp *)b; 4728 4729 return ((int)one->resource_type - (int)two->resource_type); 4730} 4731 4732static int 4733ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS) 4734{ 4735 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4736 struct i40e_hw *hw = &pf->hw; 4737 device_t dev = pf->dev; 4738 struct sbuf *buf; 4739 int error = 0; 4740 4741 u8 num_entries; 4742 struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE]; 4743 4744 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 4745 if (!buf) { 4746 device_printf(dev, "Could not allocate sbuf for output.\n"); 4747 return (ENOMEM); 4748 } 4749 4750 bzero(resp, sizeof(resp)); 4751 error = i40e_aq_get_switch_resource_alloc(hw, &num_entries, 4752 resp, 4753 IXL_SW_RES_SIZE, 4754 NULL); 4755 if (error) { 4756 device_printf(dev, "%s: get_switch_resource_alloc() error %d, aq error %d\n", 4757 __func__, error, hw->aq.asq_last_status); 4758 sbuf_delete(buf); 4759 return error; 4760 } 4761 4762 /* Sort entries by type for display */ 4763 qsort(resp, num_entries, 4764 sizeof(struct i40e_aqc_switch_resource_alloc_element_resp), 4765 &ixl_res_alloc_cmp); 4766 4767 sbuf_cat(buf, "\n"); 4768 sbuf_printf(buf, "# of entries: %d\n", num_entries); 4769 sbuf_printf(buf, 4770 "Type | Guaranteed | Total | Used | Un-allocated\n" 4771 " | (this) | (all) | (this) | (all) \n"); 4772 for (int i = 0; i < num_entries; i++) { 4773 sbuf_printf(buf, 4774 "%#4x | %10d %5d %6d %12d", 4775 resp[i].resource_type, 4776 resp[i].guaranteed, 4777 resp[i].total, 4778 resp[i].used, 4779 resp[i].total_unalloced); 4780 if (i < num_entries - 1) 4781 sbuf_cat(buf, "\n"); 4782 } 4783 4784 error = sbuf_finish(buf); 4785 if (error) { 4786 device_printf(dev, "Error finishing sbuf: %d\n", error); 4787 sbuf_delete(buf); 4788 return error; 4789 } 4790 4791 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 4792 if (error) 4793 device_printf(dev, "sysctl error: %d\n", error); 4794 sbuf_delete(buf); 4795 return error; 4796} 4797 4798/* 4799** Caller must init and delete sbuf; this function will clear and 4800** finish it for caller. 4801*/ 4802static char * 4803ixl_switch_element_string(struct sbuf *s, u16 seid, bool uplink) 4804{ 4805 sbuf_clear(s); 4806 4807 if (seid == 0 && uplink) 4808 sbuf_cat(s, "Network"); 4809 else if (seid == 0) 4810 sbuf_cat(s, "Host"); 4811 else if (seid == 1) 4812 sbuf_cat(s, "EMP"); 4813 else if (seid <= 5) 4814 sbuf_printf(s, "MAC %d", seid - 2); 4815 else if (seid <= 15) 4816 sbuf_cat(s, "Reserved"); 4817 else if (seid <= 31) 4818 sbuf_printf(s, "PF %d", seid - 16); 4819 else if (seid <= 159) 4820 sbuf_printf(s, "VF %d", seid - 32); 4821 else if (seid <= 287) 4822 sbuf_cat(s, "Reserved"); 4823 else if (seid <= 511) 4824 sbuf_cat(s, "Other"); // for other structures 4825 else if (seid <= 895) 4826 sbuf_printf(s, "VSI %d", seid - 512); 4827 else if (seid <= 1023) 4828 sbuf_printf(s, "Reserved"); 4829 else 4830 sbuf_cat(s, "Invalid"); 4831 4832 sbuf_finish(s); 4833 return sbuf_data(s); 4834} 4835 4836static int 4837ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS) 4838{ 4839 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4840 struct i40e_hw *hw = &pf->hw; 4841 device_t dev = pf->dev; 4842 struct sbuf *buf; 4843 struct sbuf *nmbuf; 4844 int error = 0; 4845 u8 aq_buf[I40E_AQ_LARGE_BUF]; 4846 4847 u16 next = 0; 4848 struct i40e_aqc_get_switch_config_resp *sw_config; 4849 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 4850 4851 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 4852 if (!buf) { 4853 device_printf(dev, "Could not allocate sbuf for sysctl output.\n"); 4854 return (ENOMEM); 4855 } 4856 4857 error = i40e_aq_get_switch_config(hw, sw_config, 4858 sizeof(aq_buf), &next, NULL); 4859 if (error) { 4860 device_printf(dev, "%s: aq_get_switch_config() error %d, aq error %d\n", 4861 __func__, error, hw->aq.asq_last_status); 4862 sbuf_delete(buf); 4863 return error; 4864 } 4865 4866 nmbuf = sbuf_new_auto(); 4867 if (!nmbuf) { 4868 device_printf(dev, "Could not allocate sbuf for name output.\n"); 4869 return (ENOMEM); 4870 } 4871 4872 sbuf_cat(buf, "\n"); 4873 // Assuming <= 255 elements in switch 4874 sbuf_printf(buf, "# of elements: %d\n", sw_config->header.num_reported); 4875 /* Exclude: 4876 ** Revision -- all elements are revision 1 for now 4877 */ 4878 sbuf_printf(buf, 4879 "SEID ( Name ) | Uplink | Downlink | Conn Type\n" 4880 " | | | (uplink)\n"); 4881 for (int i = 0; i < sw_config->header.num_reported; i++) { 4882 // "%4d (%8s) | %8s %8s %#8x", 4883 sbuf_printf(buf, "%4d", sw_config->element[i].seid); 4884 sbuf_cat(buf, " "); 4885 sbuf_printf(buf, "(%8s)", ixl_switch_element_string(nmbuf, sw_config->element[i].seid, false)); 4886 sbuf_cat(buf, " | "); 4887 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, sw_config->element[i].uplink_seid, true)); 4888 sbuf_cat(buf, " "); 4889 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, sw_config->element[i].downlink_seid, false)); 4890 sbuf_cat(buf, " "); 4891 sbuf_printf(buf, "%#8x", sw_config->element[i].connection_type); 4892 if (i < sw_config->header.num_reported - 1) 4893 sbuf_cat(buf, "\n"); 4894 } 4895 sbuf_delete(nmbuf); 4896 4897 error = sbuf_finish(buf); 4898 if (error) { 4899 device_printf(dev, "Error finishing sbuf: %d\n", error); 4900 sbuf_delete(buf); 4901 return error; 4902 } 4903 4904 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 4905 if (error) 4906 device_printf(dev, "sysctl error: %d\n", error); 4907 sbuf_delete(buf); 4908 4909 return (error); 4910} 4911 4912/* 4913** Dump TX desc given index. 4914** Doesn't work; don't use. 4915** TODO: Also needs a queue index input! 4916**/ 4917static int 4918ixl_sysctl_dump_txd(SYSCTL_HANDLER_ARGS) 4919{ 4920 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4921 device_t dev = pf->dev; 4922 struct sbuf *buf; 4923 int error = 0; 4924 4925 u16 desc_idx = 0; 4926 4927 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 4928 if (!buf) { 4929 device_printf(dev, "Could not allocate sbuf for output.\n"); 4930 return (ENOMEM); 4931 } 4932 4933 /* Read in index */ 4934 error = sysctl_handle_int(oidp, &desc_idx, 0, req); 4935 if (error) 4936 return (error); 4937 if (req->newptr == NULL) 4938 return (EIO); // fix 4939 if (desc_idx > 1024) { // fix 4940 device_printf(dev, 4941 "Invalid descriptor index, needs to be < 1024\n"); // fix 4942 return (EINVAL); 4943 } 4944 4945 // Don't use this sysctl yet 4946 if (TRUE) 4947 return (ENODEV); 4948 4949 sbuf_cat(buf, "\n"); 4950 4951 // set to queue 1? 4952 struct ixl_queue *que = pf->vsi.queues; 4953 struct tx_ring *txr = &(que[1].txr); 4954 struct i40e_tx_desc *txd = &txr->base[desc_idx]; 4955 4956 sbuf_printf(buf, "Que: %d, Desc: %d\n", que->me, desc_idx); 4957 sbuf_printf(buf, "Addr: %#18lx\n", txd->buffer_addr); 4958 sbuf_printf(buf, "Opts: %#18lx\n", txd->cmd_type_offset_bsz); 4959 4960 error = sbuf_finish(buf); 4961 if (error) { 4962 device_printf(dev, "Error finishing sbuf: %d\n", error); 4963 sbuf_delete(buf); 4964 return error; 4965 } 4966 4967 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 4968 if (error) 4969 device_printf(dev, "sysctl error: %d\n", error); 4970 sbuf_delete(buf); 4971 return error; 4972} 4973#endif /* IXL_DEBUG_SYSCTL */ 4974 4975