if_ixl.c revision 279232
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/if_ixl.c 279232 2015-02-24 06:20:50Z luigi $*/ 34 35#ifndef IXL_STANDALONE_BUILD 36#include "opt_inet.h" 37#include "opt_inet6.h" 38#include "opt_rss.h" 39#endif 40 41#include "ixl.h" 42#include "ixl_pf.h" 43 44#ifdef RSS 45#include <net/rss_config.h> 46#endif 47 48/********************************************************************* 49 * Driver version 50 *********************************************************************/ 51char ixl_driver_version[] = "1.3.6"; 52 53/********************************************************************* 54 * PCI Device ID Table 55 * 56 * Used by probe to select devices to load on 57 * Last field stores an index into ixl_strings 58 * Last entry must be all 0s 59 * 60 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 61 *********************************************************************/ 62 63static ixl_vendor_info_t ixl_vendor_info_array[] = 64{ 65 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710, 0, 0, 0}, 66 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A, 0, 0, 0}, 67 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B, 0, 0, 0}, 68 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C, 0, 0, 0}, 69 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A, 0, 0, 0}, 70 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B, 0, 0, 0}, 71 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0}, 72 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0}, 73 /* required last entry */ 74 {0, 0, 0, 0, 0} 75}; 76 77/********************************************************************* 78 * Table of branding strings 79 *********************************************************************/ 80 81static char *ixl_strings[] = { 82 "Intel(R) Ethernet Connection XL710 Driver" 83}; 84 85 86/********************************************************************* 87 * Function prototypes 88 *********************************************************************/ 89static int ixl_probe(device_t); 90static int ixl_attach(device_t); 91static int ixl_detach(device_t); 92static int ixl_shutdown(device_t); 93static int ixl_get_hw_capabilities(struct ixl_pf *); 94static void ixl_cap_txcsum_tso(struct ixl_vsi *, struct ifnet *, int); 95static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 96static void ixl_init(void *); 97static void ixl_init_locked(struct ixl_pf *); 98static void ixl_stop(struct ixl_pf *); 99static void ixl_media_status(struct ifnet *, struct ifmediareq *); 100static int ixl_media_change(struct ifnet *); 101static void ixl_update_link_status(struct ixl_pf *); 102static int ixl_allocate_pci_resources(struct ixl_pf *); 103static u16 ixl_get_bus_info(struct i40e_hw *, device_t); 104static int ixl_setup_stations(struct ixl_pf *); 105static int ixl_switch_config(struct ixl_pf *); 106static int ixl_initialize_vsi(struct ixl_vsi *); 107static int ixl_assign_vsi_msix(struct ixl_pf *); 108static int ixl_assign_vsi_legacy(struct ixl_pf *); 109static int ixl_init_msix(struct ixl_pf *); 110static void ixl_configure_msix(struct ixl_pf *); 111static void ixl_configure_itr(struct ixl_pf *); 112static void ixl_configure_legacy(struct ixl_pf *); 113static void ixl_free_pci_resources(struct ixl_pf *); 114static void ixl_local_timer(void *); 115static int ixl_setup_interface(device_t, struct ixl_vsi *); 116static bool ixl_config_link(struct i40e_hw *); 117static void ixl_config_rss(struct ixl_vsi *); 118static void ixl_set_queue_rx_itr(struct ixl_queue *); 119static void ixl_set_queue_tx_itr(struct ixl_queue *); 120static int ixl_set_advertised_speeds(struct ixl_pf *, int); 121 122static void ixl_enable_rings(struct ixl_vsi *); 123static void ixl_disable_rings(struct ixl_vsi *); 124static void ixl_enable_intr(struct ixl_vsi *); 125static void ixl_disable_intr(struct ixl_vsi *); 126 127static void ixl_enable_adminq(struct i40e_hw *); 128static void ixl_disable_adminq(struct i40e_hw *); 129static void ixl_enable_queue(struct i40e_hw *, int); 130static void ixl_disable_queue(struct i40e_hw *, int); 131static void ixl_enable_legacy(struct i40e_hw *); 132static void ixl_disable_legacy(struct i40e_hw *); 133 134static void ixl_set_promisc(struct ixl_vsi *); 135static void ixl_add_multi(struct ixl_vsi *); 136static void ixl_del_multi(struct ixl_vsi *); 137static void ixl_register_vlan(void *, struct ifnet *, u16); 138static void ixl_unregister_vlan(void *, struct ifnet *, u16); 139static void ixl_setup_vlan_filters(struct ixl_vsi *); 140 141static void ixl_init_filters(struct ixl_vsi *); 142static void ixl_add_filter(struct ixl_vsi *, u8 *, s16 vlan); 143static void ixl_del_filter(struct ixl_vsi *, u8 *, s16 vlan); 144static void ixl_add_hw_filters(struct ixl_vsi *, int, int); 145static void ixl_del_hw_filters(struct ixl_vsi *, int); 146static struct ixl_mac_filter * 147 ixl_find_filter(struct ixl_vsi *, u8 *, s16); 148static void ixl_add_mc_filter(struct ixl_vsi *, u8 *); 149 150/* Sysctl debug interface */ 151static int ixl_debug_info(SYSCTL_HANDLER_ARGS); 152static void ixl_print_debug_info(struct ixl_pf *); 153 154/* The MSI/X Interrupt handlers */ 155static void ixl_intr(void *); 156static void ixl_msix_que(void *); 157static void ixl_msix_adminq(void *); 158static void ixl_handle_mdd_event(struct ixl_pf *); 159 160/* Deferred interrupt tasklets */ 161static void ixl_do_adminq(void *, int); 162 163/* Sysctl handlers */ 164static int ixl_set_flowcntl(SYSCTL_HANDLER_ARGS); 165static int ixl_set_advertise(SYSCTL_HANDLER_ARGS); 166static int ixl_current_speed(SYSCTL_HANDLER_ARGS); 167static int ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS); 168 169/* Statistics */ 170static void ixl_add_hw_stats(struct ixl_pf *); 171static void ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *, 172 struct sysctl_oid_list *, struct i40e_hw_port_stats *); 173static void ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *, 174 struct sysctl_oid_list *, 175 struct i40e_eth_stats *); 176static void ixl_update_stats_counters(struct ixl_pf *); 177static void ixl_update_eth_stats(struct ixl_vsi *); 178static void ixl_pf_reset_stats(struct ixl_pf *); 179static void ixl_vsi_reset_stats(struct ixl_vsi *); 180static void ixl_stat_update48(struct i40e_hw *, u32, u32, bool, 181 u64 *, u64 *); 182static void ixl_stat_update32(struct i40e_hw *, u32, bool, 183 u64 *, u64 *); 184 185#ifdef IXL_DEBUG_SYSCTL 186static int ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS); 187static int ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS); 188static int ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS); 189static int ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS); 190static int ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS); 191static int ixl_sysctl_dump_txd(SYSCTL_HANDLER_ARGS); 192#endif 193 194/********************************************************************* 195 * FreeBSD Device Interface Entry Points 196 *********************************************************************/ 197 198static device_method_t ixl_methods[] = { 199 /* Device interface */ 200 DEVMETHOD(device_probe, ixl_probe), 201 DEVMETHOD(device_attach, ixl_attach), 202 DEVMETHOD(device_detach, ixl_detach), 203 DEVMETHOD(device_shutdown, ixl_shutdown), 204 {0, 0} 205}; 206 207static driver_t ixl_driver = { 208 "ixl", ixl_methods, sizeof(struct ixl_pf), 209}; 210 211devclass_t ixl_devclass; 212DRIVER_MODULE(ixl, pci, ixl_driver, ixl_devclass, 0, 0); 213 214MODULE_DEPEND(ixl, pci, 1, 1, 1); 215MODULE_DEPEND(ixl, ether, 1, 1, 1); 216#ifdef DEV_NETMAP 217MODULE_DEPEND(ixl, netmap, 1, 1, 1); 218#endif /* DEV_NETMAP */ 219 220/* 221** Global reset mutex 222*/ 223static struct mtx ixl_reset_mtx; 224 225/* 226** TUNEABLE PARAMETERS: 227*/ 228 229static SYSCTL_NODE(_hw, OID_AUTO, ixl, CTLFLAG_RD, 0, 230 "IXL driver parameters"); 231 232/* 233 * MSIX should be the default for best performance, 234 * but this allows it to be forced off for testing. 235 */ 236static int ixl_enable_msix = 1; 237TUNABLE_INT("hw.ixl.enable_msix", &ixl_enable_msix); 238SYSCTL_INT(_hw_ixl, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixl_enable_msix, 0, 239 "Enable MSI-X interrupts"); 240 241/* 242** Number of descriptors per ring: 243** - TX and RX are the same size 244*/ 245static int ixl_ringsz = DEFAULT_RING; 246TUNABLE_INT("hw.ixl.ringsz", &ixl_ringsz); 247SYSCTL_INT(_hw_ixl, OID_AUTO, ring_size, CTLFLAG_RDTUN, 248 &ixl_ringsz, 0, "Descriptor Ring Size"); 249 250/* 251** This can be set manually, if left as 0 the 252** number of queues will be calculated based 253** on cpus and msix vectors available. 254*/ 255int ixl_max_queues = 0; 256TUNABLE_INT("hw.ixl.max_queues", &ixl_max_queues); 257SYSCTL_INT(_hw_ixl, OID_AUTO, max_queues, CTLFLAG_RDTUN, 258 &ixl_max_queues, 0, "Number of Queues"); 259 260/* 261** Controls for Interrupt Throttling 262** - true/false for dynamic adjustment 263** - default values for static ITR 264*/ 265int ixl_dynamic_rx_itr = 0; 266TUNABLE_INT("hw.ixl.dynamic_rx_itr", &ixl_dynamic_rx_itr); 267SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_rx_itr, CTLFLAG_RDTUN, 268 &ixl_dynamic_rx_itr, 0, "Dynamic RX Interrupt Rate"); 269 270int ixl_dynamic_tx_itr = 0; 271TUNABLE_INT("hw.ixl.dynamic_tx_itr", &ixl_dynamic_tx_itr); 272SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_tx_itr, CTLFLAG_RDTUN, 273 &ixl_dynamic_tx_itr, 0, "Dynamic TX Interrupt Rate"); 274 275int ixl_rx_itr = IXL_ITR_8K; 276TUNABLE_INT("hw.ixl.rx_itr", &ixl_rx_itr); 277SYSCTL_INT(_hw_ixl, OID_AUTO, rx_itr, CTLFLAG_RDTUN, 278 &ixl_rx_itr, 0, "RX Interrupt Rate"); 279 280int ixl_tx_itr = IXL_ITR_4K; 281TUNABLE_INT("hw.ixl.tx_itr", &ixl_tx_itr); 282SYSCTL_INT(_hw_ixl, OID_AUTO, tx_itr, CTLFLAG_RDTUN, 283 &ixl_tx_itr, 0, "TX Interrupt Rate"); 284 285#ifdef IXL_FDIR 286static int ixl_enable_fdir = 1; 287TUNABLE_INT("hw.ixl.enable_fdir", &ixl_enable_fdir); 288/* Rate at which we sample */ 289int ixl_atr_rate = 20; 290TUNABLE_INT("hw.ixl.atr_rate", &ixl_atr_rate); 291#endif 292 293#ifdef DEV_NETMAP 294#define NETMAP_IXL_MAIN /* only bring in one part of the netmap code */ 295#include <dev/netmap/if_ixl_netmap.h> 296#endif /* DEV_NETMAP */ 297 298static char *ixl_fc_string[6] = { 299 "None", 300 "Rx", 301 "Tx", 302 "Full", 303 "Priority", 304 "Default" 305}; 306 307 308/********************************************************************* 309 * Device identification routine 310 * 311 * ixl_probe determines if the driver should be loaded on 312 * the hardware based on PCI vendor/device id of the device. 313 * 314 * return BUS_PROBE_DEFAULT on success, positive on failure 315 *********************************************************************/ 316 317static int 318ixl_probe(device_t dev) 319{ 320 ixl_vendor_info_t *ent; 321 322 u16 pci_vendor_id, pci_device_id; 323 u16 pci_subvendor_id, pci_subdevice_id; 324 char device_name[256]; 325 static bool lock_init = FALSE; 326 327 INIT_DEBUGOUT("ixl_probe: begin"); 328 329 pci_vendor_id = pci_get_vendor(dev); 330 if (pci_vendor_id != I40E_INTEL_VENDOR_ID) 331 return (ENXIO); 332 333 pci_device_id = pci_get_device(dev); 334 pci_subvendor_id = pci_get_subvendor(dev); 335 pci_subdevice_id = pci_get_subdevice(dev); 336 337 ent = ixl_vendor_info_array; 338 while (ent->vendor_id != 0) { 339 if ((pci_vendor_id == ent->vendor_id) && 340 (pci_device_id == ent->device_id) && 341 342 ((pci_subvendor_id == ent->subvendor_id) || 343 (ent->subvendor_id == 0)) && 344 345 ((pci_subdevice_id == ent->subdevice_id) || 346 (ent->subdevice_id == 0))) { 347 sprintf(device_name, "%s, Version - %s", 348 ixl_strings[ent->index], 349 ixl_driver_version); 350 device_set_desc_copy(dev, device_name); 351 /* One shot mutex init */ 352 if (lock_init == FALSE) { 353 lock_init = TRUE; 354 mtx_init(&ixl_reset_mtx, 355 "ixl_reset", 356 "IXL RESET Lock", MTX_DEF); 357 } 358 return (BUS_PROBE_DEFAULT); 359 } 360 ent++; 361 } 362 return (ENXIO); 363} 364 365/********************************************************************* 366 * Device initialization routine 367 * 368 * The attach entry point is called when the driver is being loaded. 369 * This routine identifies the type of hardware, allocates all resources 370 * and initializes the hardware. 371 * 372 * return 0 on success, positive on failure 373 *********************************************************************/ 374 375static int 376ixl_attach(device_t dev) 377{ 378 struct ixl_pf *pf; 379 struct i40e_hw *hw; 380 struct ixl_vsi *vsi; 381 u16 bus; 382 int error = 0; 383 384 INIT_DEBUGOUT("ixl_attach: begin"); 385 386 /* Allocate, clear, and link in our primary soft structure */ 387 pf = device_get_softc(dev); 388 pf->dev = pf->osdep.dev = dev; 389 hw = &pf->hw; 390 391 /* 392 ** Note this assumes we have a single embedded VSI, 393 ** this could be enhanced later to allocate multiple 394 */ 395 vsi = &pf->vsi; 396 vsi->dev = pf->dev; 397 398 /* Core Lock Init*/ 399 IXL_PF_LOCK_INIT(pf, device_get_nameunit(dev)); 400 401 /* Set up the timer callout */ 402 callout_init_mtx(&pf->timer, &pf->pf_mtx, 0); 403 404 /* Set up sysctls */ 405 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 406 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 407 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW, 408 pf, 0, ixl_set_flowcntl, "I", "Flow Control"); 409 410 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 411 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 412 OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW, 413 pf, 0, ixl_set_advertise, "I", "Advertised Speed"); 414 415 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 416 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 417 OID_AUTO, "current_speed", CTLTYPE_STRING | CTLFLAG_RD, 418 pf, 0, ixl_current_speed, "A", "Current Port Speed"); 419 420 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 421 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 422 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 423 pf, 0, ixl_sysctl_show_fw, "A", "Firmware version"); 424 425 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 426 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 427 OID_AUTO, "rx_itr", CTLFLAG_RW, 428 &ixl_rx_itr, IXL_ITR_8K, "RX ITR"); 429 430 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 431 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 432 OID_AUTO, "dynamic_rx_itr", CTLFLAG_RW, 433 &ixl_dynamic_rx_itr, 0, "Dynamic RX ITR"); 434 435 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 436 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 437 OID_AUTO, "tx_itr", CTLFLAG_RW, 438 &ixl_tx_itr, IXL_ITR_4K, "TX ITR"); 439 440 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 441 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 442 OID_AUTO, "dynamic_tx_itr", CTLFLAG_RW, 443 &ixl_dynamic_tx_itr, 0, "Dynamic TX ITR"); 444 445#ifdef IXL_DEBUG_SYSCTL 446 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 447 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 448 OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD, 449 pf, 0, ixl_sysctl_link_status, "A", "Current Link Status"); 450 451 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 452 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 453 OID_AUTO, "phy_abilities", CTLTYPE_STRING | CTLFLAG_RD, 454 pf, 0, ixl_sysctl_phy_abilities, "A", "PHY Abilities"); 455 456 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 457 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 458 OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD, 459 pf, 0, ixl_sysctl_sw_filter_list, "A", "SW Filter List"); 460 461 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 462 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 463 OID_AUTO, "hw_res_alloc", CTLTYPE_STRING | CTLFLAG_RD, 464 pf, 0, ixl_sysctl_hw_res_alloc, "A", "HW Resource Allocation"); 465 466 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 467 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 468 OID_AUTO, "switch_config", CTLTYPE_STRING | CTLFLAG_RD, 469 pf, 0, ixl_sysctl_switch_config, "A", "HW Switch Configuration"); 470 471 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 472 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 473 OID_AUTO, "dump_desc", CTLTYPE_INT | CTLFLAG_WR, 474 pf, 0, ixl_sysctl_dump_txd, "I", "Desc dump"); 475#endif 476 477 /* Save off the PCI information */ 478 hw->vendor_id = pci_get_vendor(dev); 479 hw->device_id = pci_get_device(dev); 480 hw->revision_id = pci_read_config(dev, PCIR_REVID, 1); 481 hw->subsystem_vendor_id = 482 pci_read_config(dev, PCIR_SUBVEND_0, 2); 483 hw->subsystem_device_id = 484 pci_read_config(dev, PCIR_SUBDEV_0, 2); 485 486 hw->bus.device = pci_get_slot(dev); 487 hw->bus.func = pci_get_function(dev); 488 489 /* Do PCI setup - map BAR0, etc */ 490 if (ixl_allocate_pci_resources(pf)) { 491 device_printf(dev, "Allocation of PCI resources failed\n"); 492 error = ENXIO; 493 goto err_out; 494 } 495 496 /* Create for initial debugging use */ 497 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 498 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 499 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0, 500 ixl_debug_info, "I", "Debug Information"); 501 502 503 /* Establish a clean starting point */ 504 i40e_clear_hw(hw); 505 error = i40e_pf_reset(hw); 506 if (error) { 507 device_printf(dev,"PF reset failure %x\n", error); 508 error = EIO; 509 goto err_out; 510 } 511 512 /* Set admin queue parameters */ 513 hw->aq.num_arq_entries = IXL_AQ_LEN; 514 hw->aq.num_asq_entries = IXL_AQ_LEN; 515 hw->aq.arq_buf_size = IXL_AQ_BUFSZ; 516 hw->aq.asq_buf_size = IXL_AQ_BUFSZ; 517 518 /* Initialize the shared code */ 519 error = i40e_init_shared_code(hw); 520 if (error) { 521 device_printf(dev,"Unable to initialize the shared code\n"); 522 error = EIO; 523 goto err_out; 524 } 525 526 /* Set up the admin queue */ 527 error = i40e_init_adminq(hw); 528 if (error) { 529 device_printf(dev, "The driver for the device stopped " 530 "because the NVM image is newer than expected.\n" 531 "You must install the most recent version of " 532 " the network driver.\n"); 533 goto err_out; 534 } 535 device_printf(dev, "%s\n", ixl_fw_version_str(hw)); 536 537 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 538 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) 539 device_printf(dev, "The driver for the device detected " 540 "a newer version of the NVM image than expected.\n" 541 "Please install the most recent version of the network driver.\n"); 542 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || 543 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) 544 device_printf(dev, "The driver for the device detected " 545 "an older version of the NVM image than expected.\n" 546 "Please update the NVM image.\n"); 547 548 /* Clear PXE mode */ 549 i40e_clear_pxe_mode(hw); 550 551 /* Get capabilities from the device */ 552 error = ixl_get_hw_capabilities(pf); 553 if (error) { 554 device_printf(dev, "HW capabilities failure!\n"); 555 goto err_get_cap; 556 } 557 558 /* Set up host memory cache */ 559 error = i40e_init_lan_hmc(hw, vsi->num_queues, vsi->num_queues, 0, 0); 560 if (error) { 561 device_printf(dev, "init_lan_hmc failed: %d\n", error); 562 goto err_get_cap; 563 } 564 565 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 566 if (error) { 567 device_printf(dev, "configure_lan_hmc failed: %d\n", error); 568 goto err_mac_hmc; 569 } 570 571 /* Disable LLDP from the firmware */ 572 i40e_aq_stop_lldp(hw, TRUE, NULL); 573 574 i40e_get_mac_addr(hw, hw->mac.addr); 575 error = i40e_validate_mac_addr(hw->mac.addr); 576 if (error) { 577 device_printf(dev, "validate_mac_addr failed: %d\n", error); 578 goto err_mac_hmc; 579 } 580 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN); 581 i40e_get_port_mac_addr(hw, hw->mac.port_addr); 582 583 /* Set up VSI and queues */ 584 if (ixl_setup_stations(pf) != 0) { 585 device_printf(dev, "setup stations failed!\n"); 586 error = ENOMEM; 587 goto err_mac_hmc; 588 } 589 590 /* Initialize mac filter list for VSI */ 591 SLIST_INIT(&vsi->ftl); 592 593 /* Set up interrupt routing here */ 594 if (pf->msix > 1) 595 error = ixl_assign_vsi_msix(pf); 596 else 597 error = ixl_assign_vsi_legacy(pf); 598 if (error) 599 goto err_late; 600 601 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || 602 (hw->aq.fw_maj_ver < 4)) { 603 i40e_msec_delay(75); 604 error = i40e_aq_set_link_restart_an(hw, TRUE, NULL); 605 if (error) 606 device_printf(dev, "link restart failed, aq_err=%d\n", 607 pf->hw.aq.asq_last_status); 608 } 609 610 /* Determine link state */ 611 vsi->link_up = ixl_config_link(hw); 612 613 /* Report if Unqualified modules are found */ 614 if ((vsi->link_up == FALSE) && 615 (pf->hw.phy.link_info.link_info & 616 I40E_AQ_MEDIA_AVAILABLE) && 617 (!(pf->hw.phy.link_info.an_info & 618 I40E_AQ_QUALIFIED_MODULE))) 619 device_printf(dev, "Link failed because " 620 "an unqualified module was detected\n"); 621 622 /* Setup OS specific network interface */ 623 if (ixl_setup_interface(dev, vsi) != 0) { 624 device_printf(dev, "interface setup failed!\n"); 625 error = EIO; 626 goto err_late; 627 } 628 629 error = ixl_switch_config(pf); 630 if (error) { 631 device_printf(dev, "Initial switch config failed: %d\n", error); 632 goto err_mac_hmc; 633 } 634 635 /* Limit phy interrupts to link and modules failure */ 636 error = i40e_aq_set_phy_int_mask(hw, 637 I40E_AQ_EVENT_LINK_UPDOWN | I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL); 638 if (error) 639 device_printf(dev, "set phy mask failed: %d\n", error); 640 641 /* Get the bus configuration and set the shared code */ 642 bus = ixl_get_bus_info(hw, dev); 643 i40e_set_pci_config_data(hw, bus); 644 645 /* Initialize statistics */ 646 ixl_pf_reset_stats(pf); 647 ixl_update_stats_counters(pf); 648 ixl_add_hw_stats(pf); 649 650 /* Register for VLAN events */ 651 vsi->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 652 ixl_register_vlan, vsi, EVENTHANDLER_PRI_FIRST); 653 vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 654 ixl_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST); 655 656 657#ifdef DEV_NETMAP 658 ixl_netmap_attach(vsi); 659#endif /* DEV_NETMAP */ 660 INIT_DEBUGOUT("ixl_attach: end"); 661 return (0); 662 663err_late: 664 if (vsi->ifp != NULL) 665 if_free(vsi->ifp); 666err_mac_hmc: 667 i40e_shutdown_lan_hmc(hw); 668err_get_cap: 669 i40e_shutdown_adminq(hw); 670err_out: 671 ixl_free_pci_resources(pf); 672 ixl_free_vsi(vsi); 673 IXL_PF_LOCK_DESTROY(pf); 674 return (error); 675} 676 677/********************************************************************* 678 * Device removal routine 679 * 680 * The detach entry point is called when the driver is being removed. 681 * This routine stops the adapter and deallocates all the resources 682 * that were allocated for driver operation. 683 * 684 * return 0 on success, positive on failure 685 *********************************************************************/ 686 687static int 688ixl_detach(device_t dev) 689{ 690 struct ixl_pf *pf = device_get_softc(dev); 691 struct i40e_hw *hw = &pf->hw; 692 struct ixl_vsi *vsi = &pf->vsi; 693 struct ixl_queue *que = vsi->queues; 694 i40e_status status; 695 696 INIT_DEBUGOUT("ixl_detach: begin"); 697 698 /* Make sure VLANS are not using driver */ 699 if (vsi->ifp->if_vlantrunk != NULL) { 700 device_printf(dev,"Vlan in use, detach first\n"); 701 return (EBUSY); 702 } 703 704 ether_ifdetach(vsi->ifp); 705 if (vsi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 706 IXL_PF_LOCK(pf); 707 ixl_stop(pf); 708 IXL_PF_UNLOCK(pf); 709 } 710 711 for (int i = 0; i < vsi->num_queues; i++, que++) { 712 if (que->tq) { 713 taskqueue_drain(que->tq, &que->task); 714 taskqueue_drain(que->tq, &que->tx_task); 715 taskqueue_free(que->tq); 716 } 717 } 718 719 /* Shutdown LAN HMC */ 720 status = i40e_shutdown_lan_hmc(hw); 721 if (status) 722 device_printf(dev, 723 "Shutdown LAN HMC failed with code %d\n", status); 724 725 /* Shutdown admin queue */ 726 status = i40e_shutdown_adminq(hw); 727 if (status) 728 device_printf(dev, 729 "Shutdown Admin queue failed with code %d\n", status); 730 731 /* Unregister VLAN events */ 732 if (vsi->vlan_attach != NULL) 733 EVENTHANDLER_DEREGISTER(vlan_config, vsi->vlan_attach); 734 if (vsi->vlan_detach != NULL) 735 EVENTHANDLER_DEREGISTER(vlan_unconfig, vsi->vlan_detach); 736 737 callout_drain(&pf->timer); 738#ifdef DEV_NETMAP 739 netmap_detach(vsi->ifp); 740#endif /* DEV_NETMAP */ 741 742 743 ixl_free_pci_resources(pf); 744 bus_generic_detach(dev); 745 if_free(vsi->ifp); 746 ixl_free_vsi(vsi); 747 IXL_PF_LOCK_DESTROY(pf); 748 return (0); 749} 750 751/********************************************************************* 752 * 753 * Shutdown entry point 754 * 755 **********************************************************************/ 756 757static int 758ixl_shutdown(device_t dev) 759{ 760 struct ixl_pf *pf = device_get_softc(dev); 761 IXL_PF_LOCK(pf); 762 ixl_stop(pf); 763 IXL_PF_UNLOCK(pf); 764 return (0); 765} 766 767 768/********************************************************************* 769 * 770 * Get the hardware capabilities 771 * 772 **********************************************************************/ 773 774static int 775ixl_get_hw_capabilities(struct ixl_pf *pf) 776{ 777 struct i40e_aqc_list_capabilities_element_resp *buf; 778 struct i40e_hw *hw = &pf->hw; 779 device_t dev = pf->dev; 780 int error, len; 781 u16 needed; 782 bool again = TRUE; 783 784 len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 785retry: 786 if (!(buf = (struct i40e_aqc_list_capabilities_element_resp *) 787 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO))) { 788 device_printf(dev, "Unable to allocate cap memory\n"); 789 return (ENOMEM); 790 } 791 792 /* This populates the hw struct */ 793 error = i40e_aq_discover_capabilities(hw, buf, len, 794 &needed, i40e_aqc_opc_list_func_capabilities, NULL); 795 free(buf, M_DEVBUF); 796 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) && 797 (again == TRUE)) { 798 /* retry once with a larger buffer */ 799 again = FALSE; 800 len = needed; 801 goto retry; 802 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { 803 device_printf(dev, "capability discovery failed: %d\n", 804 pf->hw.aq.asq_last_status); 805 return (ENODEV); 806 } 807 808 /* Capture this PF's starting queue pair */ 809 pf->qbase = hw->func_caps.base_queue; 810 811#ifdef IXL_DEBUG 812 device_printf(dev,"pf_id=%d, num_vfs=%d, msix_pf=%d, " 813 "msix_vf=%d, fd_g=%d, fd_b=%d, tx_qp=%d rx_qp=%d qbase=%d\n", 814 hw->pf_id, hw->func_caps.num_vfs, 815 hw->func_caps.num_msix_vectors, 816 hw->func_caps.num_msix_vectors_vf, 817 hw->func_caps.fd_filters_guaranteed, 818 hw->func_caps.fd_filters_best_effort, 819 hw->func_caps.num_tx_qp, 820 hw->func_caps.num_rx_qp, 821 hw->func_caps.base_queue); 822#endif 823 return (error); 824} 825 826static void 827ixl_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask) 828{ 829 device_t dev = vsi->dev; 830 831 /* Enable/disable TXCSUM/TSO4 */ 832 if (!(ifp->if_capenable & IFCAP_TXCSUM) 833 && !(ifp->if_capenable & IFCAP_TSO4)) { 834 if (mask & IFCAP_TXCSUM) { 835 ifp->if_capenable |= IFCAP_TXCSUM; 836 /* enable TXCSUM, restore TSO if previously enabled */ 837 if (vsi->flags & IXL_FLAGS_KEEP_TSO4) { 838 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 839 ifp->if_capenable |= IFCAP_TSO4; 840 } 841 } 842 else if (mask & IFCAP_TSO4) { 843 ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4); 844 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 845 device_printf(dev, 846 "TSO4 requires txcsum, enabling both...\n"); 847 } 848 } else if((ifp->if_capenable & IFCAP_TXCSUM) 849 && !(ifp->if_capenable & IFCAP_TSO4)) { 850 if (mask & IFCAP_TXCSUM) 851 ifp->if_capenable &= ~IFCAP_TXCSUM; 852 else if (mask & IFCAP_TSO4) 853 ifp->if_capenable |= IFCAP_TSO4; 854 } else if((ifp->if_capenable & IFCAP_TXCSUM) 855 && (ifp->if_capenable & IFCAP_TSO4)) { 856 if (mask & IFCAP_TXCSUM) { 857 vsi->flags |= IXL_FLAGS_KEEP_TSO4; 858 ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4); 859 device_printf(dev, 860 "TSO4 requires txcsum, disabling both...\n"); 861 } else if (mask & IFCAP_TSO4) 862 ifp->if_capenable &= ~IFCAP_TSO4; 863 } 864 865 /* Enable/disable TXCSUM_IPV6/TSO6 */ 866 if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6) 867 && !(ifp->if_capenable & IFCAP_TSO6)) { 868 if (mask & IFCAP_TXCSUM_IPV6) { 869 ifp->if_capenable |= IFCAP_TXCSUM_IPV6; 870 if (vsi->flags & IXL_FLAGS_KEEP_TSO6) { 871 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 872 ifp->if_capenable |= IFCAP_TSO6; 873 } 874 } else if (mask & IFCAP_TSO6) { 875 ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 876 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 877 device_printf(dev, 878 "TSO6 requires txcsum6, enabling both...\n"); 879 } 880 } else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 881 && !(ifp->if_capenable & IFCAP_TSO6)) { 882 if (mask & IFCAP_TXCSUM_IPV6) 883 ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6; 884 else if (mask & IFCAP_TSO6) 885 ifp->if_capenable |= IFCAP_TSO6; 886 } else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 887 && (ifp->if_capenable & IFCAP_TSO6)) { 888 if (mask & IFCAP_TXCSUM_IPV6) { 889 vsi->flags |= IXL_FLAGS_KEEP_TSO6; 890 ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 891 device_printf(dev, 892 "TSO6 requires txcsum6, disabling both...\n"); 893 } else if (mask & IFCAP_TSO6) 894 ifp->if_capenable &= ~IFCAP_TSO6; 895 } 896} 897 898/********************************************************************* 899 * Ioctl entry point 900 * 901 * ixl_ioctl is called when the user wants to configure the 902 * interface. 903 * 904 * return 0 on success, positive on failure 905 **********************************************************************/ 906 907static int 908ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 909{ 910 struct ixl_vsi *vsi = ifp->if_softc; 911 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 912 struct ifreq *ifr = (struct ifreq *) data; 913#if defined(INET) || defined(INET6) 914 struct ifaddr *ifa = (struct ifaddr *)data; 915 bool avoid_reset = FALSE; 916#endif 917 int error = 0; 918 919 switch (command) { 920 921 case SIOCSIFADDR: 922#ifdef INET 923 if (ifa->ifa_addr->sa_family == AF_INET) 924 avoid_reset = TRUE; 925#endif 926#ifdef INET6 927 if (ifa->ifa_addr->sa_family == AF_INET6) 928 avoid_reset = TRUE; 929#endif 930#if defined(INET) || defined(INET6) 931 /* 932 ** Calling init results in link renegotiation, 933 ** so we avoid doing it when possible. 934 */ 935 if (avoid_reset) { 936 ifp->if_flags |= IFF_UP; 937 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 938 ixl_init(pf); 939#ifdef INET 940 if (!(ifp->if_flags & IFF_NOARP)) 941 arp_ifinit(ifp, ifa); 942#endif 943 } else 944 error = ether_ioctl(ifp, command, data); 945 break; 946#endif 947 case SIOCSIFMTU: 948 IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)"); 949 if (ifr->ifr_mtu > IXL_MAX_FRAME - 950 ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) { 951 error = EINVAL; 952 } else { 953 IXL_PF_LOCK(pf); 954 ifp->if_mtu = ifr->ifr_mtu; 955 vsi->max_frame_size = 956 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 957 + ETHER_VLAN_ENCAP_LEN; 958 ixl_init_locked(pf); 959 IXL_PF_UNLOCK(pf); 960 } 961 break; 962 case SIOCSIFFLAGS: 963 IOCTL_DEBUGOUT("ioctl: SIOCSIFFLAGS (Set Interface Flags)"); 964 IXL_PF_LOCK(pf); 965 if (ifp->if_flags & IFF_UP) { 966 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 967 if ((ifp->if_flags ^ pf->if_flags) & 968 (IFF_PROMISC | IFF_ALLMULTI)) { 969 ixl_set_promisc(vsi); 970 } 971 } else 972 ixl_init_locked(pf); 973 } else 974 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 975 ixl_stop(pf); 976 pf->if_flags = ifp->if_flags; 977 IXL_PF_UNLOCK(pf); 978 break; 979 case SIOCADDMULTI: 980 IOCTL_DEBUGOUT("ioctl: SIOCADDMULTI"); 981 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 982 IXL_PF_LOCK(pf); 983 ixl_disable_intr(vsi); 984 ixl_add_multi(vsi); 985 ixl_enable_intr(vsi); 986 IXL_PF_UNLOCK(pf); 987 } 988 break; 989 case SIOCDELMULTI: 990 IOCTL_DEBUGOUT("ioctl: SIOCDELMULTI"); 991 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 992 IXL_PF_LOCK(pf); 993 ixl_disable_intr(vsi); 994 ixl_del_multi(vsi); 995 ixl_enable_intr(vsi); 996 IXL_PF_UNLOCK(pf); 997 } 998 break; 999 case SIOCSIFMEDIA: 1000 case SIOCGIFMEDIA: 1001 IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)"); 1002 error = ifmedia_ioctl(ifp, ifr, &vsi->media, command); 1003 break; 1004 case SIOCSIFCAP: 1005 { 1006 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1007 IOCTL_DEBUGOUT("ioctl: SIOCSIFCAP (Set Capabilities)"); 1008 1009 ixl_cap_txcsum_tso(vsi, ifp, mask); 1010 1011 if (mask & IFCAP_RXCSUM) 1012 ifp->if_capenable ^= IFCAP_RXCSUM; 1013 if (mask & IFCAP_RXCSUM_IPV6) 1014 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1015 if (mask & IFCAP_LRO) 1016 ifp->if_capenable ^= IFCAP_LRO; 1017 if (mask & IFCAP_VLAN_HWTAGGING) 1018 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1019 if (mask & IFCAP_VLAN_HWFILTER) 1020 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 1021 if (mask & IFCAP_VLAN_HWTSO) 1022 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1023 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1024 IXL_PF_LOCK(pf); 1025 ixl_init_locked(pf); 1026 IXL_PF_UNLOCK(pf); 1027 } 1028 VLAN_CAPABILITIES(ifp); 1029 1030 break; 1031 } 1032 1033 default: 1034 IOCTL_DEBUGOUT("ioctl: UNKNOWN (0x%X)\n", (int)command); 1035 error = ether_ioctl(ifp, command, data); 1036 break; 1037 } 1038 1039 return (error); 1040} 1041 1042 1043/********************************************************************* 1044 * Init entry point 1045 * 1046 * This routine is used in two ways. It is used by the stack as 1047 * init entry point in network interface structure. It is also used 1048 * by the driver as a hw/sw initialization routine to get to a 1049 * consistent state. 1050 * 1051 * return 0 on success, positive on failure 1052 **********************************************************************/ 1053 1054static void 1055ixl_init_locked(struct ixl_pf *pf) 1056{ 1057 struct i40e_hw *hw = &pf->hw; 1058 struct ixl_vsi *vsi = &pf->vsi; 1059 struct ifnet *ifp = vsi->ifp; 1060 device_t dev = pf->dev; 1061 struct i40e_filter_control_settings filter; 1062 u8 tmpaddr[ETHER_ADDR_LEN]; 1063 int ret; 1064 1065 mtx_assert(&pf->pf_mtx, MA_OWNED); 1066 INIT_DEBUGOUT("ixl_init: begin"); 1067 ixl_stop(pf); 1068 1069 /* Get the latest mac address... User might use a LAA */ 1070 bcopy(IF_LLADDR(vsi->ifp), tmpaddr, 1071 I40E_ETH_LENGTH_OF_ADDRESS); 1072 if (!cmp_etheraddr(hw->mac.addr, tmpaddr) && 1073 i40e_validate_mac_addr(tmpaddr)) { 1074 bcopy(tmpaddr, hw->mac.addr, 1075 I40E_ETH_LENGTH_OF_ADDRESS); 1076 ret = i40e_aq_mac_address_write(hw, 1077 I40E_AQC_WRITE_TYPE_LAA_ONLY, 1078 hw->mac.addr, NULL); 1079 if (ret) { 1080 device_printf(dev, "LLA address" 1081 "change failed!!\n"); 1082 return; 1083 } 1084 } 1085 1086 /* Set the various hardware offload abilities */ 1087 ifp->if_hwassist = 0; 1088 if (ifp->if_capenable & IFCAP_TSO) 1089 ifp->if_hwassist |= CSUM_TSO; 1090 if (ifp->if_capenable & IFCAP_TXCSUM) 1091 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1092 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 1093 ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6); 1094 1095 /* Set up the device filtering */ 1096 bzero(&filter, sizeof(filter)); 1097 filter.enable_ethtype = TRUE; 1098 filter.enable_macvlan = TRUE; 1099#ifdef IXL_FDIR 1100 filter.enable_fdir = TRUE; 1101#endif 1102 if (i40e_set_filter_control(hw, &filter)) 1103 device_printf(dev, "set_filter_control() failed\n"); 1104 1105 /* Set up RSS */ 1106 ixl_config_rss(vsi); 1107 1108 /* 1109 ** Prepare the VSI: rings, hmc contexts, etc... 1110 */ 1111 if (ixl_initialize_vsi(vsi)) { 1112 device_printf(dev, "initialize vsi failed!!\n"); 1113 return; 1114 } 1115 1116 /* Add protocol filters to list */ 1117 ixl_init_filters(vsi); 1118 1119 /* Setup vlan's if needed */ 1120 ixl_setup_vlan_filters(vsi); 1121 1122 /* Start the local timer */ 1123 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1124 1125 /* Set up MSI/X routing and the ITR settings */ 1126 if (ixl_enable_msix) { 1127 ixl_configure_msix(pf); 1128 ixl_configure_itr(pf); 1129 } else 1130 ixl_configure_legacy(pf); 1131 1132 ixl_enable_rings(vsi); 1133 1134 i40e_aq_set_default_vsi(hw, vsi->seid, NULL); 1135 1136 /* Set MTU in hardware*/ 1137 int aq_error = i40e_aq_set_mac_config(hw, vsi->max_frame_size, 1138 TRUE, 0, NULL); 1139 if (aq_error) 1140 device_printf(vsi->dev, 1141 "aq_set_mac_config in init error, code %d\n", 1142 aq_error); 1143 1144 /* And now turn on interrupts */ 1145 ixl_enable_intr(vsi); 1146 1147 /* Now inform the stack we're ready */ 1148 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1149 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1150 1151 return; 1152} 1153 1154static void 1155ixl_init(void *arg) 1156{ 1157 struct ixl_pf *pf = arg; 1158 1159 IXL_PF_LOCK(pf); 1160 ixl_init_locked(pf); 1161 IXL_PF_UNLOCK(pf); 1162 return; 1163} 1164 1165/* 1166** 1167** MSIX Interrupt Handlers and Tasklets 1168** 1169*/ 1170static void 1171ixl_handle_que(void *context, int pending) 1172{ 1173 struct ixl_queue *que = context; 1174 struct ixl_vsi *vsi = que->vsi; 1175 struct i40e_hw *hw = vsi->hw; 1176 struct tx_ring *txr = &que->txr; 1177 struct ifnet *ifp = vsi->ifp; 1178 bool more; 1179 1180 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1181 more = ixl_rxeof(que, IXL_RX_LIMIT); 1182 IXL_TX_LOCK(txr); 1183 ixl_txeof(que); 1184 if (!drbr_empty(ifp, txr->br)) 1185 ixl_mq_start_locked(ifp, txr); 1186 IXL_TX_UNLOCK(txr); 1187 if (more) { 1188 taskqueue_enqueue(que->tq, &que->task); 1189 return; 1190 } 1191 } 1192 1193 /* Reenable this interrupt - hmmm */ 1194 ixl_enable_queue(hw, que->me); 1195 return; 1196} 1197 1198 1199/********************************************************************* 1200 * 1201 * Legacy Interrupt Service routine 1202 * 1203 **********************************************************************/ 1204void 1205ixl_intr(void *arg) 1206{ 1207 struct ixl_pf *pf = arg; 1208 struct i40e_hw *hw = &pf->hw; 1209 struct ixl_vsi *vsi = &pf->vsi; 1210 struct ixl_queue *que = vsi->queues; 1211 struct ifnet *ifp = vsi->ifp; 1212 struct tx_ring *txr = &que->txr; 1213 u32 reg, icr0, mask; 1214 bool more_tx, more_rx; 1215 1216 ++que->irqs; 1217 1218 /* Protect against spurious interrupts */ 1219 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1220 return; 1221 1222 icr0 = rd32(hw, I40E_PFINT_ICR0); 1223 1224 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1225 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1226 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1227 1228 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1229 1230 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 1231 taskqueue_enqueue(pf->tq, &pf->adminq); 1232 return; 1233 } 1234 1235 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1236 1237 IXL_TX_LOCK(txr); 1238 more_tx = ixl_txeof(que); 1239 if (!drbr_empty(vsi->ifp, txr->br)) 1240 more_tx = 1; 1241 IXL_TX_UNLOCK(txr); 1242 1243 /* re-enable other interrupt causes */ 1244 wr32(hw, I40E_PFINT_ICR0_ENA, mask); 1245 1246 /* And now the queues */ 1247 reg = rd32(hw, I40E_QINT_RQCTL(0)); 1248 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1249 wr32(hw, I40E_QINT_RQCTL(0), reg); 1250 1251 reg = rd32(hw, I40E_QINT_TQCTL(0)); 1252 reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1253 reg &= ~I40E_PFINT_ICR0_INTEVENT_MASK; 1254 wr32(hw, I40E_QINT_TQCTL(0), reg); 1255 1256 ixl_enable_legacy(hw); 1257 1258 return; 1259} 1260 1261 1262/********************************************************************* 1263 * 1264 * MSIX VSI Interrupt Service routine 1265 * 1266 **********************************************************************/ 1267void 1268ixl_msix_que(void *arg) 1269{ 1270 struct ixl_queue *que = arg; 1271 struct ixl_vsi *vsi = que->vsi; 1272 struct i40e_hw *hw = vsi->hw; 1273 struct tx_ring *txr = &que->txr; 1274 bool more_tx, more_rx; 1275 1276 /* Protect against spurious interrupts */ 1277 if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING)) 1278 return; 1279 1280 ++que->irqs; 1281 1282 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1283 1284 IXL_TX_LOCK(txr); 1285 more_tx = ixl_txeof(que); 1286 /* 1287 ** Make certain that if the stack 1288 ** has anything queued the task gets 1289 ** scheduled to handle it. 1290 */ 1291 if (!drbr_empty(vsi->ifp, txr->br)) 1292 more_tx = 1; 1293 IXL_TX_UNLOCK(txr); 1294 1295 ixl_set_queue_rx_itr(que); 1296 ixl_set_queue_tx_itr(que); 1297 1298 if (more_tx || more_rx) 1299 taskqueue_enqueue(que->tq, &que->task); 1300 else 1301 ixl_enable_queue(hw, que->me); 1302 1303 return; 1304} 1305 1306 1307/********************************************************************* 1308 * 1309 * MSIX Admin Queue Interrupt Service routine 1310 * 1311 **********************************************************************/ 1312static void 1313ixl_msix_adminq(void *arg) 1314{ 1315 struct ixl_pf *pf = arg; 1316 struct i40e_hw *hw = &pf->hw; 1317 u32 reg, mask; 1318 1319 ++pf->admin_irq; 1320 1321 reg = rd32(hw, I40E_PFINT_ICR0); 1322 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1323 1324 /* Check on the cause */ 1325 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) 1326 mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 1327 1328 if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 1329 ixl_handle_mdd_event(pf); 1330 mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 1331 } 1332 1333 if (reg & I40E_PFINT_ICR0_VFLR_MASK) 1334 mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; 1335 1336 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1337 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1338 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1339 1340 taskqueue_enqueue(pf->tq, &pf->adminq); 1341 return; 1342} 1343 1344/********************************************************************* 1345 * 1346 * Media Ioctl callback 1347 * 1348 * This routine is called whenever the user queries the status of 1349 * the interface using ifconfig. 1350 * 1351 **********************************************************************/ 1352static void 1353ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr) 1354{ 1355 struct ixl_vsi *vsi = ifp->if_softc; 1356 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 1357 struct i40e_hw *hw = &pf->hw; 1358 1359 INIT_DEBUGOUT("ixl_media_status: begin"); 1360 IXL_PF_LOCK(pf); 1361 1362 ixl_update_link_status(pf); 1363 1364 ifmr->ifm_status = IFM_AVALID; 1365 ifmr->ifm_active = IFM_ETHER; 1366 1367 if (!vsi->link_up) { 1368 IXL_PF_UNLOCK(pf); 1369 return; 1370 } 1371 1372 ifmr->ifm_status |= IFM_ACTIVE; 1373 /* Hardware is always full-duplex */ 1374 ifmr->ifm_active |= IFM_FDX; 1375 1376 switch (hw->phy.link_info.phy_type) { 1377 /* 100 M */ 1378 case I40E_PHY_TYPE_100BASE_TX: 1379 ifmr->ifm_active |= IFM_100_TX; 1380 break; 1381 /* 1 G */ 1382 case I40E_PHY_TYPE_1000BASE_T: 1383 ifmr->ifm_active |= IFM_1000_T; 1384 break; 1385 case I40E_PHY_TYPE_1000BASE_SX: 1386 ifmr->ifm_active |= IFM_1000_SX; 1387 break; 1388 case I40E_PHY_TYPE_1000BASE_LX: 1389 ifmr->ifm_active |= IFM_1000_LX; 1390 break; 1391 /* 10 G */ 1392 case I40E_PHY_TYPE_10GBASE_CR1: 1393 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1394 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1395 /* Using this until a real KR media type */ 1396 case I40E_PHY_TYPE_10GBASE_KR: 1397 case I40E_PHY_TYPE_10GBASE_KX4: 1398 ifmr->ifm_active |= IFM_10G_TWINAX; 1399 break; 1400 case I40E_PHY_TYPE_10GBASE_SR: 1401 ifmr->ifm_active |= IFM_10G_SR; 1402 break; 1403 case I40E_PHY_TYPE_10GBASE_LR: 1404 ifmr->ifm_active |= IFM_10G_LR; 1405 break; 1406 case I40E_PHY_TYPE_10GBASE_T: 1407 ifmr->ifm_active |= IFM_10G_T; 1408 break; 1409 /* 40 G */ 1410 case I40E_PHY_TYPE_40GBASE_CR4: 1411 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1412 ifmr->ifm_active |= IFM_40G_CR4; 1413 break; 1414 case I40E_PHY_TYPE_40GBASE_SR4: 1415 ifmr->ifm_active |= IFM_40G_SR4; 1416 break; 1417 case I40E_PHY_TYPE_40GBASE_LR4: 1418 ifmr->ifm_active |= IFM_40G_LR4; 1419 break; 1420 /* 1421 ** Set these to CR4 because OS does not 1422 ** have types available yet. 1423 */ 1424 case I40E_PHY_TYPE_40GBASE_KR4: 1425 case I40E_PHY_TYPE_XLAUI: 1426 case I40E_PHY_TYPE_XLPPI: 1427 case I40E_PHY_TYPE_40GBASE_AOC: 1428 ifmr->ifm_active |= IFM_40G_CR4; 1429 break; 1430 default: 1431 ifmr->ifm_active |= IFM_UNKNOWN; 1432 break; 1433 } 1434 /* Report flow control status as well */ 1435 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) 1436 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 1437 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) 1438 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 1439 1440 IXL_PF_UNLOCK(pf); 1441 1442 return; 1443} 1444 1445/********************************************************************* 1446 * 1447 * Media Ioctl callback 1448 * 1449 * This routine is called when the user changes speed/duplex using 1450 * media/mediopt option with ifconfig. 1451 * 1452 **********************************************************************/ 1453static int 1454ixl_media_change(struct ifnet * ifp) 1455{ 1456 struct ixl_vsi *vsi = ifp->if_softc; 1457 struct ifmedia *ifm = &vsi->media; 1458 1459 INIT_DEBUGOUT("ixl_media_change: begin"); 1460 1461 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1462 return (EINVAL); 1463 1464 if_printf(ifp, "Media change is currently not supported.\n"); 1465 1466 return (ENODEV); 1467} 1468 1469 1470#ifdef IXL_FDIR 1471/* 1472** ATR: Application Targetted Receive - creates a filter 1473** based on TX flow info that will keep the receive 1474** portion of the flow on the same queue. Based on the 1475** implementation this is only available for TCP connections 1476*/ 1477void 1478ixl_atr(struct ixl_queue *que, struct tcphdr *th, int etype) 1479{ 1480 struct ixl_vsi *vsi = que->vsi; 1481 struct tx_ring *txr = &que->txr; 1482 struct i40e_filter_program_desc *FDIR; 1483 u32 ptype, dtype; 1484 int idx; 1485 1486 /* check if ATR is enabled and sample rate */ 1487 if ((!ixl_enable_fdir) || (!txr->atr_rate)) 1488 return; 1489 /* 1490 ** We sample all TCP SYN/FIN packets, 1491 ** or at the selected sample rate 1492 */ 1493 txr->atr_count++; 1494 if (((th->th_flags & (TH_FIN | TH_SYN)) == 0) && 1495 (txr->atr_count < txr->atr_rate)) 1496 return; 1497 txr->atr_count = 0; 1498 1499 /* Get a descriptor to use */ 1500 idx = txr->next_avail; 1501 FDIR = (struct i40e_filter_program_desc *) &txr->base[idx]; 1502 if (++idx == que->num_desc) 1503 idx = 0; 1504 txr->avail--; 1505 txr->next_avail = idx; 1506 1507 ptype = (que->me << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 1508 I40E_TXD_FLTR_QW0_QINDEX_MASK; 1509 1510 ptype |= (etype == ETHERTYPE_IP) ? 1511 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 1512 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 1513 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 1514 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 1515 1516 ptype |= vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 1517 1518 dtype = I40E_TX_DESC_DTYPE_FILTER_PROG; 1519 1520 /* 1521 ** We use the TCP TH_FIN as a trigger to remove 1522 ** the filter, otherwise its an update. 1523 */ 1524 dtype |= (th->th_flags & TH_FIN) ? 1525 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 1526 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 1527 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 1528 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 1529 1530 dtype |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 1531 I40E_TXD_FLTR_QW1_DEST_SHIFT; 1532 1533 dtype |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 1534 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 1535 1536 FDIR->qindex_flex_ptype_vsi = htole32(ptype); 1537 FDIR->dtype_cmd_cntindex = htole32(dtype); 1538 return; 1539} 1540#endif 1541 1542 1543static void 1544ixl_set_promisc(struct ixl_vsi *vsi) 1545{ 1546 struct ifnet *ifp = vsi->ifp; 1547 struct i40e_hw *hw = vsi->hw; 1548 int err, mcnt = 0; 1549 bool uni = FALSE, multi = FALSE; 1550 1551 if (ifp->if_flags & IFF_ALLMULTI) 1552 multi = TRUE; 1553 else { /* Need to count the multicast addresses */ 1554 struct ifmultiaddr *ifma; 1555 if_maddr_rlock(ifp); 1556 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1557 if (ifma->ifma_addr->sa_family != AF_LINK) 1558 continue; 1559 if (mcnt == MAX_MULTICAST_ADDR) 1560 break; 1561 mcnt++; 1562 } 1563 if_maddr_runlock(ifp); 1564 } 1565 1566 if (mcnt >= MAX_MULTICAST_ADDR) 1567 multi = TRUE; 1568 if (ifp->if_flags & IFF_PROMISC) 1569 uni = TRUE; 1570 1571 err = i40e_aq_set_vsi_unicast_promiscuous(hw, 1572 vsi->seid, uni, NULL); 1573 err = i40e_aq_set_vsi_multicast_promiscuous(hw, 1574 vsi->seid, multi, NULL); 1575 return; 1576} 1577 1578/********************************************************************* 1579 * Filter Routines 1580 * 1581 * Routines for multicast and vlan filter management. 1582 * 1583 *********************************************************************/ 1584static void 1585ixl_add_multi(struct ixl_vsi *vsi) 1586{ 1587 struct ifmultiaddr *ifma; 1588 struct ifnet *ifp = vsi->ifp; 1589 struct i40e_hw *hw = vsi->hw; 1590 int mcnt = 0, flags; 1591 1592 IOCTL_DEBUGOUT("ixl_add_multi: begin"); 1593 1594 if_maddr_rlock(ifp); 1595 /* 1596 ** First just get a count, to decide if we 1597 ** we simply use multicast promiscuous. 1598 */ 1599 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1600 if (ifma->ifma_addr->sa_family != AF_LINK) 1601 continue; 1602 mcnt++; 1603 } 1604 if_maddr_runlock(ifp); 1605 1606 if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) { 1607 /* delete existing MC filters */ 1608 ixl_del_hw_filters(vsi, mcnt); 1609 i40e_aq_set_vsi_multicast_promiscuous(hw, 1610 vsi->seid, TRUE, NULL); 1611 return; 1612 } 1613 1614 mcnt = 0; 1615 if_maddr_rlock(ifp); 1616 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1617 if (ifma->ifma_addr->sa_family != AF_LINK) 1618 continue; 1619 ixl_add_mc_filter(vsi, 1620 (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 1621 mcnt++; 1622 } 1623 if_maddr_runlock(ifp); 1624 if (mcnt > 0) { 1625 flags = (IXL_FILTER_ADD | IXL_FILTER_USED | IXL_FILTER_MC); 1626 ixl_add_hw_filters(vsi, flags, mcnt); 1627 } 1628 1629 IOCTL_DEBUGOUT("ixl_add_multi: end"); 1630 return; 1631} 1632 1633static void 1634ixl_del_multi(struct ixl_vsi *vsi) 1635{ 1636 struct ifnet *ifp = vsi->ifp; 1637 struct ifmultiaddr *ifma; 1638 struct ixl_mac_filter *f; 1639 int mcnt = 0; 1640 bool match = FALSE; 1641 1642 IOCTL_DEBUGOUT("ixl_del_multi: begin"); 1643 1644 /* Search for removed multicast addresses */ 1645 if_maddr_rlock(ifp); 1646 SLIST_FOREACH(f, &vsi->ftl, next) { 1647 if ((f->flags & IXL_FILTER_USED) && (f->flags & IXL_FILTER_MC)) { 1648 match = FALSE; 1649 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1650 if (ifma->ifma_addr->sa_family != AF_LINK) 1651 continue; 1652 u8 *mc_addr = (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1653 if (cmp_etheraddr(f->macaddr, mc_addr)) { 1654 match = TRUE; 1655 break; 1656 } 1657 } 1658 if (match == FALSE) { 1659 f->flags |= IXL_FILTER_DEL; 1660 mcnt++; 1661 } 1662 } 1663 } 1664 if_maddr_runlock(ifp); 1665 1666 if (mcnt > 0) 1667 ixl_del_hw_filters(vsi, mcnt); 1668} 1669 1670 1671/********************************************************************* 1672 * Timer routine 1673 * 1674 * This routine checks for link status,updates statistics, 1675 * and runs the watchdog check. 1676 * 1677 **********************************************************************/ 1678 1679static void 1680ixl_local_timer(void *arg) 1681{ 1682 struct ixl_pf *pf = arg; 1683 struct i40e_hw *hw = &pf->hw; 1684 struct ixl_vsi *vsi = &pf->vsi; 1685 struct ixl_queue *que = vsi->queues; 1686 device_t dev = pf->dev; 1687 int hung = 0; 1688 u32 mask; 1689 1690 mtx_assert(&pf->pf_mtx, MA_OWNED); 1691 1692 /* Fire off the adminq task */ 1693 taskqueue_enqueue(pf->tq, &pf->adminq); 1694 1695 /* Update stats */ 1696 ixl_update_stats_counters(pf); 1697 1698 /* 1699 ** Check status of the queues 1700 */ 1701 mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK | 1702 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK); 1703 1704 for (int i = 0; i < vsi->num_queues; i++,que++) { 1705 /* Any queues with outstanding work get a sw irq */ 1706 if (que->busy) 1707 wr32(hw, I40E_PFINT_DYN_CTLN(que->me), mask); 1708 /* 1709 ** Each time txeof runs without cleaning, but there 1710 ** are uncleaned descriptors it increments busy. If 1711 ** we get to 5 we declare it hung. 1712 */ 1713 if (que->busy == IXL_QUEUE_HUNG) { 1714 ++hung; 1715 /* Mark the queue as inactive */ 1716 vsi->active_queues &= ~((u64)1 << que->me); 1717 continue; 1718 } else { 1719 /* Check if we've come back from hung */ 1720 if ((vsi->active_queues & ((u64)1 << que->me)) == 0) 1721 vsi->active_queues |= ((u64)1 << que->me); 1722 } 1723 if (que->busy >= IXL_MAX_TX_BUSY) { 1724#ifdef IXL_DEBUG 1725 device_printf(dev,"Warning queue %d " 1726 "appears to be hung!\n", i); 1727#endif 1728 que->busy = IXL_QUEUE_HUNG; 1729 ++hung; 1730 } 1731 } 1732 /* Only reinit if all queues show hung */ 1733 if (hung == vsi->num_queues) 1734 goto hung; 1735 1736 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1737 return; 1738 1739hung: 1740 device_printf(dev, "Local Timer: HANG DETECT - Resetting!!\n"); 1741 ixl_init_locked(pf); 1742} 1743 1744/* 1745** Note: this routine updates the OS on the link state 1746** the real check of the hardware only happens with 1747** a link interrupt. 1748*/ 1749static void 1750ixl_update_link_status(struct ixl_pf *pf) 1751{ 1752 struct ixl_vsi *vsi = &pf->vsi; 1753 struct i40e_hw *hw = &pf->hw; 1754 struct ifnet *ifp = vsi->ifp; 1755 device_t dev = pf->dev; 1756 1757 1758 if (vsi->link_up){ 1759 if (vsi->link_active == FALSE) { 1760 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1761 pf->fc = hw->fc.current_mode; 1762 if (bootverbose) { 1763 device_printf(dev,"Link is up %d Gbps %s," 1764 " Flow Control: %s\n", 1765 ((vsi->link_speed == I40E_LINK_SPEED_40GB)? 40:10), 1766 "Full Duplex", ixl_fc_string[pf->fc]); 1767 } 1768 vsi->link_active = TRUE; 1769 /* 1770 ** Warn user if link speed on NPAR enabled 1771 ** partition is not at least 10GB 1772 */ 1773 if (hw->func_caps.npar_enable && 1774 (hw->phy.link_info.link_speed == I40E_LINK_SPEED_1GB || 1775 hw->phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) 1776 device_printf(dev, "The partition detected link" 1777 "speed that is less than 10Gbps\n"); 1778 if_link_state_change(ifp, LINK_STATE_UP); 1779 } 1780 } else { /* Link down */ 1781 if (vsi->link_active == TRUE) { 1782 if (bootverbose) 1783 device_printf(dev,"Link is Down\n"); 1784 if_link_state_change(ifp, LINK_STATE_DOWN); 1785 vsi->link_active = FALSE; 1786 } 1787 } 1788 1789 return; 1790} 1791 1792/********************************************************************* 1793 * 1794 * This routine disables all traffic on the adapter by issuing a 1795 * global reset on the MAC and deallocates TX/RX buffers. 1796 * 1797 **********************************************************************/ 1798 1799static void 1800ixl_stop(struct ixl_pf *pf) 1801{ 1802 struct ixl_vsi *vsi = &pf->vsi; 1803 struct ifnet *ifp = vsi->ifp; 1804 1805 mtx_assert(&pf->pf_mtx, MA_OWNED); 1806 1807 INIT_DEBUGOUT("ixl_stop: begin\n"); 1808 ixl_disable_intr(vsi); 1809 ixl_disable_rings(vsi); 1810 1811 /* Tell the stack that the interface is no longer active */ 1812 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1813 1814 /* Stop the local timer */ 1815 callout_stop(&pf->timer); 1816 1817 return; 1818} 1819 1820 1821/********************************************************************* 1822 * 1823 * Setup MSIX Interrupt resources and handlers for the VSI 1824 * 1825 **********************************************************************/ 1826static int 1827ixl_assign_vsi_legacy(struct ixl_pf *pf) 1828{ 1829 device_t dev = pf->dev; 1830 struct ixl_vsi *vsi = &pf->vsi; 1831 struct ixl_queue *que = vsi->queues; 1832 int error, rid = 0; 1833 1834 if (pf->msix == 1) 1835 rid = 1; 1836 pf->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1837 &rid, RF_SHAREABLE | RF_ACTIVE); 1838 if (pf->res == NULL) { 1839 device_printf(dev,"Unable to allocate" 1840 " bus resource: vsi legacy/msi interrupt\n"); 1841 return (ENXIO); 1842 } 1843 1844 /* Set the handler function */ 1845 error = bus_setup_intr(dev, pf->res, 1846 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1847 ixl_intr, pf, &pf->tag); 1848 if (error) { 1849 pf->res = NULL; 1850 device_printf(dev, "Failed to register legacy/msi handler"); 1851 return (error); 1852 } 1853 bus_describe_intr(dev, pf->res, pf->tag, "irq0"); 1854 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1855 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1856 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1857 taskqueue_thread_enqueue, &que->tq); 1858 taskqueue_start_threads(&que->tq, 1, PI_NET, "%s que", 1859 device_get_nameunit(dev)); 1860 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1861 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1862 taskqueue_thread_enqueue, &pf->tq); 1863 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1864 device_get_nameunit(dev)); 1865 1866 return (0); 1867} 1868 1869 1870/********************************************************************* 1871 * 1872 * Setup MSIX Interrupt resources and handlers for the VSI 1873 * 1874 **********************************************************************/ 1875static int 1876ixl_assign_vsi_msix(struct ixl_pf *pf) 1877{ 1878 device_t dev = pf->dev; 1879 struct ixl_vsi *vsi = &pf->vsi; 1880 struct ixl_queue *que = vsi->queues; 1881 struct tx_ring *txr; 1882 int error, rid, vector = 0; 1883 1884 /* Admin Que is vector 0*/ 1885 rid = vector + 1; 1886 pf->res = bus_alloc_resource_any(dev, 1887 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 1888 if (!pf->res) { 1889 device_printf(dev,"Unable to allocate" 1890 " bus resource: Adminq interrupt [%d]\n", rid); 1891 return (ENXIO); 1892 } 1893 /* Set the adminq vector and handler */ 1894 error = bus_setup_intr(dev, pf->res, 1895 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1896 ixl_msix_adminq, pf, &pf->tag); 1897 if (error) { 1898 pf->res = NULL; 1899 device_printf(dev, "Failed to register Admin que handler"); 1900 return (error); 1901 } 1902 bus_describe_intr(dev, pf->res, pf->tag, "aq"); 1903 pf->admvec = vector; 1904 /* Tasklet for Admin Queue */ 1905 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1906 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1907 taskqueue_thread_enqueue, &pf->tq); 1908 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1909 device_get_nameunit(pf->dev)); 1910 ++vector; 1911 1912 /* Now set up the stations */ 1913 for (int i = 0; i < vsi->num_queues; i++, vector++, que++) { 1914 int cpu_id = i; 1915 rid = vector + 1; 1916 txr = &que->txr; 1917 que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1918 RF_SHAREABLE | RF_ACTIVE); 1919 if (que->res == NULL) { 1920 device_printf(dev,"Unable to allocate" 1921 " bus resource: que interrupt [%d]\n", vector); 1922 return (ENXIO); 1923 } 1924 /* Set the handler function */ 1925 error = bus_setup_intr(dev, que->res, 1926 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1927 ixl_msix_que, que, &que->tag); 1928 if (error) { 1929 que->res = NULL; 1930 device_printf(dev, "Failed to register que handler"); 1931 return (error); 1932 } 1933 bus_describe_intr(dev, que->res, que->tag, "q%d", i); 1934 /* Bind the vector to a CPU */ 1935#ifdef RSS 1936 cpu_id = rss_getcpu(i % rss_getnumbuckets()); 1937#endif 1938 bus_bind_intr(dev, que->res, cpu_id); 1939 que->msix = vector; 1940 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1941 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1942 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1943 taskqueue_thread_enqueue, &que->tq); 1944#ifdef RSS 1945 taskqueue_start_threads_pinned(&que->tq, 1, PI_NET, 1946 cpu_id, "%s (bucket %d)", 1947 device_get_nameunit(dev), cpu_id); 1948#else 1949 taskqueue_start_threads(&que->tq, 1, PI_NET, 1950 "%s que", device_get_nameunit(dev)); 1951#endif 1952 } 1953 1954 return (0); 1955} 1956 1957 1958/* 1959 * Allocate MSI/X vectors 1960 */ 1961static int 1962ixl_init_msix(struct ixl_pf *pf) 1963{ 1964 device_t dev = pf->dev; 1965 int rid, want, vectors, queues, available; 1966 1967 /* Override by tuneable */ 1968 if (ixl_enable_msix == 0) 1969 goto msi; 1970 1971 /* 1972 ** When used in a virtualized environment 1973 ** PCI BUSMASTER capability may not be set 1974 ** so explicity set it here and rewrite 1975 ** the ENABLE in the MSIX control register 1976 ** at this point to cause the host to 1977 ** successfully initialize us. 1978 */ 1979 { 1980 u16 pci_cmd_word; 1981 int msix_ctrl; 1982 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1983 pci_cmd_word |= PCIM_CMD_BUSMASTEREN; 1984 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); 1985 pci_find_cap(dev, PCIY_MSIX, &rid); 1986 rid += PCIR_MSIX_CTRL; 1987 msix_ctrl = pci_read_config(dev, rid, 2); 1988 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1989 pci_write_config(dev, rid, msix_ctrl, 2); 1990 } 1991 1992 /* First try MSI/X */ 1993 rid = PCIR_BAR(IXL_BAR); 1994 pf->msix_mem = bus_alloc_resource_any(dev, 1995 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1996 if (!pf->msix_mem) { 1997 /* May not be enabled */ 1998 device_printf(pf->dev, 1999 "Unable to map MSIX table \n"); 2000 goto msi; 2001 } 2002 2003 available = pci_msix_count(dev); 2004 if (available == 0) { /* system has msix disabled */ 2005 bus_release_resource(dev, SYS_RES_MEMORY, 2006 rid, pf->msix_mem); 2007 pf->msix_mem = NULL; 2008 goto msi; 2009 } 2010 2011 /* Figure out a reasonable auto config value */ 2012 queues = (mp_ncpus > (available - 1)) ? (available - 1) : mp_ncpus; 2013 2014 /* Override with hardcoded value if sane */ 2015 if ((ixl_max_queues != 0) && (ixl_max_queues <= queues)) 2016 queues = ixl_max_queues; 2017 2018#ifdef RSS 2019 /* If we're doing RSS, clamp at the number of RSS buckets */ 2020 if (queues > rss_getnumbuckets()) 2021 queues = rss_getnumbuckets(); 2022#endif 2023 2024 /* 2025 ** Want one vector (RX/TX pair) per queue 2026 ** plus an additional for the admin queue. 2027 */ 2028 want = queues + 1; 2029 if (want <= available) /* Have enough */ 2030 vectors = want; 2031 else { 2032 device_printf(pf->dev, 2033 "MSIX Configuration Problem, " 2034 "%d vectors available but %d wanted!\n", 2035 available, want); 2036 return (0); /* Will go to Legacy setup */ 2037 } 2038 2039 if (pci_alloc_msix(dev, &vectors) == 0) { 2040 device_printf(pf->dev, 2041 "Using MSIX interrupts with %d vectors\n", vectors); 2042 pf->msix = vectors; 2043 pf->vsi.num_queues = queues; 2044#ifdef RSS 2045 /* 2046 * If we're doing RSS, the number of queues needs to 2047 * match the number of RSS buckets that are configured. 2048 * 2049 * + If there's more queues than RSS buckets, we'll end 2050 * up with queues that get no traffic. 2051 * 2052 * + If there's more RSS buckets than queues, we'll end 2053 * up having multiple RSS buckets map to the same queue, 2054 * so there'll be some contention. 2055 */ 2056 if (queues != rss_getnumbuckets()) { 2057 device_printf(dev, 2058 "%s: queues (%d) != RSS buckets (%d)" 2059 "; performance will be impacted.\n", 2060 __func__, queues, rss_getnumbuckets()); 2061 } 2062#endif 2063 return (vectors); 2064 } 2065msi: 2066 vectors = pci_msi_count(dev); 2067 pf->vsi.num_queues = 1; 2068 pf->msix = 1; 2069 ixl_max_queues = 1; 2070 ixl_enable_msix = 0; 2071 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) 2072 device_printf(pf->dev,"Using an MSI interrupt\n"); 2073 else { 2074 pf->msix = 0; 2075 device_printf(pf->dev,"Using a Legacy interrupt\n"); 2076 } 2077 return (vectors); 2078} 2079 2080 2081/* 2082 * Plumb MSI/X vectors 2083 */ 2084static void 2085ixl_configure_msix(struct ixl_pf *pf) 2086{ 2087 struct i40e_hw *hw = &pf->hw; 2088 struct ixl_vsi *vsi = &pf->vsi; 2089 u32 reg; 2090 u16 vector = 1; 2091 2092 /* First set up the adminq - vector 0 */ 2093 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 2094 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ 2095 2096 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 2097 I40E_PFINT_ICR0_ENA_GRST_MASK | 2098 I40E_PFINT_ICR0_HMC_ERR_MASK | 2099 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 2100 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 2101 I40E_PFINT_ICR0_ENA_VFLR_MASK | 2102 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK; 2103 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2104 2105 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 2106 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x003E); 2107 2108 wr32(hw, I40E_PFINT_DYN_CTL0, 2109 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | 2110 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); 2111 2112 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2113 2114 /* Next configure the queues */ 2115 for (int i = 0; i < vsi->num_queues; i++, vector++) { 2116 wr32(hw, I40E_PFINT_DYN_CTLN(i), i); 2117 wr32(hw, I40E_PFINT_LNKLSTN(i), i); 2118 2119 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 2120 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2121 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2122 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2123 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); 2124 wr32(hw, I40E_QINT_RQCTL(i), reg); 2125 2126 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 2127 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2128 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2129 ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2130 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2131 if (i == (vsi->num_queues - 1)) 2132 reg |= (IXL_QUEUE_EOL 2133 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2134 wr32(hw, I40E_QINT_TQCTL(i), reg); 2135 } 2136} 2137 2138/* 2139 * Configure for MSI single vector operation 2140 */ 2141static void 2142ixl_configure_legacy(struct ixl_pf *pf) 2143{ 2144 struct i40e_hw *hw = &pf->hw; 2145 u32 reg; 2146 2147 2148 wr32(hw, I40E_PFINT_ITR0(0), 0); 2149 wr32(hw, I40E_PFINT_ITR0(1), 0); 2150 2151 2152 /* Setup "other" causes */ 2153 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK 2154 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK 2155 | I40E_PFINT_ICR0_ENA_GRST_MASK 2156 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK 2157 | I40E_PFINT_ICR0_ENA_GPIO_MASK 2158 | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK 2159 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK 2160 | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK 2161 | I40E_PFINT_ICR0_ENA_VFLR_MASK 2162 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK 2163 ; 2164 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2165 2166 /* SW_ITR_IDX = 0, but don't change INTENA */ 2167 wr32(hw, I40E_PFINT_DYN_CTL0, 2168 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK | 2169 I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK); 2170 /* SW_ITR_IDX = 0, OTHER_ITR_IDX = 0 */ 2171 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2172 2173 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ 2174 wr32(hw, I40E_PFINT_LNKLST0, 0); 2175 2176 /* Associate the queue pair to the vector and enable the q int */ 2177 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK 2178 | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 2179 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2180 wr32(hw, I40E_QINT_RQCTL(0), reg); 2181 2182 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK 2183 | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 2184 | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2185 wr32(hw, I40E_QINT_TQCTL(0), reg); 2186 2187 /* Next enable the queue pair */ 2188 reg = rd32(hw, I40E_QTX_ENA(0)); 2189 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 2190 wr32(hw, I40E_QTX_ENA(0), reg); 2191 2192 reg = rd32(hw, I40E_QRX_ENA(0)); 2193 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 2194 wr32(hw, I40E_QRX_ENA(0), reg); 2195} 2196 2197 2198/* 2199 * Set the Initial ITR state 2200 */ 2201static void 2202ixl_configure_itr(struct ixl_pf *pf) 2203{ 2204 struct i40e_hw *hw = &pf->hw; 2205 struct ixl_vsi *vsi = &pf->vsi; 2206 struct ixl_queue *que = vsi->queues; 2207 2208 vsi->rx_itr_setting = ixl_rx_itr; 2209 if (ixl_dynamic_rx_itr) 2210 vsi->rx_itr_setting |= IXL_ITR_DYNAMIC; 2211 vsi->tx_itr_setting = ixl_tx_itr; 2212 if (ixl_dynamic_tx_itr) 2213 vsi->tx_itr_setting |= IXL_ITR_DYNAMIC; 2214 2215 for (int i = 0; i < vsi->num_queues; i++, que++) { 2216 struct tx_ring *txr = &que->txr; 2217 struct rx_ring *rxr = &que->rxr; 2218 2219 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), 2220 vsi->rx_itr_setting); 2221 rxr->itr = vsi->rx_itr_setting; 2222 rxr->latency = IXL_AVE_LATENCY; 2223 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), 2224 vsi->tx_itr_setting); 2225 txr->itr = vsi->tx_itr_setting; 2226 txr->latency = IXL_AVE_LATENCY; 2227 } 2228} 2229 2230 2231static int 2232ixl_allocate_pci_resources(struct ixl_pf *pf) 2233{ 2234 int rid; 2235 device_t dev = pf->dev; 2236 2237 rid = PCIR_BAR(0); 2238 pf->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2239 &rid, RF_ACTIVE); 2240 2241 if (!(pf->pci_mem)) { 2242 device_printf(dev,"Unable to allocate bus resource: memory\n"); 2243 return (ENXIO); 2244 } 2245 2246 pf->osdep.mem_bus_space_tag = 2247 rman_get_bustag(pf->pci_mem); 2248 pf->osdep.mem_bus_space_handle = 2249 rman_get_bushandle(pf->pci_mem); 2250 pf->osdep.mem_bus_space_size = rman_get_size(pf->pci_mem); 2251 pf->osdep.flush_reg = I40E_GLGEN_STAT; 2252 pf->hw.hw_addr = (u8 *) &pf->osdep.mem_bus_space_handle; 2253 2254 pf->hw.back = &pf->osdep; 2255 2256 /* 2257 ** Now setup MSI or MSI/X, should 2258 ** return us the number of supported 2259 ** vectors. (Will be 1 for MSI) 2260 */ 2261 pf->msix = ixl_init_msix(pf); 2262 return (0); 2263} 2264 2265static void 2266ixl_free_pci_resources(struct ixl_pf * pf) 2267{ 2268 struct ixl_vsi *vsi = &pf->vsi; 2269 struct ixl_queue *que = vsi->queues; 2270 device_t dev = pf->dev; 2271 int rid, memrid; 2272 2273 memrid = PCIR_BAR(IXL_BAR); 2274 2275 /* We may get here before stations are setup */ 2276 if ((!ixl_enable_msix) || (que == NULL)) 2277 goto early; 2278 2279 /* 2280 ** Release all msix VSI resources: 2281 */ 2282 for (int i = 0; i < vsi->num_queues; i++, que++) { 2283 rid = que->msix + 1; 2284 if (que->tag != NULL) { 2285 bus_teardown_intr(dev, que->res, que->tag); 2286 que->tag = NULL; 2287 } 2288 if (que->res != NULL) 2289 bus_release_resource(dev, SYS_RES_IRQ, rid, que->res); 2290 } 2291 2292early: 2293 /* Clean the AdminQ interrupt last */ 2294 if (pf->admvec) /* we are doing MSIX */ 2295 rid = pf->admvec + 1; 2296 else 2297 (pf->msix != 0) ? (rid = 1):(rid = 0); 2298 2299 if (pf->tag != NULL) { 2300 bus_teardown_intr(dev, pf->res, pf->tag); 2301 pf->tag = NULL; 2302 } 2303 if (pf->res != NULL) 2304 bus_release_resource(dev, SYS_RES_IRQ, rid, pf->res); 2305 2306 if (pf->msix) 2307 pci_release_msi(dev); 2308 2309 if (pf->msix_mem != NULL) 2310 bus_release_resource(dev, SYS_RES_MEMORY, 2311 memrid, pf->msix_mem); 2312 2313 if (pf->pci_mem != NULL) 2314 bus_release_resource(dev, SYS_RES_MEMORY, 2315 PCIR_BAR(0), pf->pci_mem); 2316 2317 return; 2318} 2319 2320static void 2321ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type) 2322{ 2323 /* Display supported media types */ 2324 if (phy_type & (1 << I40E_PHY_TYPE_100BASE_TX)) 2325 ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2326 2327 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_T)) 2328 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2329 2330 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) || 2331 phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4) || 2332 phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR) || 2333 phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) || 2334 phy_type & (1 << I40E_PHY_TYPE_XAUI) || 2335 phy_type & (1 << I40E_PHY_TYPE_XFI) || 2336 phy_type & (1 << I40E_PHY_TYPE_SFI) || 2337 phy_type & (1 << I40E_PHY_TYPE_10GBASE_SFPP_CU)) 2338 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2339 2340 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_SR)) 2341 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2342 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_LR)) 2343 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 2344 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_T)) 2345 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_T, 0, NULL); 2346 2347 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4) || 2348 phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4_CU) || 2349 phy_type & (1 << I40E_PHY_TYPE_40GBASE_AOC) || 2350 phy_type & (1 << I40E_PHY_TYPE_XLAUI) || 2351 phy_type & (1 << I40E_PHY_TYPE_XLPPI) || 2352 /* KR4 uses CR4 until the OS has the real media type */ 2353 phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2354 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2355 2356 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_SR4)) 2357 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2358 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_LR4)) 2359 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL); 2360} 2361 2362/********************************************************************* 2363 * 2364 * Setup networking device structure and register an interface. 2365 * 2366 **********************************************************************/ 2367static int 2368ixl_setup_interface(device_t dev, struct ixl_vsi *vsi) 2369{ 2370 struct ifnet *ifp; 2371 struct i40e_hw *hw = vsi->hw; 2372 struct ixl_queue *que = vsi->queues; 2373 struct i40e_aq_get_phy_abilities_resp abilities; 2374 enum i40e_status_code aq_error = 0; 2375 2376 INIT_DEBUGOUT("ixl_setup_interface: begin"); 2377 2378 ifp = vsi->ifp = if_alloc(IFT_ETHER); 2379 if (ifp == NULL) { 2380 device_printf(dev, "can not allocate ifnet structure\n"); 2381 return (-1); 2382 } 2383 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2384 ifp->if_mtu = ETHERMTU; 2385 ifp->if_baudrate = 4000000000; // ?? 2386 ifp->if_init = ixl_init; 2387 ifp->if_softc = vsi; 2388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2389 ifp->if_ioctl = ixl_ioctl; 2390 2391#if __FreeBSD_version >= 1100036 2392 if_setgetcounterfn(ifp, ixl_get_counter); 2393#endif 2394 2395 ifp->if_transmit = ixl_mq_start; 2396 2397 ifp->if_qflush = ixl_qflush; 2398 2399 ifp->if_snd.ifq_maxlen = que->num_desc - 2; 2400 2401 vsi->max_frame_size = 2402 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 2403 + ETHER_VLAN_ENCAP_LEN; 2404 2405 /* 2406 * Tell the upper layer(s) we support long frames. 2407 */ 2408 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2409 2410 ifp->if_capabilities |= IFCAP_HWCSUM; 2411 ifp->if_capabilities |= IFCAP_HWCSUM_IPV6; 2412 ifp->if_capabilities |= IFCAP_TSO; 2413 ifp->if_capabilities |= IFCAP_JUMBO_MTU; 2414 ifp->if_capabilities |= IFCAP_LRO; 2415 2416 /* VLAN capabilties */ 2417 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING 2418 | IFCAP_VLAN_HWTSO 2419 | IFCAP_VLAN_MTU 2420 | IFCAP_VLAN_HWCSUM; 2421 ifp->if_capenable = ifp->if_capabilities; 2422 2423 /* 2424 ** Don't turn this on by default, if vlans are 2425 ** created on another pseudo device (eg. lagg) 2426 ** then vlan events are not passed thru, breaking 2427 ** operation, but with HW FILTER off it works. If 2428 ** using vlans directly on the ixl driver you can 2429 ** enable this and get full hardware tag filtering. 2430 */ 2431 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER; 2432 2433 /* 2434 * Specify the media types supported by this adapter and register 2435 * callbacks to update media and link information 2436 */ 2437 ifmedia_init(&vsi->media, IFM_IMASK, ixl_media_change, 2438 ixl_media_status); 2439 2440 aq_error = i40e_aq_get_phy_capabilities(hw, 2441 FALSE, TRUE, &abilities, NULL); 2442 /* May need delay to detect fiber correctly */ 2443 if (aq_error == I40E_ERR_UNKNOWN_PHY) { 2444 i40e_msec_delay(200); 2445 aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, 2446 TRUE, &abilities, NULL); 2447 } 2448 if (aq_error) { 2449 if (aq_error == I40E_ERR_UNKNOWN_PHY) 2450 device_printf(dev, "Unknown PHY type detected!\n"); 2451 else 2452 device_printf(dev, 2453 "Error getting supported media types, err %d," 2454 " AQ error %d\n", aq_error, hw->aq.asq_last_status); 2455 return (0); 2456 } 2457 2458 ixl_add_ifmedia(vsi, abilities.phy_type); 2459 2460 /* Use autoselect media by default */ 2461 ifmedia_add(&vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2462 ifmedia_set(&vsi->media, IFM_ETHER | IFM_AUTO); 2463 2464 ether_ifattach(ifp, hw->mac.addr); 2465 2466 return (0); 2467} 2468 2469static bool 2470ixl_config_link(struct i40e_hw *hw) 2471{ 2472 bool check; 2473 2474 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2475 check = i40e_get_link_status(hw); 2476#ifdef IXL_DEBUG 2477 printf("Link is %s\n", check ? "up":"down"); 2478#endif 2479 return (check); 2480} 2481 2482/********************************************************************* 2483 * 2484 * Get Firmware Switch configuration 2485 * - this will need to be more robust when more complex 2486 * switch configurations are enabled. 2487 * 2488 **********************************************************************/ 2489static int 2490ixl_switch_config(struct ixl_pf *pf) 2491{ 2492 struct i40e_hw *hw = &pf->hw; 2493 struct ixl_vsi *vsi = &pf->vsi; 2494 device_t dev = vsi->dev; 2495 struct i40e_aqc_get_switch_config_resp *sw_config; 2496 u8 aq_buf[I40E_AQ_LARGE_BUF]; 2497 int ret = I40E_SUCCESS; 2498 u16 next = 0; 2499 2500 memset(&aq_buf, 0, sizeof(aq_buf)); 2501 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 2502 ret = i40e_aq_get_switch_config(hw, sw_config, 2503 sizeof(aq_buf), &next, NULL); 2504 if (ret) { 2505 device_printf(dev,"aq_get_switch_config failed!!\n"); 2506 return (ret); 2507 } 2508#ifdef IXL_DEBUG 2509 printf("Switch config: header reported: %d in structure, %d total\n", 2510 sw_config->header.num_reported, sw_config->header.num_total); 2511 printf("type=%d seid=%d uplink=%d downlink=%d\n", 2512 sw_config->element[0].element_type, 2513 sw_config->element[0].seid, 2514 sw_config->element[0].uplink_seid, 2515 sw_config->element[0].downlink_seid); 2516#endif 2517 /* Simplified due to a single VSI at the moment */ 2518 vsi->seid = sw_config->element[0].seid; 2519 return (ret); 2520} 2521 2522/********************************************************************* 2523 * 2524 * Initialize the VSI: this handles contexts, which means things 2525 * like the number of descriptors, buffer size, 2526 * plus we init the rings thru this function. 2527 * 2528 **********************************************************************/ 2529static int 2530ixl_initialize_vsi(struct ixl_vsi *vsi) 2531{ 2532 struct ixl_queue *que = vsi->queues; 2533 device_t dev = vsi->dev; 2534 struct i40e_hw *hw = vsi->hw; 2535 struct i40e_vsi_context ctxt; 2536 int err = 0; 2537 2538 memset(&ctxt, 0, sizeof(ctxt)); 2539 ctxt.seid = vsi->seid; 2540 ctxt.pf_num = hw->pf_id; 2541 err = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 2542 if (err) { 2543 device_printf(dev,"get vsi params failed %x!!\n", err); 2544 return (err); 2545 } 2546#ifdef IXL_DEBUG 2547 printf("get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, " 2548 "vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, " 2549 "pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid, 2550 ctxt.uplink_seid, ctxt.vsi_number, 2551 ctxt.vsis_allocated, ctxt.vsis_unallocated, 2552 ctxt.flags, ctxt.pf_num, ctxt.vf_num, 2553 ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits); 2554#endif 2555 /* 2556 ** Set the queue and traffic class bits 2557 ** - when multiple traffic classes are supported 2558 ** this will need to be more robust. 2559 */ 2560 ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; 2561 ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG; 2562 ctxt.info.queue_mapping[0] = 0; 2563 ctxt.info.tc_mapping[0] = 0x0800; 2564 2565 /* Set VLAN receive stripping mode */ 2566 ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID; 2567 ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL; 2568 if (vsi->ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2569 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 2570 else 2571 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 2572 2573 /* Keep copy of VSI info in VSI for statistic counters */ 2574 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 2575 2576 /* Reset VSI statistics */ 2577 ixl_vsi_reset_stats(vsi); 2578 vsi->hw_filters_add = 0; 2579 vsi->hw_filters_del = 0; 2580 2581 err = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 2582 if (err) { 2583 device_printf(dev,"update vsi params failed %x!!\n", 2584 hw->aq.asq_last_status); 2585 return (err); 2586 } 2587 2588 for (int i = 0; i < vsi->num_queues; i++, que++) { 2589 struct tx_ring *txr = &que->txr; 2590 struct rx_ring *rxr = &que->rxr; 2591 struct i40e_hmc_obj_txq tctx; 2592 struct i40e_hmc_obj_rxq rctx; 2593 u32 txctl; 2594 u16 size; 2595 2596 2597 /* Setup the HMC TX Context */ 2598 size = que->num_desc * sizeof(struct i40e_tx_desc); 2599 memset(&tctx, 0, sizeof(struct i40e_hmc_obj_txq)); 2600 tctx.new_context = 1; 2601 tctx.base = (txr->dma.pa/128); 2602 tctx.qlen = que->num_desc; 2603 tctx.fc_ena = 0; 2604 tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */ 2605 /* Enable HEAD writeback */ 2606 tctx.head_wb_ena = 1; 2607 tctx.head_wb_addr = txr->dma.pa + 2608 (que->num_desc * sizeof(struct i40e_tx_desc)); 2609 tctx.rdylist_act = 0; 2610 err = i40e_clear_lan_tx_queue_context(hw, i); 2611 if (err) { 2612 device_printf(dev, "Unable to clear TX context\n"); 2613 break; 2614 } 2615 err = i40e_set_lan_tx_queue_context(hw, i, &tctx); 2616 if (err) { 2617 device_printf(dev, "Unable to set TX context\n"); 2618 break; 2619 } 2620 /* Associate the ring with this PF */ 2621 txctl = I40E_QTX_CTL_PF_QUEUE; 2622 txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 2623 I40E_QTX_CTL_PF_INDX_MASK); 2624 wr32(hw, I40E_QTX_CTL(i), txctl); 2625 ixl_flush(hw); 2626 2627 /* Do ring (re)init */ 2628 ixl_init_tx_ring(que); 2629 2630 /* Next setup the HMC RX Context */ 2631 if (vsi->max_frame_size <= 2048) 2632 rxr->mbuf_sz = MCLBYTES; 2633 else 2634 rxr->mbuf_sz = MJUMPAGESIZE; 2635 2636 u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len; 2637 2638 /* Set up an RX context for the HMC */ 2639 memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq)); 2640 rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT; 2641 /* ignore header split for now */ 2642 rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT; 2643 rctx.rxmax = (vsi->max_frame_size < max_rxmax) ? 2644 vsi->max_frame_size : max_rxmax; 2645 rctx.dtype = 0; 2646 rctx.dsize = 1; /* do 32byte descriptors */ 2647 rctx.hsplit_0 = 0; /* no HDR split initially */ 2648 rctx.base = (rxr->dma.pa/128); 2649 rctx.qlen = que->num_desc; 2650 rctx.tphrdesc_ena = 1; 2651 rctx.tphwdesc_ena = 1; 2652 rctx.tphdata_ena = 0; 2653 rctx.tphhead_ena = 0; 2654 rctx.lrxqthresh = 2; 2655 rctx.crcstrip = 1; 2656 rctx.l2tsel = 1; 2657 rctx.showiv = 1; 2658 rctx.fc_ena = 0; 2659 rctx.prefena = 1; 2660 2661 err = i40e_clear_lan_rx_queue_context(hw, i); 2662 if (err) { 2663 device_printf(dev, 2664 "Unable to clear RX context %d\n", i); 2665 break; 2666 } 2667 err = i40e_set_lan_rx_queue_context(hw, i, &rctx); 2668 if (err) { 2669 device_printf(dev, "Unable to set RX context %d\n", i); 2670 break; 2671 } 2672 err = ixl_init_rx_ring(que); 2673 if (err) { 2674 device_printf(dev, "Fail in init_rx_ring %d\n", i); 2675 break; 2676 } 2677 wr32(vsi->hw, I40E_QRX_TAIL(que->me), 0); 2678#ifdef DEV_NETMAP 2679 /* preserve queue */ 2680 if (vsi->ifp->if_capenable & IFCAP_NETMAP) { 2681 struct netmap_adapter *na = NA(vsi->ifp); 2682 struct netmap_kring *kring = &na->rx_rings[i]; 2683 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 2684 wr32(vsi->hw, I40E_QRX_TAIL(que->me), t); 2685 } else 2686#endif /* DEV_NETMAP */ 2687 wr32(vsi->hw, I40E_QRX_TAIL(que->me), que->num_desc - 1); 2688 } 2689 return (err); 2690} 2691 2692 2693/********************************************************************* 2694 * 2695 * Free all VSI structs. 2696 * 2697 **********************************************************************/ 2698void 2699ixl_free_vsi(struct ixl_vsi *vsi) 2700{ 2701 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 2702 struct ixl_queue *que = vsi->queues; 2703 struct ixl_mac_filter *f; 2704 2705 /* Free station queues */ 2706 for (int i = 0; i < vsi->num_queues; i++, que++) { 2707 struct tx_ring *txr = &que->txr; 2708 struct rx_ring *rxr = &que->rxr; 2709 2710 if (!mtx_initialized(&txr->mtx)) /* uninitialized */ 2711 continue; 2712 IXL_TX_LOCK(txr); 2713 ixl_free_que_tx(que); 2714 if (txr->base) 2715 i40e_free_dma_mem(&pf->hw, &txr->dma); 2716 IXL_TX_UNLOCK(txr); 2717 IXL_TX_LOCK_DESTROY(txr); 2718 2719 if (!mtx_initialized(&rxr->mtx)) /* uninitialized */ 2720 continue; 2721 IXL_RX_LOCK(rxr); 2722 ixl_free_que_rx(que); 2723 if (rxr->base) 2724 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2725 IXL_RX_UNLOCK(rxr); 2726 IXL_RX_LOCK_DESTROY(rxr); 2727 2728 } 2729 free(vsi->queues, M_DEVBUF); 2730 2731 /* Free VSI filter list */ 2732 while (!SLIST_EMPTY(&vsi->ftl)) { 2733 f = SLIST_FIRST(&vsi->ftl); 2734 SLIST_REMOVE_HEAD(&vsi->ftl, next); 2735 free(f, M_DEVBUF); 2736 } 2737} 2738 2739 2740/********************************************************************* 2741 * 2742 * Allocate memory for the VSI (virtual station interface) and their 2743 * associated queues, rings and the descriptors associated with each, 2744 * called only once at attach. 2745 * 2746 **********************************************************************/ 2747static int 2748ixl_setup_stations(struct ixl_pf *pf) 2749{ 2750 device_t dev = pf->dev; 2751 struct ixl_vsi *vsi; 2752 struct ixl_queue *que; 2753 struct tx_ring *txr; 2754 struct rx_ring *rxr; 2755 int rsize, tsize; 2756 int error = I40E_SUCCESS; 2757 2758 vsi = &pf->vsi; 2759 vsi->back = (void *)pf; 2760 vsi->hw = &pf->hw; 2761 vsi->id = 0; 2762 vsi->num_vlans = 0; 2763 2764 /* Get memory for the station queues */ 2765 if (!(vsi->queues = 2766 (struct ixl_queue *) malloc(sizeof(struct ixl_queue) * 2767 vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2768 device_printf(dev, "Unable to allocate queue memory\n"); 2769 error = ENOMEM; 2770 goto early; 2771 } 2772 2773 for (int i = 0; i < vsi->num_queues; i++) { 2774 que = &vsi->queues[i]; 2775 que->num_desc = ixl_ringsz; 2776 que->me = i; 2777 que->vsi = vsi; 2778 /* mark the queue as active */ 2779 vsi->active_queues |= (u64)1 << que->me; 2780 txr = &que->txr; 2781 txr->que = que; 2782 txr->tail = I40E_QTX_TAIL(que->me); 2783 2784 /* Initialize the TX lock */ 2785 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 2786 device_get_nameunit(dev), que->me); 2787 mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF); 2788 /* Create the TX descriptor ring */ 2789 tsize = roundup2((que->num_desc * 2790 sizeof(struct i40e_tx_desc)) + 2791 sizeof(u32), DBA_ALIGN); 2792 if (i40e_allocate_dma_mem(&pf->hw, 2793 &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) { 2794 device_printf(dev, 2795 "Unable to allocate TX Descriptor memory\n"); 2796 error = ENOMEM; 2797 goto fail; 2798 } 2799 txr->base = (struct i40e_tx_desc *)txr->dma.va; 2800 bzero((void *)txr->base, tsize); 2801 /* Now allocate transmit soft structs for the ring */ 2802 if (ixl_allocate_tx_data(que)) { 2803 device_printf(dev, 2804 "Critical Failure setting up TX structures\n"); 2805 error = ENOMEM; 2806 goto fail; 2807 } 2808 /* Allocate a buf ring */ 2809 txr->br = buf_ring_alloc(4096, M_DEVBUF, 2810 M_WAITOK, &txr->mtx); 2811 if (txr->br == NULL) { 2812 device_printf(dev, 2813 "Critical Failure setting up TX buf ring\n"); 2814 error = ENOMEM; 2815 goto fail; 2816 } 2817 2818 /* 2819 * Next the RX queues... 2820 */ 2821 rsize = roundup2(que->num_desc * 2822 sizeof(union i40e_rx_desc), DBA_ALIGN); 2823 rxr = &que->rxr; 2824 rxr->que = que; 2825 rxr->tail = I40E_QRX_TAIL(que->me); 2826 2827 /* Initialize the RX side lock */ 2828 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 2829 device_get_nameunit(dev), que->me); 2830 mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF); 2831 2832 if (i40e_allocate_dma_mem(&pf->hw, 2833 &rxr->dma, i40e_mem_reserved, rsize, 4096)) { 2834 device_printf(dev, 2835 "Unable to allocate RX Descriptor memory\n"); 2836 error = ENOMEM; 2837 goto fail; 2838 } 2839 rxr->base = (union i40e_rx_desc *)rxr->dma.va; 2840 bzero((void *)rxr->base, rsize); 2841 2842 /* Allocate receive soft structs for the ring*/ 2843 if (ixl_allocate_rx_data(que)) { 2844 device_printf(dev, 2845 "Critical Failure setting up receive structs\n"); 2846 error = ENOMEM; 2847 goto fail; 2848 } 2849 } 2850 2851 return (0); 2852 2853fail: 2854 for (int i = 0; i < vsi->num_queues; i++) { 2855 que = &vsi->queues[i]; 2856 rxr = &que->rxr; 2857 txr = &que->txr; 2858 if (rxr->base) 2859 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2860 if (txr->base) 2861 i40e_free_dma_mem(&pf->hw, &txr->dma); 2862 } 2863 2864early: 2865 return (error); 2866} 2867 2868/* 2869** Provide a update to the queue RX 2870** interrupt moderation value. 2871*/ 2872static void 2873ixl_set_queue_rx_itr(struct ixl_queue *que) 2874{ 2875 struct ixl_vsi *vsi = que->vsi; 2876 struct i40e_hw *hw = vsi->hw; 2877 struct rx_ring *rxr = &que->rxr; 2878 u16 rx_itr; 2879 u16 rx_latency = 0; 2880 int rx_bytes; 2881 2882 2883 /* Idle, do nothing */ 2884 if (rxr->bytes == 0) 2885 return; 2886 2887 if (ixl_dynamic_rx_itr) { 2888 rx_bytes = rxr->bytes/rxr->itr; 2889 rx_itr = rxr->itr; 2890 2891 /* Adjust latency range */ 2892 switch (rxr->latency) { 2893 case IXL_LOW_LATENCY: 2894 if (rx_bytes > 10) { 2895 rx_latency = IXL_AVE_LATENCY; 2896 rx_itr = IXL_ITR_20K; 2897 } 2898 break; 2899 case IXL_AVE_LATENCY: 2900 if (rx_bytes > 20) { 2901 rx_latency = IXL_BULK_LATENCY; 2902 rx_itr = IXL_ITR_8K; 2903 } else if (rx_bytes <= 10) { 2904 rx_latency = IXL_LOW_LATENCY; 2905 rx_itr = IXL_ITR_100K; 2906 } 2907 break; 2908 case IXL_BULK_LATENCY: 2909 if (rx_bytes <= 20) { 2910 rx_latency = IXL_AVE_LATENCY; 2911 rx_itr = IXL_ITR_20K; 2912 } 2913 break; 2914 } 2915 2916 rxr->latency = rx_latency; 2917 2918 if (rx_itr != rxr->itr) { 2919 /* do an exponential smoothing */ 2920 rx_itr = (10 * rx_itr * rxr->itr) / 2921 ((9 * rx_itr) + rxr->itr); 2922 rxr->itr = rx_itr & IXL_MAX_ITR; 2923 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 2924 que->me), rxr->itr); 2925 } 2926 } else { /* We may have have toggled to non-dynamic */ 2927 if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC) 2928 vsi->rx_itr_setting = ixl_rx_itr; 2929 /* Update the hardware if needed */ 2930 if (rxr->itr != vsi->rx_itr_setting) { 2931 rxr->itr = vsi->rx_itr_setting; 2932 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 2933 que->me), rxr->itr); 2934 } 2935 } 2936 rxr->bytes = 0; 2937 rxr->packets = 0; 2938 return; 2939} 2940 2941 2942/* 2943** Provide a update to the queue TX 2944** interrupt moderation value. 2945*/ 2946static void 2947ixl_set_queue_tx_itr(struct ixl_queue *que) 2948{ 2949 struct ixl_vsi *vsi = que->vsi; 2950 struct i40e_hw *hw = vsi->hw; 2951 struct tx_ring *txr = &que->txr; 2952 u16 tx_itr; 2953 u16 tx_latency = 0; 2954 int tx_bytes; 2955 2956 2957 /* Idle, do nothing */ 2958 if (txr->bytes == 0) 2959 return; 2960 2961 if (ixl_dynamic_tx_itr) { 2962 tx_bytes = txr->bytes/txr->itr; 2963 tx_itr = txr->itr; 2964 2965 switch (txr->latency) { 2966 case IXL_LOW_LATENCY: 2967 if (tx_bytes > 10) { 2968 tx_latency = IXL_AVE_LATENCY; 2969 tx_itr = IXL_ITR_20K; 2970 } 2971 break; 2972 case IXL_AVE_LATENCY: 2973 if (tx_bytes > 20) { 2974 tx_latency = IXL_BULK_LATENCY; 2975 tx_itr = IXL_ITR_8K; 2976 } else if (tx_bytes <= 10) { 2977 tx_latency = IXL_LOW_LATENCY; 2978 tx_itr = IXL_ITR_100K; 2979 } 2980 break; 2981 case IXL_BULK_LATENCY: 2982 if (tx_bytes <= 20) { 2983 tx_latency = IXL_AVE_LATENCY; 2984 tx_itr = IXL_ITR_20K; 2985 } 2986 break; 2987 } 2988 2989 txr->latency = tx_latency; 2990 2991 if (tx_itr != txr->itr) { 2992 /* do an exponential smoothing */ 2993 tx_itr = (10 * tx_itr * txr->itr) / 2994 ((9 * tx_itr) + txr->itr); 2995 txr->itr = tx_itr & IXL_MAX_ITR; 2996 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 2997 que->me), txr->itr); 2998 } 2999 3000 } else { /* We may have have toggled to non-dynamic */ 3001 if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC) 3002 vsi->tx_itr_setting = ixl_tx_itr; 3003 /* Update the hardware if needed */ 3004 if (txr->itr != vsi->tx_itr_setting) { 3005 txr->itr = vsi->tx_itr_setting; 3006 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3007 que->me), txr->itr); 3008 } 3009 } 3010 txr->bytes = 0; 3011 txr->packets = 0; 3012 return; 3013} 3014 3015 3016static void 3017ixl_add_hw_stats(struct ixl_pf *pf) 3018{ 3019 device_t dev = pf->dev; 3020 struct ixl_vsi *vsi = &pf->vsi; 3021 struct ixl_queue *queues = vsi->queues; 3022 struct i40e_eth_stats *vsi_stats = &vsi->eth_stats; 3023 struct i40e_hw_port_stats *pf_stats = &pf->stats; 3024 3025 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3026 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3027 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3028 3029 struct sysctl_oid *vsi_node, *queue_node; 3030 struct sysctl_oid_list *vsi_list, *queue_list; 3031 3032 struct tx_ring *txr; 3033 struct rx_ring *rxr; 3034 3035 /* Driver statistics */ 3036 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 3037 CTLFLAG_RD, &pf->watchdog_events, 3038 "Watchdog timeouts"); 3039 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq", 3040 CTLFLAG_RD, &pf->admin_irq, 3041 "Admin Queue IRQ Handled"); 3042 3043 /* VSI statistics */ 3044#define QUEUE_NAME_LEN 32 3045 char queue_namebuf[QUEUE_NAME_LEN]; 3046 3047 // ERJ: Only one vsi now, re-do when >1 VSI enabled 3048 // snprintf(vsi_namebuf, QUEUE_NAME_LEN, "vsi%d", vsi->info.stat_counter_idx); 3049 vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "vsi", 3050 CTLFLAG_RD, NULL, "VSI-specific stats"); 3051 vsi_list = SYSCTL_CHILDREN(vsi_node); 3052 3053 ixl_add_sysctls_eth_stats(ctx, vsi_list, vsi_stats); 3054 3055 /* Queue statistics */ 3056 for (int q = 0; q < vsi->num_queues; q++) { 3057 snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q); 3058 queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, OID_AUTO, queue_namebuf, 3059 CTLFLAG_RD, NULL, "Queue #"); 3060 queue_list = SYSCTL_CHILDREN(queue_node); 3061 3062 txr = &(queues[q].txr); 3063 rxr = &(queues[q].rxr); 3064 3065 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed", 3066 CTLFLAG_RD, &(queues[q].mbuf_defrag_failed), 3067 "m_defrag() failed"); 3068 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "dropped", 3069 CTLFLAG_RD, &(queues[q].dropped_pkts), 3070 "Driver dropped packets"); 3071 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 3072 CTLFLAG_RD, &(queues[q].irqs), 3073 "irqs on this queue"); 3074 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 3075 CTLFLAG_RD, &(queues[q].tso), 3076 "TSO"); 3077 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dma_setup", 3078 CTLFLAG_RD, &(queues[q].tx_dma_setup), 3079 "Driver tx dma failure in xmit"); 3080 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail", 3081 CTLFLAG_RD, &(txr->no_desc), 3082 "Queue No Descriptor Available"); 3083 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 3084 CTLFLAG_RD, &(txr->total_packets), 3085 "Queue Packets Transmitted"); 3086 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes", 3087 CTLFLAG_RD, &(txr->tx_bytes), 3088 "Queue Bytes Transmitted"); 3089 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 3090 CTLFLAG_RD, &(rxr->rx_packets), 3091 "Queue Packets Received"); 3092 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 3093 CTLFLAG_RD, &(rxr->rx_bytes), 3094 "Queue Bytes Received"); 3095 } 3096 3097 /* MAC stats */ 3098 ixl_add_sysctls_mac_stats(ctx, child, pf_stats); 3099} 3100 3101static void 3102ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, 3103 struct sysctl_oid_list *child, 3104 struct i40e_eth_stats *eth_stats) 3105{ 3106 struct ixl_sysctl_info ctls[] = 3107 { 3108 {ð_stats->rx_bytes, "good_octets_rcvd", "Good Octets Received"}, 3109 {ð_stats->rx_unicast, "ucast_pkts_rcvd", 3110 "Unicast Packets Received"}, 3111 {ð_stats->rx_multicast, "mcast_pkts_rcvd", 3112 "Multicast Packets Received"}, 3113 {ð_stats->rx_broadcast, "bcast_pkts_rcvd", 3114 "Broadcast Packets Received"}, 3115 {ð_stats->rx_discards, "rx_discards", "Discarded RX packets"}, 3116 {ð_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"}, 3117 {ð_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"}, 3118 {ð_stats->tx_multicast, "mcast_pkts_txd", 3119 "Multicast Packets Transmitted"}, 3120 {ð_stats->tx_broadcast, "bcast_pkts_txd", 3121 "Broadcast Packets Transmitted"}, 3122 // end 3123 {0,0,0} 3124 }; 3125 3126 struct ixl_sysctl_info *entry = ctls; 3127 while (entry->stat != 0) 3128 { 3129 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, entry->name, 3130 CTLFLAG_RD, entry->stat, 3131 entry->description); 3132 entry++; 3133 } 3134} 3135 3136static void 3137ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx, 3138 struct sysctl_oid_list *child, 3139 struct i40e_hw_port_stats *stats) 3140{ 3141 struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac", 3142 CTLFLAG_RD, NULL, "Mac Statistics"); 3143 struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node); 3144 3145 struct i40e_eth_stats *eth_stats = &stats->eth; 3146 ixl_add_sysctls_eth_stats(ctx, stat_list, eth_stats); 3147 3148 struct ixl_sysctl_info ctls[] = 3149 { 3150 {&stats->crc_errors, "crc_errors", "CRC Errors"}, 3151 {&stats->illegal_bytes, "illegal_bytes", "Illegal Byte Errors"}, 3152 {&stats->mac_local_faults, "local_faults", "MAC Local Faults"}, 3153 {&stats->mac_remote_faults, "remote_faults", "MAC Remote Faults"}, 3154 {&stats->rx_length_errors, "rx_length_errors", "Receive Length Errors"}, 3155 /* Packet Reception Stats */ 3156 {&stats->rx_size_64, "rx_frames_64", "64 byte frames received"}, 3157 {&stats->rx_size_127, "rx_frames_65_127", "65-127 byte frames received"}, 3158 {&stats->rx_size_255, "rx_frames_128_255", "128-255 byte frames received"}, 3159 {&stats->rx_size_511, "rx_frames_256_511", "256-511 byte frames received"}, 3160 {&stats->rx_size_1023, "rx_frames_512_1023", "512-1023 byte frames received"}, 3161 {&stats->rx_size_1522, "rx_frames_1024_1522", "1024-1522 byte frames received"}, 3162 {&stats->rx_size_big, "rx_frames_big", "1523-9522 byte frames received"}, 3163 {&stats->rx_undersize, "rx_undersize", "Undersized packets received"}, 3164 {&stats->rx_fragments, "rx_fragmented", "Fragmented packets received"}, 3165 {&stats->rx_oversize, "rx_oversized", "Oversized packets received"}, 3166 {&stats->rx_jabber, "rx_jabber", "Received Jabber"}, 3167 {&stats->checksum_error, "checksum_errors", "Checksum Errors"}, 3168 /* Packet Transmission Stats */ 3169 {&stats->tx_size_64, "tx_frames_64", "64 byte frames transmitted"}, 3170 {&stats->tx_size_127, "tx_frames_65_127", "65-127 byte frames transmitted"}, 3171 {&stats->tx_size_255, "tx_frames_128_255", "128-255 byte frames transmitted"}, 3172 {&stats->tx_size_511, "tx_frames_256_511", "256-511 byte frames transmitted"}, 3173 {&stats->tx_size_1023, "tx_frames_512_1023", "512-1023 byte frames transmitted"}, 3174 {&stats->tx_size_1522, "tx_frames_1024_1522", "1024-1522 byte frames transmitted"}, 3175 {&stats->tx_size_big, "tx_frames_big", "1523-9522 byte frames transmitted"}, 3176 /* Flow control */ 3177 {&stats->link_xon_tx, "xon_txd", "Link XON transmitted"}, 3178 {&stats->link_xon_rx, "xon_recvd", "Link XON received"}, 3179 {&stats->link_xoff_tx, "xoff_txd", "Link XOFF transmitted"}, 3180 {&stats->link_xoff_rx, "xoff_recvd", "Link XOFF received"}, 3181 /* End */ 3182 {0,0,0} 3183 }; 3184 3185 struct ixl_sysctl_info *entry = ctls; 3186 while (entry->stat != 0) 3187 { 3188 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, entry->name, 3189 CTLFLAG_RD, entry->stat, 3190 entry->description); 3191 entry++; 3192 } 3193} 3194 3195/* 3196** ixl_config_rss - setup RSS 3197** - note this is done for the single vsi 3198*/ 3199static void ixl_config_rss(struct ixl_vsi *vsi) 3200{ 3201 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3202 struct i40e_hw *hw = vsi->hw; 3203 u32 lut = 0; 3204 u64 set_hena = 0, hena; 3205 int i, j, que_id; 3206#ifdef RSS 3207 u32 rss_hash_config; 3208 u32 rss_seed[IXL_KEYSZ]; 3209#else 3210 u32 rss_seed[IXL_KEYSZ] = {0x41b01687, 3211 0x183cfd8c, 0xce880440, 0x580cbc3c, 3212 0x35897377, 0x328b25e1, 0x4fa98922, 3213 0xb7d90c14, 0xd5bad70d, 0xcd15a2c1}; 3214#endif 3215 3216#ifdef RSS 3217 /* Fetch the configured RSS key */ 3218 rss_getkey((uint8_t *) &rss_seed); 3219#endif 3220 3221 /* Fill out hash function seed */ 3222 for (i = 0; i < IXL_KEYSZ; i++) 3223 wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]); 3224 3225 /* Enable PCTYPES for RSS: */ 3226#ifdef RSS 3227 rss_hash_config = rss_gethashconfig(); 3228 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 3229 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER); 3230 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 3231 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP); 3232 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 3233 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP); 3234 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 3235 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER); 3236 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 3237 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6); 3238 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 3239 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP); 3240 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 3241 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP); 3242#else 3243 set_hena = 3244 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | 3245 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | 3246 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | 3247 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | 3248 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | 3249 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | 3250 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | 3251 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | 3252 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | 3253 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | 3254 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD); 3255#endif 3256 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | 3257 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); 3258 hena |= set_hena; 3259 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); 3260 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 3261 3262 /* Populate the LUT with max no. of queues in round robin fashion */ 3263 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) { 3264 if (j == vsi->num_queues) 3265 j = 0; 3266#ifdef RSS 3267 /* 3268 * Fetch the RSS bucket id for the given indirection entry. 3269 * Cap it at the number of configured buckets (which is 3270 * num_queues.) 3271 */ 3272 que_id = rss_get_indirection_to_bucket(i); 3273 que_id = que_id % vsi->num_queues; 3274#else 3275 que_id = j; 3276#endif 3277 /* lut = 4-byte sliding window of 4 lut entries */ 3278 lut = (lut << 8) | (que_id & 3279 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1)); 3280 /* On i = 3, we have 4 entries in lut; write to the register */ 3281 if ((i & 3) == 3) 3282 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut); 3283 } 3284 ixl_flush(hw); 3285} 3286 3287 3288/* 3289** This routine is run via an vlan config EVENT, 3290** it enables us to use the HW Filter table since 3291** we can get the vlan id. This just creates the 3292** entry in the soft version of the VFTA, init will 3293** repopulate the real table. 3294*/ 3295static void 3296ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3297{ 3298 struct ixl_vsi *vsi = ifp->if_softc; 3299 struct i40e_hw *hw = vsi->hw; 3300 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3301 3302 if (ifp->if_softc != arg) /* Not our event */ 3303 return; 3304 3305 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3306 return; 3307 3308 IXL_PF_LOCK(pf); 3309 ++vsi->num_vlans; 3310 ixl_add_filter(vsi, hw->mac.addr, vtag); 3311 IXL_PF_UNLOCK(pf); 3312} 3313 3314/* 3315** This routine is run via an vlan 3316** unconfig EVENT, remove our entry 3317** in the soft vfta. 3318*/ 3319static void 3320ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3321{ 3322 struct ixl_vsi *vsi = ifp->if_softc; 3323 struct i40e_hw *hw = vsi->hw; 3324 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3325 3326 if (ifp->if_softc != arg) 3327 return; 3328 3329 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3330 return; 3331 3332 IXL_PF_LOCK(pf); 3333 --vsi->num_vlans; 3334 ixl_del_filter(vsi, hw->mac.addr, vtag); 3335 IXL_PF_UNLOCK(pf); 3336} 3337 3338/* 3339** This routine updates vlan filters, called by init 3340** it scans the filter table and then updates the hw 3341** after a soft reset. 3342*/ 3343static void 3344ixl_setup_vlan_filters(struct ixl_vsi *vsi) 3345{ 3346 struct ixl_mac_filter *f; 3347 int cnt = 0, flags; 3348 3349 if (vsi->num_vlans == 0) 3350 return; 3351 /* 3352 ** Scan the filter list for vlan entries, 3353 ** mark them for addition and then call 3354 ** for the AQ update. 3355 */ 3356 SLIST_FOREACH(f, &vsi->ftl, next) { 3357 if (f->flags & IXL_FILTER_VLAN) { 3358 f->flags |= 3359 (IXL_FILTER_ADD | 3360 IXL_FILTER_USED); 3361 cnt++; 3362 } 3363 } 3364 if (cnt == 0) { 3365 printf("setup vlan: no filters found!\n"); 3366 return; 3367 } 3368 flags = IXL_FILTER_VLAN; 3369 flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3370 ixl_add_hw_filters(vsi, flags, cnt); 3371 return; 3372} 3373 3374/* 3375** Initialize filter list and add filters that the hardware 3376** needs to know about. 3377*/ 3378static void 3379ixl_init_filters(struct ixl_vsi *vsi) 3380{ 3381 /* Add broadcast address */ 3382 u8 bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 3383 ixl_add_filter(vsi, bc, IXL_VLAN_ANY); 3384} 3385 3386/* 3387** This routine adds mulicast filters 3388*/ 3389static void 3390ixl_add_mc_filter(struct ixl_vsi *vsi, u8 *macaddr) 3391{ 3392 struct ixl_mac_filter *f; 3393 3394 /* Does one already exist */ 3395 f = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3396 if (f != NULL) 3397 return; 3398 3399 f = ixl_get_filter(vsi); 3400 if (f == NULL) { 3401 printf("WARNING: no filter available!!\n"); 3402 return; 3403 } 3404 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3405 f->vlan = IXL_VLAN_ANY; 3406 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED 3407 | IXL_FILTER_MC); 3408 3409 return; 3410} 3411 3412/* 3413** This routine adds macvlan filters 3414*/ 3415static void 3416ixl_add_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3417{ 3418 struct ixl_mac_filter *f, *tmp; 3419 device_t dev = vsi->dev; 3420 3421 DEBUGOUT("ixl_add_filter: begin"); 3422 3423 /* Does one already exist */ 3424 f = ixl_find_filter(vsi, macaddr, vlan); 3425 if (f != NULL) 3426 return; 3427 /* 3428 ** Is this the first vlan being registered, if so we 3429 ** need to remove the ANY filter that indicates we are 3430 ** not in a vlan, and replace that with a 0 filter. 3431 */ 3432 if ((vlan != IXL_VLAN_ANY) && (vsi->num_vlans == 1)) { 3433 tmp = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3434 if (tmp != NULL) { 3435 ixl_del_filter(vsi, macaddr, IXL_VLAN_ANY); 3436 ixl_add_filter(vsi, macaddr, 0); 3437 } 3438 } 3439 3440 f = ixl_get_filter(vsi); 3441 if (f == NULL) { 3442 device_printf(dev, "WARNING: no filter available!!\n"); 3443 return; 3444 } 3445 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3446 f->vlan = vlan; 3447 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3448 if (f->vlan != IXL_VLAN_ANY) 3449 f->flags |= IXL_FILTER_VLAN; 3450 3451 ixl_add_hw_filters(vsi, f->flags, 1); 3452 return; 3453} 3454 3455static void 3456ixl_del_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3457{ 3458 struct ixl_mac_filter *f; 3459 3460 f = ixl_find_filter(vsi, macaddr, vlan); 3461 if (f == NULL) 3462 return; 3463 3464 f->flags |= IXL_FILTER_DEL; 3465 ixl_del_hw_filters(vsi, 1); 3466 3467 /* Check if this is the last vlan removal */ 3468 if (vlan != IXL_VLAN_ANY && vsi->num_vlans == 0) { 3469 /* Switch back to a non-vlan filter */ 3470 ixl_del_filter(vsi, macaddr, 0); 3471 ixl_add_filter(vsi, macaddr, IXL_VLAN_ANY); 3472 } 3473 return; 3474} 3475 3476/* 3477** Find the filter with both matching mac addr and vlan id 3478*/ 3479static struct ixl_mac_filter * 3480ixl_find_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3481{ 3482 struct ixl_mac_filter *f; 3483 bool match = FALSE; 3484 3485 SLIST_FOREACH(f, &vsi->ftl, next) { 3486 if (!cmp_etheraddr(f->macaddr, macaddr)) 3487 continue; 3488 if (f->vlan == vlan) { 3489 match = TRUE; 3490 break; 3491 } 3492 } 3493 3494 if (!match) 3495 f = NULL; 3496 return (f); 3497} 3498 3499/* 3500** This routine takes additions to the vsi filter 3501** table and creates an Admin Queue call to create 3502** the filters in the hardware. 3503*/ 3504static void 3505ixl_add_hw_filters(struct ixl_vsi *vsi, int flags, int cnt) 3506{ 3507 struct i40e_aqc_add_macvlan_element_data *a, *b; 3508 struct ixl_mac_filter *f; 3509 struct i40e_hw *hw = vsi->hw; 3510 device_t dev = vsi->dev; 3511 int err, j = 0; 3512 3513 a = malloc(sizeof(struct i40e_aqc_add_macvlan_element_data) * cnt, 3514 M_DEVBUF, M_NOWAIT | M_ZERO); 3515 if (a == NULL) { 3516 device_printf(dev, "add_hw_filters failed to get memory\n"); 3517 return; 3518 } 3519 3520 /* 3521 ** Scan the filter list, each time we find one 3522 ** we add it to the admin queue array and turn off 3523 ** the add bit. 3524 */ 3525 SLIST_FOREACH(f, &vsi->ftl, next) { 3526 if (f->flags == flags) { 3527 b = &a[j]; // a pox on fvl long names :) 3528 bcopy(f->macaddr, b->mac_addr, ETHER_ADDR_LEN); 3529 b->vlan_tag = 3530 (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3531 b->flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 3532 f->flags &= ~IXL_FILTER_ADD; 3533 j++; 3534 } 3535 if (j == cnt) 3536 break; 3537 } 3538 if (j > 0) { 3539 err = i40e_aq_add_macvlan(hw, vsi->seid, a, j, NULL); 3540 if (err) 3541 device_printf(dev, "aq_add_macvlan err %d, " 3542 "aq_error %d\n", err, hw->aq.asq_last_status); 3543 else 3544 vsi->hw_filters_add += j; 3545 } 3546 free(a, M_DEVBUF); 3547 return; 3548} 3549 3550/* 3551** This routine takes removals in the vsi filter 3552** table and creates an Admin Queue call to delete 3553** the filters in the hardware. 3554*/ 3555static void 3556ixl_del_hw_filters(struct ixl_vsi *vsi, int cnt) 3557{ 3558 struct i40e_aqc_remove_macvlan_element_data *d, *e; 3559 struct i40e_hw *hw = vsi->hw; 3560 device_t dev = vsi->dev; 3561 struct ixl_mac_filter *f, *f_temp; 3562 int err, j = 0; 3563 3564 DEBUGOUT("ixl_del_hw_filters: begin\n"); 3565 3566 d = malloc(sizeof(struct i40e_aqc_remove_macvlan_element_data) * cnt, 3567 M_DEVBUF, M_NOWAIT | M_ZERO); 3568 if (d == NULL) { 3569 printf("del hw filter failed to get memory\n"); 3570 return; 3571 } 3572 3573 SLIST_FOREACH_SAFE(f, &vsi->ftl, next, f_temp) { 3574 if (f->flags & IXL_FILTER_DEL) { 3575 e = &d[j]; // a pox on fvl long names :) 3576 bcopy(f->macaddr, e->mac_addr, ETHER_ADDR_LEN); 3577 e->vlan_tag = (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3578 e->flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 3579 /* delete entry from vsi list */ 3580 SLIST_REMOVE(&vsi->ftl, f, ixl_mac_filter, next); 3581 free(f, M_DEVBUF); 3582 j++; 3583 } 3584 if (j == cnt) 3585 break; 3586 } 3587 if (j > 0) { 3588 err = i40e_aq_remove_macvlan(hw, vsi->seid, d, j, NULL); 3589 /* NOTE: returns ENOENT every time but seems to work fine, 3590 so we'll ignore that specific error. */ 3591 // TODO: Does this still occur on current firmwares? 3592 if (err && hw->aq.asq_last_status != I40E_AQ_RC_ENOENT) { 3593 int sc = 0; 3594 for (int i = 0; i < j; i++) 3595 sc += (!d[i].error_code); 3596 vsi->hw_filters_del += sc; 3597 device_printf(dev, 3598 "Failed to remove %d/%d filters, aq error %d\n", 3599 j - sc, j, hw->aq.asq_last_status); 3600 } else 3601 vsi->hw_filters_del += j; 3602 } 3603 free(d, M_DEVBUF); 3604 3605 DEBUGOUT("ixl_del_hw_filters: end\n"); 3606 return; 3607} 3608 3609 3610static void 3611ixl_enable_rings(struct ixl_vsi *vsi) 3612{ 3613 struct i40e_hw *hw = vsi->hw; 3614 u32 reg; 3615 3616 for (int i = 0; i < vsi->num_queues; i++) { 3617 i40e_pre_tx_queue_cfg(hw, i, TRUE); 3618 3619 reg = rd32(hw, I40E_QTX_ENA(i)); 3620 reg |= I40E_QTX_ENA_QENA_REQ_MASK | 3621 I40E_QTX_ENA_QENA_STAT_MASK; 3622 wr32(hw, I40E_QTX_ENA(i), reg); 3623 /* Verify the enable took */ 3624 for (int j = 0; j < 10; j++) { 3625 reg = rd32(hw, I40E_QTX_ENA(i)); 3626 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3627 break; 3628 i40e_msec_delay(10); 3629 } 3630 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) 3631 printf("TX queue %d disabled!\n", i); 3632 3633 reg = rd32(hw, I40E_QRX_ENA(i)); 3634 reg |= I40E_QRX_ENA_QENA_REQ_MASK | 3635 I40E_QRX_ENA_QENA_STAT_MASK; 3636 wr32(hw, I40E_QRX_ENA(i), reg); 3637 /* Verify the enable took */ 3638 for (int j = 0; j < 10; j++) { 3639 reg = rd32(hw, I40E_QRX_ENA(i)); 3640 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3641 break; 3642 i40e_msec_delay(10); 3643 } 3644 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3645 printf("RX queue %d disabled!\n", i); 3646 } 3647} 3648 3649static void 3650ixl_disable_rings(struct ixl_vsi *vsi) 3651{ 3652 struct i40e_hw *hw = vsi->hw; 3653 u32 reg; 3654 3655 for (int i = 0; i < vsi->num_queues; i++) { 3656 i40e_pre_tx_queue_cfg(hw, i, FALSE); 3657 i40e_usec_delay(500); 3658 3659 reg = rd32(hw, I40E_QTX_ENA(i)); 3660 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 3661 wr32(hw, I40E_QTX_ENA(i), reg); 3662 /* Verify the disable took */ 3663 for (int j = 0; j < 10; j++) { 3664 reg = rd32(hw, I40E_QTX_ENA(i)); 3665 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3666 break; 3667 i40e_msec_delay(10); 3668 } 3669 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3670 printf("TX queue %d still enabled!\n", i); 3671 3672 reg = rd32(hw, I40E_QRX_ENA(i)); 3673 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 3674 wr32(hw, I40E_QRX_ENA(i), reg); 3675 /* Verify the disable took */ 3676 for (int j = 0; j < 10; j++) { 3677 reg = rd32(hw, I40E_QRX_ENA(i)); 3678 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3679 break; 3680 i40e_msec_delay(10); 3681 } 3682 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3683 printf("RX queue %d still enabled!\n", i); 3684 } 3685} 3686 3687/** 3688 * ixl_handle_mdd_event 3689 * 3690 * Called from interrupt handler to identify possibly malicious vfs 3691 * (But also detects events from the PF, as well) 3692 **/ 3693static void ixl_handle_mdd_event(struct ixl_pf *pf) 3694{ 3695 struct i40e_hw *hw = &pf->hw; 3696 device_t dev = pf->dev; 3697 bool mdd_detected = false; 3698 bool pf_mdd_detected = false; 3699 u32 reg; 3700 3701 /* find what triggered the MDD event */ 3702 reg = rd32(hw, I40E_GL_MDET_TX); 3703 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 3704 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 3705 I40E_GL_MDET_TX_PF_NUM_SHIFT; 3706 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 3707 I40E_GL_MDET_TX_EVENT_SHIFT; 3708 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 3709 I40E_GL_MDET_TX_QUEUE_SHIFT; 3710 device_printf(dev, 3711 "Malicious Driver Detection event 0x%02x" 3712 " on TX queue %d pf number 0x%02x\n", 3713 event, queue, pf_num); 3714 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 3715 mdd_detected = true; 3716 } 3717 reg = rd32(hw, I40E_GL_MDET_RX); 3718 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 3719 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 3720 I40E_GL_MDET_RX_FUNCTION_SHIFT; 3721 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 3722 I40E_GL_MDET_RX_EVENT_SHIFT; 3723 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 3724 I40E_GL_MDET_RX_QUEUE_SHIFT; 3725 device_printf(dev, 3726 "Malicious Driver Detection event 0x%02x" 3727 " on RX queue %d of function 0x%02x\n", 3728 event, queue, func); 3729 wr32(hw, I40E_GL_MDET_RX, 0xffffffff); 3730 mdd_detected = true; 3731 } 3732 3733 if (mdd_detected) { 3734 reg = rd32(hw, I40E_PF_MDET_TX); 3735 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 3736 wr32(hw, I40E_PF_MDET_TX, 0xFFFF); 3737 device_printf(dev, 3738 "MDD TX event is for this function 0x%08x", 3739 reg); 3740 pf_mdd_detected = true; 3741 } 3742 reg = rd32(hw, I40E_PF_MDET_RX); 3743 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 3744 wr32(hw, I40E_PF_MDET_RX, 0xFFFF); 3745 device_printf(dev, 3746 "MDD RX event is for this function 0x%08x", 3747 reg); 3748 pf_mdd_detected = true; 3749 } 3750 } 3751 3752 /* re-enable mdd interrupt cause */ 3753 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 3754 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 3755 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 3756 ixl_flush(hw); 3757} 3758 3759static void 3760ixl_enable_intr(struct ixl_vsi *vsi) 3761{ 3762 struct i40e_hw *hw = vsi->hw; 3763 struct ixl_queue *que = vsi->queues; 3764 3765 if (ixl_enable_msix) { 3766 ixl_enable_adminq(hw); 3767 for (int i = 0; i < vsi->num_queues; i++, que++) 3768 ixl_enable_queue(hw, que->me); 3769 } else 3770 ixl_enable_legacy(hw); 3771} 3772 3773static void 3774ixl_disable_intr(struct ixl_vsi *vsi) 3775{ 3776 struct i40e_hw *hw = vsi->hw; 3777 struct ixl_queue *que = vsi->queues; 3778 3779 if (ixl_enable_msix) { 3780 ixl_disable_adminq(hw); 3781 for (int i = 0; i < vsi->num_queues; i++, que++) 3782 ixl_disable_queue(hw, que->me); 3783 } else 3784 ixl_disable_legacy(hw); 3785} 3786 3787static void 3788ixl_enable_adminq(struct i40e_hw *hw) 3789{ 3790 u32 reg; 3791 3792 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 3793 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 3794 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 3795 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3796 ixl_flush(hw); 3797 return; 3798} 3799 3800static void 3801ixl_disable_adminq(struct i40e_hw *hw) 3802{ 3803 u32 reg; 3804 3805 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 3806 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3807 3808 return; 3809} 3810 3811static void 3812ixl_enable_queue(struct i40e_hw *hw, int id) 3813{ 3814 u32 reg; 3815 3816 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | 3817 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 3818 (IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 3819 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 3820} 3821 3822static void 3823ixl_disable_queue(struct i40e_hw *hw, int id) 3824{ 3825 u32 reg; 3826 3827 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 3828 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 3829 3830 return; 3831} 3832 3833static void 3834ixl_enable_legacy(struct i40e_hw *hw) 3835{ 3836 u32 reg; 3837 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 3838 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 3839 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 3840 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3841} 3842 3843static void 3844ixl_disable_legacy(struct i40e_hw *hw) 3845{ 3846 u32 reg; 3847 3848 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 3849 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 3850 3851 return; 3852} 3853 3854static void 3855ixl_update_stats_counters(struct ixl_pf *pf) 3856{ 3857 struct i40e_hw *hw = &pf->hw; 3858 struct ixl_vsi *vsi = &pf->vsi; 3859 3860 struct i40e_hw_port_stats *nsd = &pf->stats; 3861 struct i40e_hw_port_stats *osd = &pf->stats_offsets; 3862 3863 /* Update hw stats */ 3864 ixl_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), 3865 pf->stat_offsets_loaded, 3866 &osd->crc_errors, &nsd->crc_errors); 3867 ixl_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), 3868 pf->stat_offsets_loaded, 3869 &osd->illegal_bytes, &nsd->illegal_bytes); 3870 ixl_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), 3871 I40E_GLPRT_GORCL(hw->port), 3872 pf->stat_offsets_loaded, 3873 &osd->eth.rx_bytes, &nsd->eth.rx_bytes); 3874 ixl_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), 3875 I40E_GLPRT_GOTCL(hw->port), 3876 pf->stat_offsets_loaded, 3877 &osd->eth.tx_bytes, &nsd->eth.tx_bytes); 3878 ixl_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), 3879 pf->stat_offsets_loaded, 3880 &osd->eth.rx_discards, 3881 &nsd->eth.rx_discards); 3882 ixl_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), 3883 I40E_GLPRT_UPRCL(hw->port), 3884 pf->stat_offsets_loaded, 3885 &osd->eth.rx_unicast, 3886 &nsd->eth.rx_unicast); 3887 ixl_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), 3888 I40E_GLPRT_UPTCL(hw->port), 3889 pf->stat_offsets_loaded, 3890 &osd->eth.tx_unicast, 3891 &nsd->eth.tx_unicast); 3892 ixl_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), 3893 I40E_GLPRT_MPRCL(hw->port), 3894 pf->stat_offsets_loaded, 3895 &osd->eth.rx_multicast, 3896 &nsd->eth.rx_multicast); 3897 ixl_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), 3898 I40E_GLPRT_MPTCL(hw->port), 3899 pf->stat_offsets_loaded, 3900 &osd->eth.tx_multicast, 3901 &nsd->eth.tx_multicast); 3902 ixl_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), 3903 I40E_GLPRT_BPRCL(hw->port), 3904 pf->stat_offsets_loaded, 3905 &osd->eth.rx_broadcast, 3906 &nsd->eth.rx_broadcast); 3907 ixl_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), 3908 I40E_GLPRT_BPTCL(hw->port), 3909 pf->stat_offsets_loaded, 3910 &osd->eth.tx_broadcast, 3911 &nsd->eth.tx_broadcast); 3912 3913 ixl_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), 3914 pf->stat_offsets_loaded, 3915 &osd->tx_dropped_link_down, 3916 &nsd->tx_dropped_link_down); 3917 ixl_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), 3918 pf->stat_offsets_loaded, 3919 &osd->mac_local_faults, 3920 &nsd->mac_local_faults); 3921 ixl_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), 3922 pf->stat_offsets_loaded, 3923 &osd->mac_remote_faults, 3924 &nsd->mac_remote_faults); 3925 ixl_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), 3926 pf->stat_offsets_loaded, 3927 &osd->rx_length_errors, 3928 &nsd->rx_length_errors); 3929 3930 /* Flow control (LFC) stats */ 3931 ixl_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), 3932 pf->stat_offsets_loaded, 3933 &osd->link_xon_rx, &nsd->link_xon_rx); 3934 ixl_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), 3935 pf->stat_offsets_loaded, 3936 &osd->link_xon_tx, &nsd->link_xon_tx); 3937 ixl_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 3938 pf->stat_offsets_loaded, 3939 &osd->link_xoff_rx, &nsd->link_xoff_rx); 3940 ixl_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 3941 pf->stat_offsets_loaded, 3942 &osd->link_xoff_tx, &nsd->link_xoff_tx); 3943 3944 /* Packet size stats rx */ 3945 ixl_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), 3946 I40E_GLPRT_PRC64L(hw->port), 3947 pf->stat_offsets_loaded, 3948 &osd->rx_size_64, &nsd->rx_size_64); 3949 ixl_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), 3950 I40E_GLPRT_PRC127L(hw->port), 3951 pf->stat_offsets_loaded, 3952 &osd->rx_size_127, &nsd->rx_size_127); 3953 ixl_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), 3954 I40E_GLPRT_PRC255L(hw->port), 3955 pf->stat_offsets_loaded, 3956 &osd->rx_size_255, &nsd->rx_size_255); 3957 ixl_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), 3958 I40E_GLPRT_PRC511L(hw->port), 3959 pf->stat_offsets_loaded, 3960 &osd->rx_size_511, &nsd->rx_size_511); 3961 ixl_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), 3962 I40E_GLPRT_PRC1023L(hw->port), 3963 pf->stat_offsets_loaded, 3964 &osd->rx_size_1023, &nsd->rx_size_1023); 3965 ixl_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), 3966 I40E_GLPRT_PRC1522L(hw->port), 3967 pf->stat_offsets_loaded, 3968 &osd->rx_size_1522, &nsd->rx_size_1522); 3969 ixl_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), 3970 I40E_GLPRT_PRC9522L(hw->port), 3971 pf->stat_offsets_loaded, 3972 &osd->rx_size_big, &nsd->rx_size_big); 3973 3974 /* Packet size stats tx */ 3975 ixl_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), 3976 I40E_GLPRT_PTC64L(hw->port), 3977 pf->stat_offsets_loaded, 3978 &osd->tx_size_64, &nsd->tx_size_64); 3979 ixl_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), 3980 I40E_GLPRT_PTC127L(hw->port), 3981 pf->stat_offsets_loaded, 3982 &osd->tx_size_127, &nsd->tx_size_127); 3983 ixl_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), 3984 I40E_GLPRT_PTC255L(hw->port), 3985 pf->stat_offsets_loaded, 3986 &osd->tx_size_255, &nsd->tx_size_255); 3987 ixl_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), 3988 I40E_GLPRT_PTC511L(hw->port), 3989 pf->stat_offsets_loaded, 3990 &osd->tx_size_511, &nsd->tx_size_511); 3991 ixl_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), 3992 I40E_GLPRT_PTC1023L(hw->port), 3993 pf->stat_offsets_loaded, 3994 &osd->tx_size_1023, &nsd->tx_size_1023); 3995 ixl_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), 3996 I40E_GLPRT_PTC1522L(hw->port), 3997 pf->stat_offsets_loaded, 3998 &osd->tx_size_1522, &nsd->tx_size_1522); 3999 ixl_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), 4000 I40E_GLPRT_PTC9522L(hw->port), 4001 pf->stat_offsets_loaded, 4002 &osd->tx_size_big, &nsd->tx_size_big); 4003 4004 ixl_stat_update32(hw, I40E_GLPRT_RUC(hw->port), 4005 pf->stat_offsets_loaded, 4006 &osd->rx_undersize, &nsd->rx_undersize); 4007 ixl_stat_update32(hw, I40E_GLPRT_RFC(hw->port), 4008 pf->stat_offsets_loaded, 4009 &osd->rx_fragments, &nsd->rx_fragments); 4010 ixl_stat_update32(hw, I40E_GLPRT_ROC(hw->port), 4011 pf->stat_offsets_loaded, 4012 &osd->rx_oversize, &nsd->rx_oversize); 4013 ixl_stat_update32(hw, I40E_GLPRT_RJC(hw->port), 4014 pf->stat_offsets_loaded, 4015 &osd->rx_jabber, &nsd->rx_jabber); 4016 pf->stat_offsets_loaded = true; 4017 /* End hw stats */ 4018 4019 /* Update vsi stats */ 4020 ixl_update_eth_stats(vsi); 4021 4022 /* OS statistics */ 4023 // ERJ - these are per-port, update all vsis? 4024 IXL_SET_IERRORS(vsi, nsd->crc_errors + nsd->illegal_bytes); 4025} 4026 4027/* 4028** Tasklet handler for MSIX Adminq interrupts 4029** - do outside interrupt since it might sleep 4030*/ 4031static void 4032ixl_do_adminq(void *context, int pending) 4033{ 4034 struct ixl_pf *pf = context; 4035 struct i40e_hw *hw = &pf->hw; 4036 struct ixl_vsi *vsi = &pf->vsi; 4037 struct i40e_arq_event_info event; 4038 i40e_status ret; 4039 u32 reg, loop = 0; 4040 u16 opcode, result; 4041 4042 event.buf_len = IXL_AQ_BUF_SZ; 4043 event.msg_buf = malloc(event.buf_len, 4044 M_DEVBUF, M_NOWAIT | M_ZERO); 4045 if (!event.msg_buf) { 4046 printf("Unable to allocate adminq memory\n"); 4047 return; 4048 } 4049 4050 /* clean and process any events */ 4051 do { 4052 ret = i40e_clean_arq_element(hw, &event, &result); 4053 if (ret) 4054 break; 4055 opcode = LE16_TO_CPU(event.desc.opcode); 4056 switch (opcode) { 4057 case i40e_aqc_opc_get_link_status: 4058 vsi->link_up = ixl_config_link(hw); 4059 ixl_update_link_status(pf); 4060 break; 4061 case i40e_aqc_opc_send_msg_to_pf: 4062 /* process pf/vf communication here */ 4063 break; 4064 case i40e_aqc_opc_event_lan_overflow: 4065 break; 4066 default: 4067#ifdef IXL_DEBUG 4068 printf("AdminQ unknown event %x\n", opcode); 4069#endif 4070 break; 4071 } 4072 4073 } while (result && (loop++ < IXL_ADM_LIMIT)); 4074 4075 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4076 reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 4077 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4078 free(event.msg_buf, M_DEVBUF); 4079 4080 if (pf->msix > 1) 4081 ixl_enable_adminq(&pf->hw); 4082 else 4083 ixl_enable_intr(vsi); 4084} 4085 4086static int 4087ixl_debug_info(SYSCTL_HANDLER_ARGS) 4088{ 4089 struct ixl_pf *pf; 4090 int error, input = 0; 4091 4092 error = sysctl_handle_int(oidp, &input, 0, req); 4093 4094 if (error || !req->newptr) 4095 return (error); 4096 4097 if (input == 1) { 4098 pf = (struct ixl_pf *)arg1; 4099 ixl_print_debug_info(pf); 4100 } 4101 4102 return (error); 4103} 4104 4105static void 4106ixl_print_debug_info(struct ixl_pf *pf) 4107{ 4108 struct i40e_hw *hw = &pf->hw; 4109 struct ixl_vsi *vsi = &pf->vsi; 4110 struct ixl_queue *que = vsi->queues; 4111 struct rx_ring *rxr = &que->rxr; 4112 struct tx_ring *txr = &que->txr; 4113 u32 reg; 4114 4115 4116 printf("Queue irqs = %jx\n", (uintmax_t)que->irqs); 4117 printf("AdminQ irqs = %jx\n", (uintmax_t)pf->admin_irq); 4118 printf("RX next check = %x\n", rxr->next_check); 4119 printf("RX not ready = %jx\n", (uintmax_t)rxr->not_done); 4120 printf("RX packets = %jx\n", (uintmax_t)rxr->rx_packets); 4121 printf("TX desc avail = %x\n", txr->avail); 4122 4123 reg = rd32(hw, I40E_GLV_GORCL(0xc)); 4124 printf("RX Bytes = %x\n", reg); 4125 reg = rd32(hw, I40E_GLPRT_GORCL(hw->port)); 4126 printf("Port RX Bytes = %x\n", reg); 4127 reg = rd32(hw, I40E_GLV_RDPC(0xc)); 4128 printf("RX discard = %x\n", reg); 4129 reg = rd32(hw, I40E_GLPRT_RDPC(hw->port)); 4130 printf("Port RX discard = %x\n", reg); 4131 4132 reg = rd32(hw, I40E_GLV_TEPC(0xc)); 4133 printf("TX errors = %x\n", reg); 4134 reg = rd32(hw, I40E_GLV_GOTCL(0xc)); 4135 printf("TX Bytes = %x\n", reg); 4136 4137 reg = rd32(hw, I40E_GLPRT_RUC(hw->port)); 4138 printf("RX undersize = %x\n", reg); 4139 reg = rd32(hw, I40E_GLPRT_RFC(hw->port)); 4140 printf("RX fragments = %x\n", reg); 4141 reg = rd32(hw, I40E_GLPRT_ROC(hw->port)); 4142 printf("RX oversize = %x\n", reg); 4143 reg = rd32(hw, I40E_GLPRT_RLEC(hw->port)); 4144 printf("RX length error = %x\n", reg); 4145 reg = rd32(hw, I40E_GLPRT_MRFC(hw->port)); 4146 printf("mac remote fault = %x\n", reg); 4147 reg = rd32(hw, I40E_GLPRT_MLFC(hw->port)); 4148 printf("mac local fault = %x\n", reg); 4149} 4150 4151/** 4152 * Update VSI-specific ethernet statistics counters. 4153 **/ 4154void ixl_update_eth_stats(struct ixl_vsi *vsi) 4155{ 4156 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 4157 struct i40e_hw *hw = &pf->hw; 4158 struct i40e_eth_stats *es; 4159 struct i40e_eth_stats *oes; 4160 int i; 4161 uint64_t tx_discards; 4162 struct i40e_hw_port_stats *nsd; 4163 u16 stat_idx = vsi->info.stat_counter_idx; 4164 4165 es = &vsi->eth_stats; 4166 oes = &vsi->eth_stats_offsets; 4167 nsd = &pf->stats; 4168 4169 /* Gather up the stats that the hw collects */ 4170 ixl_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 4171 vsi->stat_offsets_loaded, 4172 &oes->tx_errors, &es->tx_errors); 4173 ixl_stat_update32(hw, I40E_GLV_RDPC(stat_idx), 4174 vsi->stat_offsets_loaded, 4175 &oes->rx_discards, &es->rx_discards); 4176 4177 ixl_stat_update48(hw, I40E_GLV_GORCH(stat_idx), 4178 I40E_GLV_GORCL(stat_idx), 4179 vsi->stat_offsets_loaded, 4180 &oes->rx_bytes, &es->rx_bytes); 4181 ixl_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), 4182 I40E_GLV_UPRCL(stat_idx), 4183 vsi->stat_offsets_loaded, 4184 &oes->rx_unicast, &es->rx_unicast); 4185 ixl_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), 4186 I40E_GLV_MPRCL(stat_idx), 4187 vsi->stat_offsets_loaded, 4188 &oes->rx_multicast, &es->rx_multicast); 4189 ixl_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), 4190 I40E_GLV_BPRCL(stat_idx), 4191 vsi->stat_offsets_loaded, 4192 &oes->rx_broadcast, &es->rx_broadcast); 4193 4194 ixl_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), 4195 I40E_GLV_GOTCL(stat_idx), 4196 vsi->stat_offsets_loaded, 4197 &oes->tx_bytes, &es->tx_bytes); 4198 ixl_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), 4199 I40E_GLV_UPTCL(stat_idx), 4200 vsi->stat_offsets_loaded, 4201 &oes->tx_unicast, &es->tx_unicast); 4202 ixl_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), 4203 I40E_GLV_MPTCL(stat_idx), 4204 vsi->stat_offsets_loaded, 4205 &oes->tx_multicast, &es->tx_multicast); 4206 ixl_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), 4207 I40E_GLV_BPTCL(stat_idx), 4208 vsi->stat_offsets_loaded, 4209 &oes->tx_broadcast, &es->tx_broadcast); 4210 vsi->stat_offsets_loaded = true; 4211 4212 tx_discards = es->tx_discards + nsd->tx_dropped_link_down; 4213 for (i = 0; i < vsi->num_queues; i++) 4214 tx_discards += vsi->queues[i].txr.br->br_drops; 4215 4216 /* Update ifnet stats */ 4217 IXL_SET_IPACKETS(vsi, es->rx_unicast + 4218 es->rx_multicast + 4219 es->rx_broadcast); 4220 IXL_SET_OPACKETS(vsi, es->tx_unicast + 4221 es->tx_multicast + 4222 es->tx_broadcast); 4223 IXL_SET_IBYTES(vsi, es->rx_bytes); 4224 IXL_SET_OBYTES(vsi, es->tx_bytes); 4225 IXL_SET_IMCASTS(vsi, es->rx_multicast); 4226 IXL_SET_OMCASTS(vsi, es->tx_multicast); 4227 4228 IXL_SET_OERRORS(vsi, es->tx_errors); 4229 IXL_SET_IQDROPS(vsi, es->rx_discards + nsd->eth.rx_discards); 4230 IXL_SET_OQDROPS(vsi, tx_discards); 4231 IXL_SET_NOPROTO(vsi, es->rx_unknown_protocol); 4232 IXL_SET_COLLISIONS(vsi, 0); 4233} 4234 4235/** 4236 * Reset all of the stats for the given pf 4237 **/ 4238void ixl_pf_reset_stats(struct ixl_pf *pf) 4239{ 4240 bzero(&pf->stats, sizeof(struct i40e_hw_port_stats)); 4241 bzero(&pf->stats_offsets, sizeof(struct i40e_hw_port_stats)); 4242 pf->stat_offsets_loaded = false; 4243} 4244 4245/** 4246 * Resets all stats of the given vsi 4247 **/ 4248void ixl_vsi_reset_stats(struct ixl_vsi *vsi) 4249{ 4250 bzero(&vsi->eth_stats, sizeof(struct i40e_eth_stats)); 4251 bzero(&vsi->eth_stats_offsets, sizeof(struct i40e_eth_stats)); 4252 vsi->stat_offsets_loaded = false; 4253} 4254 4255/** 4256 * Read and update a 48 bit stat from the hw 4257 * 4258 * Since the device stats are not reset at PFReset, they likely will not 4259 * be zeroed when the driver starts. We'll save the first values read 4260 * and use them as offsets to be subtracted from the raw values in order 4261 * to report stats that count from zero. 4262 **/ 4263static void 4264ixl_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, 4265 bool offset_loaded, u64 *offset, u64 *stat) 4266{ 4267 u64 new_data; 4268 4269#if defined(__FreeBSD__) && (__FreeBSD_version >= 1000000) && defined(__amd64__) 4270 new_data = rd64(hw, loreg); 4271#else 4272 /* 4273 * Use two rd32's instead of one rd64; FreeBSD versions before 4274 * 10 don't support 8 byte bus reads/writes. 4275 */ 4276 new_data = rd32(hw, loreg); 4277 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 4278#endif 4279 4280 if (!offset_loaded) 4281 *offset = new_data; 4282 if (new_data >= *offset) 4283 *stat = new_data - *offset; 4284 else 4285 *stat = (new_data + ((u64)1 << 48)) - *offset; 4286 *stat &= 0xFFFFFFFFFFFFULL; 4287} 4288 4289/** 4290 * Read and update a 32 bit stat from the hw 4291 **/ 4292static void 4293ixl_stat_update32(struct i40e_hw *hw, u32 reg, 4294 bool offset_loaded, u64 *offset, u64 *stat) 4295{ 4296 u32 new_data; 4297 4298 new_data = rd32(hw, reg); 4299 if (!offset_loaded) 4300 *offset = new_data; 4301 if (new_data >= *offset) 4302 *stat = (u32)(new_data - *offset); 4303 else 4304 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset); 4305} 4306 4307/* 4308** Set flow control using sysctl: 4309** 0 - off 4310** 1 - rx pause 4311** 2 - tx pause 4312** 3 - full 4313*/ 4314static int 4315ixl_set_flowcntl(SYSCTL_HANDLER_ARGS) 4316{ 4317 /* 4318 * TODO: ensure flow control is disabled if 4319 * priority flow control is enabled 4320 * 4321 * TODO: ensure tx CRC by hardware should be enabled 4322 * if tx flow control is enabled. 4323 */ 4324 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4325 struct i40e_hw *hw = &pf->hw; 4326 device_t dev = pf->dev; 4327 int error = 0; 4328 enum i40e_status_code aq_error = 0; 4329 u8 fc_aq_err = 0; 4330 4331 /* Get request */ 4332 error = sysctl_handle_int(oidp, &pf->fc, 0, req); 4333 if ((error) || (req->newptr == NULL)) 4334 return (error); 4335 if (pf->fc < 0 || pf->fc > 3) { 4336 device_printf(dev, 4337 "Invalid fc mode; valid modes are 0 through 3\n"); 4338 return (EINVAL); 4339 } 4340 4341 /* 4342 ** Changing flow control mode currently does not work on 4343 ** 40GBASE-CR4 PHYs 4344 */ 4345 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4 4346 || hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4_CU) { 4347 device_printf(dev, "Changing flow control mode unsupported" 4348 " on 40GBase-CR4 media.\n"); 4349 return (ENODEV); 4350 } 4351 4352 /* Set fc ability for port */ 4353 hw->fc.requested_mode = pf->fc; 4354 aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE); 4355 if (aq_error) { 4356 device_printf(dev, 4357 "%s: Error setting new fc mode %d; fc_err %#x\n", 4358 __func__, aq_error, fc_aq_err); 4359 return (EAGAIN); 4360 } 4361 4362 return (0); 4363} 4364 4365static int 4366ixl_current_speed(SYSCTL_HANDLER_ARGS) 4367{ 4368 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4369 struct i40e_hw *hw = &pf->hw; 4370 int error = 0, index = 0; 4371 4372 char *speeds[] = { 4373 "Unknown", 4374 "100M", 4375 "1G", 4376 "10G", 4377 "40G", 4378 "20G" 4379 }; 4380 4381 ixl_update_link_status(pf); 4382 4383 switch (hw->phy.link_info.link_speed) { 4384 case I40E_LINK_SPEED_100MB: 4385 index = 1; 4386 break; 4387 case I40E_LINK_SPEED_1GB: 4388 index = 2; 4389 break; 4390 case I40E_LINK_SPEED_10GB: 4391 index = 3; 4392 break; 4393 case I40E_LINK_SPEED_40GB: 4394 index = 4; 4395 break; 4396 case I40E_LINK_SPEED_20GB: 4397 index = 5; 4398 break; 4399 case I40E_LINK_SPEED_UNKNOWN: 4400 default: 4401 index = 0; 4402 break; 4403 } 4404 4405 error = sysctl_handle_string(oidp, speeds[index], 4406 strlen(speeds[index]), req); 4407 return (error); 4408} 4409 4410static int 4411ixl_set_advertised_speeds(struct ixl_pf *pf, int speeds) 4412{ 4413 struct i40e_hw *hw = &pf->hw; 4414 device_t dev = pf->dev; 4415 struct i40e_aq_get_phy_abilities_resp abilities; 4416 struct i40e_aq_set_phy_config config; 4417 enum i40e_status_code aq_error = 0; 4418 4419 /* Get current capability information */ 4420 aq_error = i40e_aq_get_phy_capabilities(hw, 4421 FALSE, FALSE, &abilities, NULL); 4422 if (aq_error) { 4423 device_printf(dev, 4424 "%s: Error getting phy capabilities %d," 4425 " aq error: %d\n", __func__, aq_error, 4426 hw->aq.asq_last_status); 4427 return (EAGAIN); 4428 } 4429 4430 /* Prepare new config */ 4431 bzero(&config, sizeof(config)); 4432 config.phy_type = abilities.phy_type; 4433 config.abilities = abilities.abilities 4434 | I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 4435 config.eee_capability = abilities.eee_capability; 4436 config.eeer = abilities.eeer_val; 4437 config.low_power_ctrl = abilities.d3_lpan; 4438 /* Translate into aq cmd link_speed */ 4439 if (speeds & 0x4) 4440 config.link_speed |= I40E_LINK_SPEED_10GB; 4441 if (speeds & 0x2) 4442 config.link_speed |= I40E_LINK_SPEED_1GB; 4443 if (speeds & 0x1) 4444 config.link_speed |= I40E_LINK_SPEED_100MB; 4445 4446 /* Do aq command & restart link */ 4447 aq_error = i40e_aq_set_phy_config(hw, &config, NULL); 4448 if (aq_error) { 4449 device_printf(dev, 4450 "%s: Error setting new phy config %d," 4451 " aq error: %d\n", __func__, aq_error, 4452 hw->aq.asq_last_status); 4453 return (EAGAIN); 4454 } 4455 4456 /* 4457 ** This seems a bit heavy handed, but we 4458 ** need to get a reinit on some devices 4459 */ 4460 IXL_PF_LOCK(pf); 4461 ixl_stop(pf); 4462 ixl_init_locked(pf); 4463 IXL_PF_UNLOCK(pf); 4464 4465 return (0); 4466} 4467 4468/* 4469** Control link advertise speed: 4470** Flags: 4471** 0x1 - advertise 100 Mb 4472** 0x2 - advertise 1G 4473** 0x4 - advertise 10G 4474** 4475** Does not work on 40G devices. 4476*/ 4477static int 4478ixl_set_advertise(SYSCTL_HANDLER_ARGS) 4479{ 4480 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4481 struct i40e_hw *hw = &pf->hw; 4482 device_t dev = pf->dev; 4483 int requested_ls = 0; 4484 int error = 0; 4485 4486 /* 4487 ** FW doesn't support changing advertised speed 4488 ** for 40G devices; speed is always 40G. 4489 */ 4490 if (i40e_is_40G_device(hw->device_id)) 4491 return (ENODEV); 4492 4493 /* Read in new mode */ 4494 requested_ls = pf->advertised_speed; 4495 error = sysctl_handle_int(oidp, &requested_ls, 0, req); 4496 if ((error) || (req->newptr == NULL)) 4497 return (error); 4498 if (requested_ls < 1 || requested_ls > 7) { 4499 device_printf(dev, 4500 "Invalid advertised speed; valid modes are 0x1 through 0x7\n"); 4501 return (EINVAL); 4502 } 4503 4504 /* Exit if no change */ 4505 if (pf->advertised_speed == requested_ls) 4506 return (0); 4507 4508 error = ixl_set_advertised_speeds(pf, requested_ls); 4509 if (error) 4510 return (error); 4511 4512 pf->advertised_speed = requested_ls; 4513 ixl_update_link_status(pf); 4514 return (0); 4515} 4516 4517/* 4518** Get the width and transaction speed of 4519** the bus this adapter is plugged into. 4520*/ 4521static u16 4522ixl_get_bus_info(struct i40e_hw *hw, device_t dev) 4523{ 4524 u16 link; 4525 u32 offset; 4526 4527 4528 /* Get the PCI Express Capabilities offset */ 4529 pci_find_cap(dev, PCIY_EXPRESS, &offset); 4530 4531 /* ...and read the Link Status Register */ 4532 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 4533 4534 switch (link & I40E_PCI_LINK_WIDTH) { 4535 case I40E_PCI_LINK_WIDTH_1: 4536 hw->bus.width = i40e_bus_width_pcie_x1; 4537 break; 4538 case I40E_PCI_LINK_WIDTH_2: 4539 hw->bus.width = i40e_bus_width_pcie_x2; 4540 break; 4541 case I40E_PCI_LINK_WIDTH_4: 4542 hw->bus.width = i40e_bus_width_pcie_x4; 4543 break; 4544 case I40E_PCI_LINK_WIDTH_8: 4545 hw->bus.width = i40e_bus_width_pcie_x8; 4546 break; 4547 default: 4548 hw->bus.width = i40e_bus_width_unknown; 4549 break; 4550 } 4551 4552 switch (link & I40E_PCI_LINK_SPEED) { 4553 case I40E_PCI_LINK_SPEED_2500: 4554 hw->bus.speed = i40e_bus_speed_2500; 4555 break; 4556 case I40E_PCI_LINK_SPEED_5000: 4557 hw->bus.speed = i40e_bus_speed_5000; 4558 break; 4559 case I40E_PCI_LINK_SPEED_8000: 4560 hw->bus.speed = i40e_bus_speed_8000; 4561 break; 4562 default: 4563 hw->bus.speed = i40e_bus_speed_unknown; 4564 break; 4565 } 4566 4567 4568 device_printf(dev,"PCI Express Bus: Speed %s %s\n", 4569 ((hw->bus.speed == i40e_bus_speed_8000) ? "8.0GT/s": 4570 (hw->bus.speed == i40e_bus_speed_5000) ? "5.0GT/s": 4571 (hw->bus.speed == i40e_bus_speed_2500) ? "2.5GT/s":"Unknown"), 4572 (hw->bus.width == i40e_bus_width_pcie_x8) ? "Width x8" : 4573 (hw->bus.width == i40e_bus_width_pcie_x4) ? "Width x4" : 4574 (hw->bus.width == i40e_bus_width_pcie_x1) ? "Width x1" : 4575 ("Unknown")); 4576 4577 if ((hw->bus.width <= i40e_bus_width_pcie_x8) && 4578 (hw->bus.speed < i40e_bus_speed_8000)) { 4579 device_printf(dev, "PCI-Express bandwidth available" 4580 " for this device\n is not sufficient for" 4581 " normal operation.\n"); 4582 device_printf(dev, "For expected performance a x8 " 4583 "PCIE Gen3 slot is required.\n"); 4584 } 4585 4586 return (link); 4587} 4588 4589static int 4590ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS) 4591{ 4592 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4593 struct i40e_hw *hw = &pf->hw; 4594 char buf[32]; 4595 4596 snprintf(buf, sizeof(buf), 4597 "f%d.%d a%d.%d n%02x.%02x e%08x", 4598 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 4599 hw->aq.api_maj_ver, hw->aq.api_min_ver, 4600 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> 4601 IXL_NVM_VERSION_HI_SHIFT, 4602 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> 4603 IXL_NVM_VERSION_LO_SHIFT, 4604 hw->nvm.eetrack); 4605 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4606} 4607 4608 4609#ifdef IXL_DEBUG_SYSCTL 4610static int 4611ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS) 4612{ 4613 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4614 struct i40e_hw *hw = &pf->hw; 4615 struct i40e_link_status link_status; 4616 char buf[512]; 4617 4618 enum i40e_status_code aq_error = 0; 4619 4620 aq_error = i40e_aq_get_link_info(hw, TRUE, &link_status, NULL); 4621 if (aq_error) { 4622 printf("i40e_aq_get_link_info() error %d\n", aq_error); 4623 return (EPERM); 4624 } 4625 4626 sprintf(buf, "\n" 4627 "PHY Type : %#04x\n" 4628 "Speed : %#04x\n" 4629 "Link info: %#04x\n" 4630 "AN info : %#04x\n" 4631 "Ext info : %#04x", 4632 link_status.phy_type, link_status.link_speed, 4633 link_status.link_info, link_status.an_info, 4634 link_status.ext_info); 4635 4636 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4637} 4638 4639static int 4640ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS) 4641{ 4642 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4643 struct i40e_hw *hw = &pf->hw; 4644 struct i40e_aq_get_phy_abilities_resp abilities_resp; 4645 char buf[512]; 4646 4647 enum i40e_status_code aq_error = 0; 4648 4649 // TODO: Print out list of qualified modules as well? 4650 aq_error = i40e_aq_get_phy_capabilities(hw, TRUE, FALSE, &abilities_resp, NULL); 4651 if (aq_error) { 4652 printf("i40e_aq_get_phy_capabilities() error %d\n", aq_error); 4653 return (EPERM); 4654 } 4655 4656 sprintf(buf, "\n" 4657 "PHY Type : %#010x\n" 4658 "Speed : %#04x\n" 4659 "Abilities: %#04x\n" 4660 "EEE cap : %#06x\n" 4661 "EEER reg : %#010x\n" 4662 "D3 Lpan : %#04x", 4663 abilities_resp.phy_type, abilities_resp.link_speed, 4664 abilities_resp.abilities, abilities_resp.eee_capability, 4665 abilities_resp.eeer_val, abilities_resp.d3_lpan); 4666 4667 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4668} 4669 4670static int 4671ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS) 4672{ 4673 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4674 struct ixl_vsi *vsi = &pf->vsi; 4675 struct ixl_mac_filter *f; 4676 char *buf, *buf_i; 4677 4678 int error = 0; 4679 int ftl_len = 0; 4680 int ftl_counter = 0; 4681 int buf_len = 0; 4682 int entry_len = 42; 4683 4684 SLIST_FOREACH(f, &vsi->ftl, next) { 4685 ftl_len++; 4686 } 4687 4688 if (ftl_len < 1) { 4689 sysctl_handle_string(oidp, "(none)", 6, req); 4690 return (0); 4691 } 4692 4693 buf_len = sizeof(char) * (entry_len + 1) * ftl_len + 2; 4694 buf = buf_i = malloc(buf_len, M_DEVBUF, M_NOWAIT); 4695 4696 sprintf(buf_i++, "\n"); 4697 SLIST_FOREACH(f, &vsi->ftl, next) { 4698 sprintf(buf_i, 4699 MAC_FORMAT ", vlan %4d, flags %#06x", 4700 MAC_FORMAT_ARGS(f->macaddr), f->vlan, f->flags); 4701 buf_i += entry_len; 4702 /* don't print '\n' for last entry */ 4703 if (++ftl_counter != ftl_len) { 4704 sprintf(buf_i, "\n"); 4705 buf_i++; 4706 } 4707 } 4708 4709 error = sysctl_handle_string(oidp, buf, strlen(buf), req); 4710 if (error) 4711 printf("sysctl error: %d\n", error); 4712 free(buf, M_DEVBUF); 4713 return error; 4714} 4715 4716#define IXL_SW_RES_SIZE 0x14 4717static int 4718ixl_res_alloc_cmp(const void *a, const void *b) 4719{ 4720 const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two; 4721 one = (struct i40e_aqc_switch_resource_alloc_element_resp *)a; 4722 two = (struct i40e_aqc_switch_resource_alloc_element_resp *)b; 4723 4724 return ((int)one->resource_type - (int)two->resource_type); 4725} 4726 4727static int 4728ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS) 4729{ 4730 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4731 struct i40e_hw *hw = &pf->hw; 4732 device_t dev = pf->dev; 4733 struct sbuf *buf; 4734 int error = 0; 4735 4736 u8 num_entries; 4737 struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE]; 4738 4739 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 4740 if (!buf) { 4741 device_printf(dev, "Could not allocate sbuf for output.\n"); 4742 return (ENOMEM); 4743 } 4744 4745 bzero(resp, sizeof(resp)); 4746 error = i40e_aq_get_switch_resource_alloc(hw, &num_entries, 4747 resp, 4748 IXL_SW_RES_SIZE, 4749 NULL); 4750 if (error) { 4751 device_printf(dev, "%s: get_switch_resource_alloc() error %d, aq error %d\n", 4752 __func__, error, hw->aq.asq_last_status); 4753 sbuf_delete(buf); 4754 return error; 4755 } 4756 4757 /* Sort entries by type for display */ 4758 qsort(resp, num_entries, 4759 sizeof(struct i40e_aqc_switch_resource_alloc_element_resp), 4760 &ixl_res_alloc_cmp); 4761 4762 sbuf_cat(buf, "\n"); 4763 sbuf_printf(buf, "# of entries: %d\n", num_entries); 4764 sbuf_printf(buf, 4765 "Type | Guaranteed | Total | Used | Un-allocated\n" 4766 " | (this) | (all) | (this) | (all) \n"); 4767 for (int i = 0; i < num_entries; i++) { 4768 sbuf_printf(buf, 4769 "%#4x | %10d %5d %6d %12d", 4770 resp[i].resource_type, 4771 resp[i].guaranteed, 4772 resp[i].total, 4773 resp[i].used, 4774 resp[i].total_unalloced); 4775 if (i < num_entries - 1) 4776 sbuf_cat(buf, "\n"); 4777 } 4778 4779 error = sbuf_finish(buf); 4780 if (error) { 4781 device_printf(dev, "Error finishing sbuf: %d\n", error); 4782 sbuf_delete(buf); 4783 return error; 4784 } 4785 4786 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 4787 if (error) 4788 device_printf(dev, "sysctl error: %d\n", error); 4789 sbuf_delete(buf); 4790 return error; 4791} 4792 4793/* 4794** Caller must init and delete sbuf; this function will clear and 4795** finish it for caller. 4796*/ 4797static char * 4798ixl_switch_element_string(struct sbuf *s, u16 seid, bool uplink) 4799{ 4800 sbuf_clear(s); 4801 4802 if (seid == 0 && uplink) 4803 sbuf_cat(s, "Network"); 4804 else if (seid == 0) 4805 sbuf_cat(s, "Host"); 4806 else if (seid == 1) 4807 sbuf_cat(s, "EMP"); 4808 else if (seid <= 5) 4809 sbuf_printf(s, "MAC %d", seid - 2); 4810 else if (seid <= 15) 4811 sbuf_cat(s, "Reserved"); 4812 else if (seid <= 31) 4813 sbuf_printf(s, "PF %d", seid - 16); 4814 else if (seid <= 159) 4815 sbuf_printf(s, "VF %d", seid - 32); 4816 else if (seid <= 287) 4817 sbuf_cat(s, "Reserved"); 4818 else if (seid <= 511) 4819 sbuf_cat(s, "Other"); // for other structures 4820 else if (seid <= 895) 4821 sbuf_printf(s, "VSI %d", seid - 512); 4822 else if (seid <= 1023) 4823 sbuf_printf(s, "Reserved"); 4824 else 4825 sbuf_cat(s, "Invalid"); 4826 4827 sbuf_finish(s); 4828 return sbuf_data(s); 4829} 4830 4831static int 4832ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS) 4833{ 4834 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4835 struct i40e_hw *hw = &pf->hw; 4836 device_t dev = pf->dev; 4837 struct sbuf *buf; 4838 struct sbuf *nmbuf; 4839 int error = 0; 4840 u8 aq_buf[I40E_AQ_LARGE_BUF]; 4841 4842 u16 next = 0; 4843 struct i40e_aqc_get_switch_config_resp *sw_config; 4844 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 4845 4846 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 4847 if (!buf) { 4848 device_printf(dev, "Could not allocate sbuf for sysctl output.\n"); 4849 return (ENOMEM); 4850 } 4851 4852 error = i40e_aq_get_switch_config(hw, sw_config, 4853 sizeof(aq_buf), &next, NULL); 4854 if (error) { 4855 device_printf(dev, "%s: aq_get_switch_config() error %d, aq error %d\n", 4856 __func__, error, hw->aq.asq_last_status); 4857 sbuf_delete(buf); 4858 return error; 4859 } 4860 4861 nmbuf = sbuf_new_auto(); 4862 if (!nmbuf) { 4863 device_printf(dev, "Could not allocate sbuf for name output.\n"); 4864 return (ENOMEM); 4865 } 4866 4867 sbuf_cat(buf, "\n"); 4868 // Assuming <= 255 elements in switch 4869 sbuf_printf(buf, "# of elements: %d\n", sw_config->header.num_reported); 4870 /* Exclude: 4871 ** Revision -- all elements are revision 1 for now 4872 */ 4873 sbuf_printf(buf, 4874 "SEID ( Name ) | Uplink | Downlink | Conn Type\n" 4875 " | | | (uplink)\n"); 4876 for (int i = 0; i < sw_config->header.num_reported; i++) { 4877 // "%4d (%8s) | %8s %8s %#8x", 4878 sbuf_printf(buf, "%4d", sw_config->element[i].seid); 4879 sbuf_cat(buf, " "); 4880 sbuf_printf(buf, "(%8s)", ixl_switch_element_string(nmbuf, sw_config->element[i].seid, false)); 4881 sbuf_cat(buf, " | "); 4882 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, sw_config->element[i].uplink_seid, true)); 4883 sbuf_cat(buf, " "); 4884 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, sw_config->element[i].downlink_seid, false)); 4885 sbuf_cat(buf, " "); 4886 sbuf_printf(buf, "%#8x", sw_config->element[i].connection_type); 4887 if (i < sw_config->header.num_reported - 1) 4888 sbuf_cat(buf, "\n"); 4889 } 4890 sbuf_delete(nmbuf); 4891 4892 error = sbuf_finish(buf); 4893 if (error) { 4894 device_printf(dev, "Error finishing sbuf: %d\n", error); 4895 sbuf_delete(buf); 4896 return error; 4897 } 4898 4899 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 4900 if (error) 4901 device_printf(dev, "sysctl error: %d\n", error); 4902 sbuf_delete(buf); 4903 4904 return (error); 4905} 4906 4907/* 4908** Dump TX desc given index. 4909** Doesn't work; don't use. 4910** TODO: Also needs a queue index input! 4911**/ 4912static int 4913ixl_sysctl_dump_txd(SYSCTL_HANDLER_ARGS) 4914{ 4915 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4916 device_t dev = pf->dev; 4917 struct sbuf *buf; 4918 int error = 0; 4919 4920 u16 desc_idx = 0; 4921 4922 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 4923 if (!buf) { 4924 device_printf(dev, "Could not allocate sbuf for output.\n"); 4925 return (ENOMEM); 4926 } 4927 4928 /* Read in index */ 4929 error = sysctl_handle_int(oidp, &desc_idx, 0, req); 4930 if (error) 4931 return (error); 4932 if (req->newptr == NULL) 4933 return (EIO); // fix 4934 if (desc_idx > 1024) { // fix 4935 device_printf(dev, 4936 "Invalid descriptor index, needs to be < 1024\n"); // fix 4937 return (EINVAL); 4938 } 4939 4940 // Don't use this sysctl yet 4941 if (TRUE) 4942 return (ENODEV); 4943 4944 sbuf_cat(buf, "\n"); 4945 4946 // set to queue 1? 4947 struct ixl_queue *que = pf->vsi.queues; 4948 struct tx_ring *txr = &(que[1].txr); 4949 struct i40e_tx_desc *txd = &txr->base[desc_idx]; 4950 4951 sbuf_printf(buf, "Que: %d, Desc: %d\n", que->me, desc_idx); 4952 sbuf_printf(buf, "Addr: %#18lx\n", txd->buffer_addr); 4953 sbuf_printf(buf, "Opts: %#18lx\n", txd->cmd_type_offset_bsz); 4954 4955 error = sbuf_finish(buf); 4956 if (error) { 4957 device_printf(dev, "Error finishing sbuf: %d\n", error); 4958 sbuf_delete(buf); 4959 return error; 4960 } 4961 4962 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 4963 if (error) 4964 device_printf(dev, "sysctl error: %d\n", error); 4965 sbuf_delete(buf); 4966 return error; 4967} 4968#endif /* IXL_DEBUG_SYSCTL */ 4969 4970