1282289Serj/****************************************************************************** 2282289Serj 3282289Serj Copyright (c) 2001-2015, Intel Corporation 4282289Serj All rights reserved. 5282289Serj 6282289Serj Redistribution and use in source and binary forms, with or without 7282289Serj modification, are permitted provided that the following conditions are met: 8282289Serj 9282289Serj 1. Redistributions of source code must retain the above copyright notice, 10282289Serj this list of conditions and the following disclaimer. 11282289Serj 12282289Serj 2. Redistributions in binary form must reproduce the above copyright 13282289Serj notice, this list of conditions and the following disclaimer in the 14282289Serj documentation and/or other materials provided with the distribution. 15282289Serj 16282289Serj 3. Neither the name of the Intel Corporation nor the names of its 17282289Serj contributors may be used to endorse or promote products derived from 18282289Serj this software without specific prior written permission. 19282289Serj 20282289Serj THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21282289Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22282289Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23282289Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24282289Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25282289Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26282289Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27282289Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28282289Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29282289Serj ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30282289Serj POSSIBILITY OF SUCH DAMAGE. 31282289Serj 32282289Serj******************************************************************************/ 33282289Serj/*$FreeBSD: releng/11.0/sys/dev/ixgbe/ixgbe_x550.c 295093 2016-01-31 15:14:23Z smh $*/ 34282289Serj 35282289Serj#include "ixgbe_x550.h" 36282289Serj#include "ixgbe_x540.h" 37282289Serj#include "ixgbe_type.h" 38282289Serj#include "ixgbe_api.h" 39282289Serj#include "ixgbe_common.h" 40282289Serj#include "ixgbe_phy.h" 41282289Serj 42282289Serjstatic s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 43282289Serj 44282289Serj/** 45282289Serj * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 46282289Serj * @hw: pointer to hardware structure 47282289Serj * 48282289Serj * Initialize the function pointers and assign the MAC type for X550. 49282289Serj * Does not touch the hardware. 50282289Serj **/ 51282289Serjs32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 52282289Serj{ 53282289Serj struct ixgbe_mac_info *mac = &hw->mac; 54282289Serj struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 55282289Serj s32 ret_val; 56282289Serj 57282289Serj DEBUGFUNC("ixgbe_init_ops_X550"); 58282289Serj 59282289Serj ret_val = ixgbe_init_ops_X540(hw); 60282289Serj mac->ops.dmac_config = ixgbe_dmac_config_X550; 61282289Serj mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 62282289Serj mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 63282289Serj mac->ops.setup_eee = ixgbe_setup_eee_X550; 64282289Serj mac->ops.set_source_address_pruning = 65282289Serj ixgbe_set_source_address_pruning_X550; 66282289Serj mac->ops.set_ethertype_anti_spoofing = 67282289Serj ixgbe_set_ethertype_anti_spoofing_X550; 68282289Serj 69282289Serj mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 70282289Serj eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 71282289Serj eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 72282289Serj eeprom->ops.read = ixgbe_read_ee_hostif_X550; 73282289Serj eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 74282289Serj eeprom->ops.write = ixgbe_write_ee_hostif_X550; 75282289Serj eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 76282289Serj eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 77282289Serj eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 78282289Serj 79282289Serj mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 80282289Serj mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 81282289Serj mac->ops.mdd_event = ixgbe_mdd_event_X550; 82282289Serj mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 83282289Serj mac->ops.disable_rx = ixgbe_disable_rx_x550; 84282289Serj if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 85282289Serj hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 86282289Serj hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 87282289Serj } 88282289Serj return ret_val; 89282289Serj} 90282289Serj 91282289Serj/** 92282289Serj * ixgbe_read_cs4227 - Read CS4227 register 93282289Serj * @hw: pointer to hardware structure 94282289Serj * @reg: register number to write 95282289Serj * @value: pointer to receive value read 96282289Serj * 97282289Serj * Returns status code 98282289Serj **/ 99282289Serjstatic s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 100282289Serj{ 101282289Serj return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 102282289Serj} 103282289Serj 104282289Serj/** 105282289Serj * ixgbe_write_cs4227 - Write CS4227 register 106282289Serj * @hw: pointer to hardware structure 107282289Serj * @reg: register number to write 108282289Serj * @value: value to write to register 109282289Serj * 110282289Serj * Returns status code 111282289Serj **/ 112282289Serjstatic s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 113282289Serj{ 114282289Serj return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 115282289Serj} 116282289Serj 117282289Serj/** 118282289Serj * ixgbe_read_pe - Read register from port expander 119282289Serj * @hw: pointer to hardware structure 120282289Serj * @reg: register number to read 121282289Serj * @value: pointer to receive read value 122282289Serj * 123282289Serj * Returns status code 124282289Serj **/ 125282289Serjstatic s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 126282289Serj{ 127282289Serj s32 status; 128282289Serj 129282289Serj status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 130282289Serj if (status != IXGBE_SUCCESS) 131282289Serj ERROR_REPORT2(IXGBE_ERROR_CAUTION, 132282289Serj "port expander access failed with %d\n", status); 133282289Serj return status; 134282289Serj} 135282289Serj 136282289Serj/** 137282289Serj * ixgbe_write_pe - Write register to port expander 138282289Serj * @hw: pointer to hardware structure 139282289Serj * @reg: register number to write 140282289Serj * @value: value to write 141282289Serj * 142282289Serj * Returns status code 143282289Serj **/ 144282289Serjstatic s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 145282289Serj{ 146282289Serj s32 status; 147282289Serj 148282289Serj status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 149282289Serj if (status != IXGBE_SUCCESS) 150282289Serj ERROR_REPORT2(IXGBE_ERROR_CAUTION, 151282289Serj "port expander access failed with %d\n", status); 152282289Serj return status; 153282289Serj} 154282289Serj 155282289Serj/** 156282289Serj * ixgbe_reset_cs4227 - Reset CS4227 using port expander 157282289Serj * @hw: pointer to hardware structure 158282289Serj * 159292674Ssbruno * This function assumes that the caller has acquired the proper semaphore. 160282289Serj * Returns error code 161282289Serj **/ 162282289Serjstatic s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 163282289Serj{ 164282289Serj s32 status; 165292674Ssbruno u32 retry; 166292674Ssbruno u16 value; 167282289Serj u8 reg; 168282289Serj 169292674Ssbruno /* Trigger hard reset. */ 170282289Serj status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 171282289Serj if (status != IXGBE_SUCCESS) 172282289Serj return status; 173282289Serj reg |= IXGBE_PE_BIT1; 174282289Serj status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 175282289Serj if (status != IXGBE_SUCCESS) 176282289Serj return status; 177282289Serj 178282289Serj status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 179282289Serj if (status != IXGBE_SUCCESS) 180282289Serj return status; 181282289Serj reg &= ~IXGBE_PE_BIT1; 182282289Serj status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 183282289Serj if (status != IXGBE_SUCCESS) 184282289Serj return status; 185282289Serj 186282289Serj status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 187282289Serj if (status != IXGBE_SUCCESS) 188282289Serj return status; 189282289Serj reg &= ~IXGBE_PE_BIT1; 190282289Serj status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 191282289Serj if (status != IXGBE_SUCCESS) 192282289Serj return status; 193282289Serj 194282289Serj usec_delay(IXGBE_CS4227_RESET_HOLD); 195282289Serj 196282289Serj status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 197282289Serj if (status != IXGBE_SUCCESS) 198282289Serj return status; 199282289Serj reg |= IXGBE_PE_BIT1; 200282289Serj status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 201282289Serj if (status != IXGBE_SUCCESS) 202282289Serj return status; 203282289Serj 204292674Ssbruno /* Wait for the reset to complete. */ 205282289Serj msec_delay(IXGBE_CS4227_RESET_DELAY); 206292674Ssbruno for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 207292674Ssbruno status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 208292674Ssbruno &value); 209292674Ssbruno if (status == IXGBE_SUCCESS && 210292674Ssbruno value == IXGBE_CS4227_EEPROM_LOAD_OK) 211292674Ssbruno break; 212292674Ssbruno msec_delay(IXGBE_CS4227_CHECK_DELAY); 213292674Ssbruno } 214292674Ssbruno if (retry == IXGBE_CS4227_RETRIES) { 215292674Ssbruno ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 216292674Ssbruno "CS4227 reset did not complete."); 217292674Ssbruno return IXGBE_ERR_PHY; 218292674Ssbruno } 219282289Serj 220292674Ssbruno status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 221292674Ssbruno if (status != IXGBE_SUCCESS || 222292674Ssbruno !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 223292674Ssbruno ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 224292674Ssbruno "CS4227 EEPROM did not load successfully."); 225292674Ssbruno return IXGBE_ERR_PHY; 226292674Ssbruno } 227292674Ssbruno 228282289Serj return IXGBE_SUCCESS; 229282289Serj} 230282289Serj 231282289Serj/** 232282289Serj * ixgbe_check_cs4227 - Check CS4227 and reset as needed 233282289Serj * @hw: pointer to hardware structure 234282289Serj **/ 235282289Serjstatic void ixgbe_check_cs4227(struct ixgbe_hw *hw) 236282289Serj{ 237292674Ssbruno s32 status = IXGBE_SUCCESS; 238282289Serj u32 swfw_mask = hw->phy.phy_semaphore_mask; 239292674Ssbruno u16 value = 0; 240282289Serj u8 retry; 241282289Serj 242282289Serj for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 243282289Serj status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 244282289Serj if (status != IXGBE_SUCCESS) { 245282289Serj ERROR_REPORT2(IXGBE_ERROR_CAUTION, 246292674Ssbruno "semaphore failed with %d", status); 247292674Ssbruno msec_delay(IXGBE_CS4227_CHECK_DELAY); 248292674Ssbruno continue; 249282289Serj } 250292674Ssbruno 251292674Ssbruno /* Get status of reset flow. */ 252292674Ssbruno status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 253292674Ssbruno 254292674Ssbruno if (status == IXGBE_SUCCESS && 255292674Ssbruno value == IXGBE_CS4227_RESET_COMPLETE) 256292674Ssbruno goto out; 257292674Ssbruno 258292674Ssbruno if (status != IXGBE_SUCCESS || 259292674Ssbruno value != IXGBE_CS4227_RESET_PENDING) 260292674Ssbruno break; 261292674Ssbruno 262292674Ssbruno /* Reset is pending. Wait and check again. */ 263292674Ssbruno hw->mac.ops.release_swfw_sync(hw, swfw_mask); 264292674Ssbruno msec_delay(IXGBE_CS4227_CHECK_DELAY); 265292674Ssbruno } 266292674Ssbruno 267292674Ssbruno /* If still pending, assume other instance failed. */ 268292674Ssbruno if (retry == IXGBE_CS4227_RETRIES) { 269292674Ssbruno status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 270292674Ssbruno if (status != IXGBE_SUCCESS) { 271292674Ssbruno ERROR_REPORT2(IXGBE_ERROR_CAUTION, 272292674Ssbruno "semaphore failed with %d", status); 273282289Serj return; 274282289Serj } 275282289Serj } 276292674Ssbruno 277292674Ssbruno /* Reset the CS4227. */ 278292674Ssbruno status = ixgbe_reset_cs4227(hw); 279292674Ssbruno if (status != IXGBE_SUCCESS) { 280292674Ssbruno ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 281292674Ssbruno "CS4227 reset failed: %d", status); 282292674Ssbruno goto out; 283292674Ssbruno } 284292674Ssbruno 285292674Ssbruno /* Reset takes so long, temporarily release semaphore in case the 286292674Ssbruno * other driver instance is waiting for the reset indication. 287292674Ssbruno */ 288292674Ssbruno ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 289292674Ssbruno IXGBE_CS4227_RESET_PENDING); 290292674Ssbruno hw->mac.ops.release_swfw_sync(hw, swfw_mask); 291292674Ssbruno msec_delay(10); 292292674Ssbruno status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 293292674Ssbruno if (status != IXGBE_SUCCESS) { 294292674Ssbruno ERROR_REPORT2(IXGBE_ERROR_CAUTION, 295292674Ssbruno "semaphore failed with %d", status); 296292674Ssbruno return; 297292674Ssbruno } 298292674Ssbruno 299292674Ssbruno /* Record completion for next time. */ 300292674Ssbruno status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 301292674Ssbruno IXGBE_CS4227_RESET_COMPLETE); 302292674Ssbruno 303292674Ssbrunoout: 304292674Ssbruno hw->mac.ops.release_swfw_sync(hw, swfw_mask); 305292674Ssbruno msec_delay(hw->eeprom.semaphore_delay); 306282289Serj} 307282289Serj 308282289Serj/** 309282289Serj * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 310282289Serj * @hw: pointer to hardware structure 311282289Serj **/ 312282289Serjstatic void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 313282289Serj{ 314282289Serj u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 315282289Serj 316282289Serj if (hw->bus.lan_id) { 317282289Serj esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 318282289Serj esdp |= IXGBE_ESDP_SDP1_DIR; 319282289Serj } 320282289Serj esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 321282289Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 322282289Serj IXGBE_WRITE_FLUSH(hw); 323282289Serj} 324282289Serj 325282289Serj/** 326282289Serj * ixgbe_identify_phy_x550em - Get PHY type based on device id 327282289Serj * @hw: pointer to hardware structure 328282289Serj * 329282289Serj * Returns error code 330282289Serj */ 331282289Serjstatic s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 332282289Serj{ 333282289Serj switch (hw->device_id) { 334282289Serj case IXGBE_DEV_ID_X550EM_X_SFP: 335282289Serj /* set up for CS4227 usage */ 336282289Serj hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 337282289Serj ixgbe_setup_mux_ctl(hw); 338282289Serj ixgbe_check_cs4227(hw); 339282289Serj 340282289Serj return ixgbe_identify_module_generic(hw); 341282289Serj break; 342282289Serj case IXGBE_DEV_ID_X550EM_X_KX4: 343282289Serj hw->phy.type = ixgbe_phy_x550em_kx4; 344282289Serj break; 345282289Serj case IXGBE_DEV_ID_X550EM_X_KR: 346282289Serj hw->phy.type = ixgbe_phy_x550em_kr; 347282289Serj break; 348282289Serj case IXGBE_DEV_ID_X550EM_X_1G_T: 349282289Serj case IXGBE_DEV_ID_X550EM_X_10G_T: 350282289Serj return ixgbe_identify_phy_generic(hw); 351282289Serj default: 352282289Serj break; 353282289Serj } 354282289Serj return IXGBE_SUCCESS; 355282289Serj} 356282289Serj 357282289Serjstatic s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 358282289Serj u32 device_type, u16 *phy_data) 359282289Serj{ 360282289Serj UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 361282289Serj return IXGBE_NOT_IMPLEMENTED; 362282289Serj} 363282289Serj 364282289Serjstatic s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 365282289Serj u32 device_type, u16 phy_data) 366282289Serj{ 367282289Serj UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 368282289Serj return IXGBE_NOT_IMPLEMENTED; 369282289Serj} 370282289Serj 371282289Serj/** 372282289Serj* ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 373282289Serj* @hw: pointer to hardware structure 374282289Serj* 375282289Serj* Initialize the function pointers and for MAC type X550EM. 376282289Serj* Does not touch the hardware. 377282289Serj**/ 378282289Serjs32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 379282289Serj{ 380282289Serj struct ixgbe_mac_info *mac = &hw->mac; 381282289Serj struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 382282289Serj struct ixgbe_phy_info *phy = &hw->phy; 383282289Serj s32 ret_val; 384282289Serj 385282289Serj DEBUGFUNC("ixgbe_init_ops_X550EM"); 386282289Serj 387282289Serj /* Similar to X550 so start there. */ 388282289Serj ret_val = ixgbe_init_ops_X550(hw); 389282289Serj 390282289Serj /* Since this function eventually calls 391282289Serj * ixgbe_init_ops_540 by design, we are setting 392282289Serj * the pointers to NULL explicitly here to overwrite 393282289Serj * the values being set in the x540 function. 394282289Serj */ 395282289Serj 396282289Serj /* FCOE not supported in x550EM */ 397282289Serj mac->ops.get_san_mac_addr = NULL; 398282289Serj mac->ops.set_san_mac_addr = NULL; 399282289Serj mac->ops.get_wwn_prefix = NULL; 400282289Serj mac->ops.get_fcoe_boot_status = NULL; 401282289Serj 402282289Serj /* IPsec not supported in x550EM */ 403282289Serj mac->ops.disable_sec_rx_path = NULL; 404282289Serj mac->ops.enable_sec_rx_path = NULL; 405282289Serj 406282289Serj /* AUTOC register is not present in x550EM. */ 407282289Serj mac->ops.prot_autoc_read = NULL; 408282289Serj mac->ops.prot_autoc_write = NULL; 409282289Serj 410282289Serj /* X550EM bus type is internal*/ 411282289Serj hw->bus.type = ixgbe_bus_type_internal; 412282289Serj mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 413282289Serj 414292674Ssbruno if (hw->mac.type == ixgbe_mac_X550EM_x) { 415292674Ssbruno mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 416292674Ssbruno mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 417292674Ssbruno } 418292674Ssbruno 419282289Serj mac->ops.get_media_type = ixgbe_get_media_type_X550em; 420282289Serj mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 421282289Serj mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 422282289Serj mac->ops.reset_hw = ixgbe_reset_hw_X550em; 423282289Serj mac->ops.get_supported_physical_layer = 424282289Serj ixgbe_get_supported_physical_layer_X550em; 425282289Serj 426282289Serj if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 427282289Serj mac->ops.setup_fc = ixgbe_setup_fc_generic; 428282289Serj else 429282289Serj mac->ops.setup_fc = ixgbe_setup_fc_X550em; 430282289Serj 431282289Serj mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 432282289Serj mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 433282289Serj 434282289Serj if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR) 435282289Serj mac->ops.setup_eee = NULL; 436282289Serj 437282289Serj /* PHY */ 438282289Serj phy->ops.init = ixgbe_init_phy_ops_X550em; 439282289Serj phy->ops.identify = ixgbe_identify_phy_x550em; 440282289Serj if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 441282289Serj phy->ops.set_phy_power = NULL; 442282289Serj 443282289Serj 444282289Serj /* EEPROM */ 445282289Serj eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 446282289Serj eeprom->ops.read = ixgbe_read_ee_hostif_X550; 447282289Serj eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 448282289Serj eeprom->ops.write = ixgbe_write_ee_hostif_X550; 449282289Serj eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 450282289Serj eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 451282289Serj eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 452282289Serj eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 453282289Serj 454282289Serj return ret_val; 455282289Serj} 456282289Serj 457282289Serj/** 458282289Serj * ixgbe_dmac_config_X550 459282289Serj * @hw: pointer to hardware structure 460282289Serj * 461282289Serj * Configure DMA coalescing. If enabling dmac, dmac is activated. 462282289Serj * When disabling dmac, dmac enable dmac bit is cleared. 463282289Serj **/ 464282289Serjs32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 465282289Serj{ 466282289Serj u32 reg, high_pri_tc; 467282289Serj 468282289Serj DEBUGFUNC("ixgbe_dmac_config_X550"); 469282289Serj 470282289Serj /* Disable DMA coalescing before configuring */ 471282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 472282289Serj reg &= ~IXGBE_DMACR_DMAC_EN; 473282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 474282289Serj 475282289Serj /* Disable DMA Coalescing if the watchdog timer is 0 */ 476282289Serj if (!hw->mac.dmac_config.watchdog_timer) 477282289Serj goto out; 478282289Serj 479282289Serj ixgbe_dmac_config_tcs_X550(hw); 480282289Serj 481282289Serj /* Configure DMA Coalescing Control Register */ 482282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 483282289Serj 484282289Serj /* Set the watchdog timer in units of 40.96 usec */ 485282289Serj reg &= ~IXGBE_DMACR_DMACWT_MASK; 486282289Serj reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 487282289Serj 488282289Serj reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 489282289Serj /* If fcoe is enabled, set high priority traffic class */ 490282289Serj if (hw->mac.dmac_config.fcoe_en) { 491282289Serj high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 492282289Serj reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 493282289Serj IXGBE_DMACR_HIGH_PRI_TC_MASK); 494282289Serj } 495282289Serj reg |= IXGBE_DMACR_EN_MNG_IND; 496282289Serj 497282289Serj /* Enable DMA coalescing after configuration */ 498282289Serj reg |= IXGBE_DMACR_DMAC_EN; 499282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 500282289Serj 501282289Serjout: 502282289Serj return IXGBE_SUCCESS; 503282289Serj} 504282289Serj 505282289Serj/** 506282289Serj * ixgbe_dmac_config_tcs_X550 507282289Serj * @hw: pointer to hardware structure 508282289Serj * 509282289Serj * Configure DMA coalescing threshold per TC. The dmac enable bit must 510282289Serj * be cleared before configuring. 511282289Serj **/ 512282289Serjs32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 513282289Serj{ 514282289Serj u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 515282289Serj 516282289Serj DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 517282289Serj 518282289Serj /* Configure DMA coalescing enabled */ 519282289Serj switch (hw->mac.dmac_config.link_speed) { 520282289Serj case IXGBE_LINK_SPEED_100_FULL: 521282289Serj pb_headroom = IXGBE_DMACRXT_100M; 522282289Serj break; 523282289Serj case IXGBE_LINK_SPEED_1GB_FULL: 524282289Serj pb_headroom = IXGBE_DMACRXT_1G; 525282289Serj break; 526282289Serj default: 527282289Serj pb_headroom = IXGBE_DMACRXT_10G; 528282289Serj break; 529282289Serj } 530282289Serj 531282289Serj maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 532282289Serj IXGBE_MHADD_MFS_SHIFT) / 1024); 533282289Serj 534282289Serj /* Set the per Rx packet buffer receive threshold */ 535282289Serj for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 536282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 537282289Serj reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 538282289Serj 539282289Serj if (tc < hw->mac.dmac_config.num_tcs) { 540282289Serj /* Get Rx PB size */ 541282289Serj rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 542282289Serj rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 543282289Serj IXGBE_RXPBSIZE_SHIFT; 544282289Serj 545282289Serj /* Calculate receive buffer threshold in kilobytes */ 546282289Serj if (rx_pb_size > pb_headroom) 547282289Serj rx_pb_size = rx_pb_size - pb_headroom; 548282289Serj else 549282289Serj rx_pb_size = 0; 550282289Serj 551282289Serj /* Minimum of MFS shall be set for DMCTH */ 552282289Serj reg |= (rx_pb_size > maxframe_size_kb) ? 553282289Serj rx_pb_size : maxframe_size_kb; 554282289Serj } 555282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 556282289Serj } 557282289Serj return IXGBE_SUCCESS; 558282289Serj} 559282289Serj 560282289Serj/** 561282289Serj * ixgbe_dmac_update_tcs_X550 562282289Serj * @hw: pointer to hardware structure 563282289Serj * 564282289Serj * Disables dmac, updates per TC settings, and then enables dmac. 565282289Serj **/ 566282289Serjs32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 567282289Serj{ 568282289Serj u32 reg; 569282289Serj 570282289Serj DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 571282289Serj 572282289Serj /* Disable DMA coalescing before configuring */ 573282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 574282289Serj reg &= ~IXGBE_DMACR_DMAC_EN; 575282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 576282289Serj 577282289Serj ixgbe_dmac_config_tcs_X550(hw); 578282289Serj 579282289Serj /* Enable DMA coalescing after configuration */ 580282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 581282289Serj reg |= IXGBE_DMACR_DMAC_EN; 582282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 583282289Serj 584282289Serj return IXGBE_SUCCESS; 585282289Serj} 586282289Serj 587282289Serj/** 588282289Serj * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 589282289Serj * @hw: pointer to hardware structure 590282289Serj * 591282289Serj * Initializes the EEPROM parameters ixgbe_eeprom_info within the 592282289Serj * ixgbe_hw struct in order to set up EEPROM access. 593282289Serj **/ 594282289Serjs32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 595282289Serj{ 596282289Serj struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 597282289Serj u32 eec; 598282289Serj u16 eeprom_size; 599282289Serj 600282289Serj DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 601282289Serj 602282289Serj if (eeprom->type == ixgbe_eeprom_uninitialized) { 603282289Serj eeprom->semaphore_delay = 10; 604282289Serj eeprom->type = ixgbe_flash; 605282289Serj 606282289Serj eec = IXGBE_READ_REG(hw, IXGBE_EEC); 607282289Serj eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 608282289Serj IXGBE_EEC_SIZE_SHIFT); 609282289Serj eeprom->word_size = 1 << (eeprom_size + 610282289Serj IXGBE_EEPROM_WORD_SIZE_SHIFT); 611282289Serj 612282289Serj DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 613282289Serj eeprom->type, eeprom->word_size); 614282289Serj } 615282289Serj 616282289Serj return IXGBE_SUCCESS; 617282289Serj} 618282289Serj 619282289Serj/** 620282289Serj * ixgbe_setup_eee_X550 - Enable/disable EEE support 621282289Serj * @hw: pointer to the HW structure 622282289Serj * @enable_eee: boolean flag to enable EEE 623282289Serj * 624282289Serj * Enable/disable EEE based on enable_eee flag. 625282289Serj * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 626282289Serj * are modified. 627282289Serj * 628282289Serj **/ 629282289Serjs32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) 630282289Serj{ 631282289Serj u32 eeer; 632282289Serj u16 autoneg_eee_reg; 633282289Serj u32 link_reg; 634282289Serj s32 status; 635282289Serj u32 fuse; 636282289Serj 637282289Serj DEBUGFUNC("ixgbe_setup_eee_X550"); 638282289Serj 639282289Serj eeer = IXGBE_READ_REG(hw, IXGBE_EEER); 640282289Serj /* Enable or disable EEE per flag */ 641282289Serj if (enable_eee) { 642282289Serj eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 643282289Serj 644292674Ssbruno if (hw->mac.type == ixgbe_mac_X550) { 645282289Serj /* Advertise EEE capability */ 646282289Serj hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 647282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 648282289Serj 649282289Serj autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 650282289Serj IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 651282289Serj IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 652282289Serj 653282289Serj hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 654282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 655282289Serj } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 656282289Serj /* Not supported on first revision. */ 657282289Serj fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)); 658282289Serj if (!(fuse & IXGBE_FUSES0_REV1)) 659282289Serj return IXGBE_SUCCESS; 660282289Serj 661282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 662282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 663282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 664282289Serj if (status != IXGBE_SUCCESS) 665282289Serj return status; 666282289Serj 667282289Serj link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 668282289Serj IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX; 669282289Serj 670282289Serj /* Don't advertise FEC capability when EEE enabled. */ 671282289Serj link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 672282289Serj 673282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 674282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 675282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 676282289Serj if (status != IXGBE_SUCCESS) 677282289Serj return status; 678282289Serj } 679282289Serj } else { 680282289Serj eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 681282289Serj 682292674Ssbruno if (hw->mac.type == ixgbe_mac_X550) { 683282289Serj /* Disable advertised EEE capability */ 684282289Serj hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 685282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 686282289Serj 687282289Serj autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 688282289Serj IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 689282289Serj IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 690282289Serj 691282289Serj hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 692282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 693282289Serj } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 694282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 695282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 696282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 697282289Serj if (status != IXGBE_SUCCESS) 698282289Serj return status; 699282289Serj 700282289Serj link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 701282289Serj IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX); 702282289Serj 703282289Serj /* Advertise FEC capability when EEE is disabled. */ 704282289Serj link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 705282289Serj 706282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 707282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 708282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 709282289Serj if (status != IXGBE_SUCCESS) 710282289Serj return status; 711282289Serj } 712282289Serj } 713282289Serj IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer); 714282289Serj 715282289Serj return IXGBE_SUCCESS; 716282289Serj} 717282289Serj 718282289Serj/** 719282289Serj * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 720282289Serj * @hw: pointer to hardware structure 721282289Serj * @enable: enable or disable source address pruning 722282289Serj * @pool: Rx pool to set source address pruning for 723282289Serj **/ 724282289Serjvoid ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 725282289Serj unsigned int pool) 726282289Serj{ 727282289Serj u64 pfflp; 728282289Serj 729282289Serj /* max rx pool is 63 */ 730282289Serj if (pool > 63) 731282289Serj return; 732282289Serj 733282289Serj pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 734282289Serj pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 735282289Serj 736282289Serj if (enable) 737282289Serj pfflp |= (1ULL << pool); 738282289Serj else 739282289Serj pfflp &= ~(1ULL << pool); 740282289Serj 741282289Serj IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 742282289Serj IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 743282289Serj} 744282289Serj 745282289Serj/** 746282289Serj * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 747282289Serj * @hw: pointer to hardware structure 748282289Serj * @enable: enable or disable switch for Ethertype anti-spoofing 749282289Serj * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 750282289Serj * 751282289Serj **/ 752282289Serjvoid ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 753282289Serj bool enable, int vf) 754282289Serj{ 755282289Serj int vf_target_reg = vf >> 3; 756282289Serj int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 757282289Serj u32 pfvfspoof; 758282289Serj 759282289Serj DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 760282289Serj 761282289Serj pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 762282289Serj if (enable) 763282289Serj pfvfspoof |= (1 << vf_target_shift); 764282289Serj else 765282289Serj pfvfspoof &= ~(1 << vf_target_shift); 766282289Serj 767282289Serj IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 768282289Serj} 769282289Serj 770282289Serj/** 771282289Serj * ixgbe_iosf_wait - Wait for IOSF command completion 772282289Serj * @hw: pointer to hardware structure 773282289Serj * @ctrl: pointer to location to receive final IOSF control value 774282289Serj * 775282289Serj * Returns failing status on timeout 776282289Serj * 777282289Serj * Note: ctrl can be NULL if the IOSF control register value is not needed 778282289Serj **/ 779282289Serjstatic s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 780282289Serj{ 781292674Ssbruno u32 i, command = 0; 782282289Serj 783282289Serj /* Check every 10 usec to see if the address cycle completed. 784282289Serj * The SB IOSF BUSY bit will clear when the operation is 785282289Serj * complete 786282289Serj */ 787282289Serj for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 788282289Serj command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 789282289Serj if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 790282289Serj break; 791282289Serj usec_delay(10); 792282289Serj } 793282289Serj if (ctrl) 794282289Serj *ctrl = command; 795282289Serj if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 796282289Serj ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 797282289Serj return IXGBE_ERR_PHY; 798282289Serj } 799282289Serj 800282289Serj return IXGBE_SUCCESS; 801282289Serj} 802282289Serj 803282289Serj/** 804282289Serj * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 805282289Serj * device 806282289Serj * @hw: pointer to hardware structure 807282289Serj * @reg_addr: 32 bit PHY register to write 808282289Serj * @device_type: 3 bit device type 809282289Serj * @data: Data to write to the register 810282289Serj **/ 811282289Serjs32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 812282289Serj u32 device_type, u32 data) 813282289Serj{ 814282289Serj u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 815282289Serj u32 command, error; 816282289Serj s32 ret; 817282289Serj 818282289Serj ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 819282289Serj if (ret != IXGBE_SUCCESS) 820282289Serj return ret; 821282289Serj 822282289Serj ret = ixgbe_iosf_wait(hw, NULL); 823282289Serj if (ret != IXGBE_SUCCESS) 824282289Serj goto out; 825282289Serj 826282289Serj command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 827282289Serj (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 828282289Serj 829282289Serj /* Write IOSF control register */ 830282289Serj IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 831282289Serj 832282289Serj /* Write IOSF data register */ 833282289Serj IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 834282289Serj 835282289Serj ret = ixgbe_iosf_wait(hw, &command); 836282289Serj 837282289Serj if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 838282289Serj error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 839282289Serj IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 840282289Serj ERROR_REPORT2(IXGBE_ERROR_POLLING, 841282289Serj "Failed to write, error %x\n", error); 842282289Serj ret = IXGBE_ERR_PHY; 843282289Serj } 844282289Serj 845282289Serjout: 846282289Serj ixgbe_release_swfw_semaphore(hw, gssr); 847282289Serj return ret; 848282289Serj} 849282289Serj 850282289Serj/** 851282289Serj * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 852282289Serj * device 853282289Serj * @hw: pointer to hardware structure 854282289Serj * @reg_addr: 32 bit PHY register to write 855282289Serj * @device_type: 3 bit device type 856282289Serj * @phy_data: Pointer to read data from the register 857282289Serj **/ 858282289Serjs32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 859282289Serj u32 device_type, u32 *data) 860282289Serj{ 861282289Serj u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 862282289Serj u32 command, error; 863282289Serj s32 ret; 864282289Serj 865282289Serj ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 866282289Serj if (ret != IXGBE_SUCCESS) 867282289Serj return ret; 868282289Serj 869282289Serj ret = ixgbe_iosf_wait(hw, NULL); 870282289Serj if (ret != IXGBE_SUCCESS) 871282289Serj goto out; 872282289Serj 873282289Serj command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 874282289Serj (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 875282289Serj 876282289Serj /* Write IOSF control register */ 877282289Serj IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 878282289Serj 879282289Serj ret = ixgbe_iosf_wait(hw, &command); 880282289Serj 881282289Serj if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 882282289Serj error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 883282289Serj IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 884282289Serj ERROR_REPORT2(IXGBE_ERROR_POLLING, 885282289Serj "Failed to read, error %x\n", error); 886282289Serj ret = IXGBE_ERR_PHY; 887282289Serj } 888282289Serj 889282289Serj if (ret == IXGBE_SUCCESS) 890282289Serj *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 891282289Serj 892282289Serjout: 893282289Serj ixgbe_release_swfw_semaphore(hw, gssr); 894282289Serj return ret; 895282289Serj} 896282289Serj 897282289Serj/** 898282289Serj * ixgbe_disable_mdd_X550 899282289Serj * @hw: pointer to hardware structure 900282289Serj * 901282289Serj * Disable malicious driver detection 902282289Serj **/ 903282289Serjvoid ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 904282289Serj{ 905282289Serj u32 reg; 906282289Serj 907282289Serj DEBUGFUNC("ixgbe_disable_mdd_X550"); 908282289Serj 909282289Serj /* Disable MDD for TX DMA and interrupt */ 910282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 911282289Serj reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 912282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 913282289Serj 914282289Serj /* Disable MDD for RX and interrupt */ 915282289Serj reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 916282289Serj reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 917282289Serj IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 918282289Serj} 919282289Serj 920282289Serj/** 921282289Serj * ixgbe_enable_mdd_X550 922282289Serj * @hw: pointer to hardware structure 923282289Serj * 924282289Serj * Enable malicious driver detection 925282289Serj **/ 926282289Serjvoid ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 927282289Serj{ 928282289Serj u32 reg; 929282289Serj 930282289Serj DEBUGFUNC("ixgbe_enable_mdd_X550"); 931282289Serj 932282289Serj /* Enable MDD for TX DMA and interrupt */ 933282289Serj reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 934282289Serj reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 935282289Serj IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 936282289Serj 937282289Serj /* Enable MDD for RX and interrupt */ 938282289Serj reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 939282289Serj reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 940282289Serj IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 941282289Serj} 942282289Serj 943282289Serj/** 944282289Serj * ixgbe_restore_mdd_vf_X550 945282289Serj * @hw: pointer to hardware structure 946282289Serj * @vf: vf index 947282289Serj * 948282289Serj * Restore VF that was disabled during malicious driver detection event 949282289Serj **/ 950282289Serjvoid ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 951282289Serj{ 952282289Serj u32 idx, reg, num_qs, start_q, bitmask; 953282289Serj 954282289Serj DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 955282289Serj 956282289Serj /* Map VF to queues */ 957282289Serj reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 958282289Serj switch (reg & IXGBE_MRQC_MRQE_MASK) { 959282289Serj case IXGBE_MRQC_VMDQRT8TCEN: 960282289Serj num_qs = 8; /* 16 VFs / pools */ 961282289Serj bitmask = 0x000000FF; 962282289Serj break; 963282289Serj case IXGBE_MRQC_VMDQRSS32EN: 964282289Serj case IXGBE_MRQC_VMDQRT4TCEN: 965282289Serj num_qs = 4; /* 32 VFs / pools */ 966282289Serj bitmask = 0x0000000F; 967282289Serj break; 968295093Ssmh default: /* 64 VFs / pools */ 969282289Serj num_qs = 2; 970282289Serj bitmask = 0x00000003; 971282289Serj break; 972282289Serj } 973282289Serj start_q = vf * num_qs; 974282289Serj 975282289Serj /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 976282289Serj idx = start_q / 32; 977282289Serj reg = 0; 978282289Serj reg |= (bitmask << (start_q % 32)); 979282289Serj IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 980282289Serj IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 981282289Serj} 982282289Serj 983282289Serj/** 984282289Serj * ixgbe_mdd_event_X550 985282289Serj * @hw: pointer to hardware structure 986282289Serj * @vf_bitmap: vf bitmap of malicious vfs 987282289Serj * 988282289Serj * Handle malicious driver detection event. 989282289Serj **/ 990282289Serjvoid ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 991282289Serj{ 992282289Serj u32 wqbr; 993282289Serj u32 i, j, reg, q, shift, vf, idx; 994282289Serj 995282289Serj DEBUGFUNC("ixgbe_mdd_event_X550"); 996282289Serj 997282289Serj /* figure out pool size for mapping to vf's */ 998282289Serj reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 999282289Serj switch (reg & IXGBE_MRQC_MRQE_MASK) { 1000282289Serj case IXGBE_MRQC_VMDQRT8TCEN: 1001282289Serj shift = 3; /* 16 VFs / pools */ 1002282289Serj break; 1003282289Serj case IXGBE_MRQC_VMDQRSS32EN: 1004282289Serj case IXGBE_MRQC_VMDQRT4TCEN: 1005282289Serj shift = 2; /* 32 VFs / pools */ 1006282289Serj break; 1007282289Serj default: 1008282289Serj shift = 1; /* 64 VFs / pools */ 1009282289Serj break; 1010282289Serj } 1011282289Serj 1012282289Serj /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1013282289Serj for (i = 0; i < 4; i++) { 1014282289Serj wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1015282289Serj wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1016282289Serj 1017282289Serj if (!wqbr) 1018282289Serj continue; 1019282289Serj 1020282289Serj /* Get malicious queue */ 1021282289Serj for (j = 0; j < 32 && wqbr; j++) { 1022282289Serj 1023282289Serj if (!(wqbr & (1 << j))) 1024282289Serj continue; 1025282289Serj 1026282289Serj /* Get queue from bitmask */ 1027282289Serj q = j + (i * 32); 1028282289Serj 1029282289Serj /* Map queue to vf */ 1030282289Serj vf = (q >> shift); 1031282289Serj 1032282289Serj /* Set vf bit in vf_bitmap */ 1033282289Serj idx = vf / 32; 1034282289Serj vf_bitmap[idx] |= (1 << (vf % 32)); 1035282289Serj wqbr &= ~(1 << j); 1036282289Serj } 1037282289Serj } 1038282289Serj} 1039282289Serj 1040282289Serj/** 1041282289Serj * ixgbe_get_media_type_X550em - Get media type 1042282289Serj * @hw: pointer to hardware structure 1043282289Serj * 1044282289Serj * Returns the media type (fiber, copper, backplane) 1045282289Serj */ 1046282289Serjenum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1047282289Serj{ 1048282289Serj enum ixgbe_media_type media_type; 1049282289Serj 1050282289Serj DEBUGFUNC("ixgbe_get_media_type_X550em"); 1051282289Serj 1052282289Serj /* Detect if there is a copper PHY attached. */ 1053282289Serj switch (hw->device_id) { 1054282289Serj case IXGBE_DEV_ID_X550EM_X_KR: 1055282289Serj case IXGBE_DEV_ID_X550EM_X_KX4: 1056282289Serj media_type = ixgbe_media_type_backplane; 1057282289Serj break; 1058282289Serj case IXGBE_DEV_ID_X550EM_X_SFP: 1059282289Serj media_type = ixgbe_media_type_fiber; 1060282289Serj break; 1061282289Serj case IXGBE_DEV_ID_X550EM_X_1G_T: 1062282289Serj case IXGBE_DEV_ID_X550EM_X_10G_T: 1063282289Serj media_type = ixgbe_media_type_copper; 1064282289Serj break; 1065282289Serj default: 1066282289Serj media_type = ixgbe_media_type_unknown; 1067282289Serj break; 1068282289Serj } 1069282289Serj return media_type; 1070282289Serj} 1071282289Serj 1072282289Serj/** 1073282289Serj * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1074282289Serj * @hw: pointer to hardware structure 1075282289Serj * @linear: TRUE if SFP module is linear 1076282289Serj */ 1077282289Serjstatic s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1078282289Serj{ 1079282289Serj DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1080282289Serj 1081282289Serj switch (hw->phy.sfp_type) { 1082282289Serj case ixgbe_sfp_type_not_present: 1083282289Serj return IXGBE_ERR_SFP_NOT_PRESENT; 1084282289Serj case ixgbe_sfp_type_da_cu_core0: 1085282289Serj case ixgbe_sfp_type_da_cu_core1: 1086282289Serj *linear = TRUE; 1087282289Serj break; 1088282289Serj case ixgbe_sfp_type_srlr_core0: 1089282289Serj case ixgbe_sfp_type_srlr_core1: 1090282289Serj case ixgbe_sfp_type_da_act_lmt_core0: 1091282289Serj case ixgbe_sfp_type_da_act_lmt_core1: 1092282289Serj case ixgbe_sfp_type_1g_sx_core0: 1093282289Serj case ixgbe_sfp_type_1g_sx_core1: 1094282289Serj case ixgbe_sfp_type_1g_lx_core0: 1095282289Serj case ixgbe_sfp_type_1g_lx_core1: 1096282289Serj *linear = FALSE; 1097282289Serj break; 1098282289Serj case ixgbe_sfp_type_unknown: 1099282289Serj case ixgbe_sfp_type_1g_cu_core0: 1100282289Serj case ixgbe_sfp_type_1g_cu_core1: 1101282289Serj default: 1102282289Serj return IXGBE_ERR_SFP_NOT_SUPPORTED; 1103282289Serj } 1104282289Serj 1105282289Serj return IXGBE_SUCCESS; 1106282289Serj} 1107282289Serj 1108282289Serj/** 1109282289Serj * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1110282289Serj * @hw: pointer to hardware structure 1111282289Serj * 1112282289Serj * Searches for and identifies the SFP module and assigns appropriate PHY type. 1113282289Serj **/ 1114282289Serjs32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1115282289Serj{ 1116282289Serj s32 status; 1117282289Serj bool linear; 1118282289Serj 1119282289Serj DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1120282289Serj 1121282289Serj status = ixgbe_identify_module_generic(hw); 1122282289Serj 1123282289Serj if (status != IXGBE_SUCCESS) 1124282289Serj return status; 1125282289Serj 1126282289Serj /* Check if SFP module is supported */ 1127282289Serj status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1128282289Serj 1129282289Serj return status; 1130282289Serj} 1131282289Serj 1132282289Serj/** 1133282289Serj * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1134282289Serj * @hw: pointer to hardware structure 1135282289Serj */ 1136282289Serjs32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1137282289Serj{ 1138282289Serj s32 status; 1139282289Serj bool linear; 1140282289Serj 1141282289Serj DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1142282289Serj 1143282289Serj /* Check if SFP module is supported */ 1144282289Serj status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1145282289Serj 1146282289Serj if (status != IXGBE_SUCCESS) 1147282289Serj return status; 1148282289Serj 1149282289Serj ixgbe_init_mac_link_ops_X550em(hw); 1150282289Serj hw->phy.ops.reset = NULL; 1151282289Serj 1152282289Serj return IXGBE_SUCCESS; 1153282289Serj} 1154282289Serj 1155282289Serj/** 1156282289Serj * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1157282289Serj * @hw: pointer to hardware structure 1158282289Serj */ 1159282289Serjvoid ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1160282289Serj{ 1161282289Serj struct ixgbe_mac_info *mac = &hw->mac; 1162282289Serj 1163282289Serj DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1164282289Serj 1165282289Serj switch (hw->mac.ops.get_media_type(hw)) { 1166282289Serj case ixgbe_media_type_fiber: 1167282289Serj /* CS4227 does not support autoneg, so disable the laser control 1168282289Serj * functions for SFP+ fiber 1169282289Serj */ 1170282289Serj mac->ops.disable_tx_laser = NULL; 1171282289Serj mac->ops.enable_tx_laser = NULL; 1172282289Serj mac->ops.flap_tx_laser = NULL; 1173282289Serj mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1174282289Serj mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; 1175282289Serj mac->ops.set_rate_select_speed = 1176282289Serj ixgbe_set_soft_rate_select_speed; 1177282289Serj break; 1178282289Serj case ixgbe_media_type_copper: 1179282289Serj mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1180282289Serj mac->ops.check_link = ixgbe_check_link_t_X550em; 1181282289Serj break; 1182282289Serj default: 1183282289Serj break; 1184282289Serj } 1185282289Serj} 1186282289Serj 1187282289Serj/** 1188282289Serj * ixgbe_get_link_capabilities_x550em - Determines link capabilities 1189282289Serj * @hw: pointer to hardware structure 1190282289Serj * @speed: pointer to link speed 1191282289Serj * @autoneg: TRUE when autoneg or autotry is enabled 1192282289Serj */ 1193282289Serjs32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1194282289Serj ixgbe_link_speed *speed, 1195282289Serj bool *autoneg) 1196282289Serj{ 1197282289Serj DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 1198282289Serj 1199282289Serj /* SFP */ 1200282289Serj if (hw->phy.media_type == ixgbe_media_type_fiber) { 1201282289Serj 1202282289Serj /* CS4227 SFP must not enable auto-negotiation */ 1203282289Serj *autoneg = FALSE; 1204282289Serj 1205282289Serj /* Check if 1G SFP module. */ 1206282289Serj if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1207282289Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 1208282289Serj || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1209282289Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 1210282289Serj *speed = IXGBE_LINK_SPEED_1GB_FULL; 1211282289Serj return IXGBE_SUCCESS; 1212282289Serj } 1213282289Serj 1214282289Serj /* Link capabilities are based on SFP */ 1215282289Serj if (hw->phy.multispeed_fiber) 1216282289Serj *speed = IXGBE_LINK_SPEED_10GB_FULL | 1217282289Serj IXGBE_LINK_SPEED_1GB_FULL; 1218282289Serj else 1219282289Serj *speed = IXGBE_LINK_SPEED_10GB_FULL; 1220282289Serj } else { 1221282289Serj *speed = IXGBE_LINK_SPEED_10GB_FULL | 1222282289Serj IXGBE_LINK_SPEED_1GB_FULL; 1223282289Serj *autoneg = TRUE; 1224282289Serj } 1225282289Serj 1226282289Serj return IXGBE_SUCCESS; 1227282289Serj} 1228282289Serj 1229282289Serj/** 1230282289Serj * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1231282289Serj * @hw: pointer to hardware structure 1232282289Serj * @lsc: pointer to boolean flag which indicates whether external Base T 1233282289Serj * PHY interrupt is lsc 1234282289Serj * 1235282289Serj * Determime if external Base T PHY interrupt cause is high temperature 1236282289Serj * failure alarm or link status change. 1237282289Serj * 1238282289Serj * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1239282289Serj * failure alarm, else return PHY access status. 1240282289Serj */ 1241282289Serjstatic s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1242282289Serj{ 1243282289Serj u32 status; 1244282289Serj u16 reg; 1245282289Serj 1246282289Serj *lsc = FALSE; 1247282289Serj 1248282289Serj /* Vendor alarm triggered */ 1249282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1250282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1251282289Serj ®); 1252282289Serj 1253282289Serj if (status != IXGBE_SUCCESS || 1254282289Serj !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1255282289Serj return status; 1256282289Serj 1257282289Serj /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1258282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1259282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1260282289Serj ®); 1261282289Serj 1262282289Serj if (status != IXGBE_SUCCESS || 1263282289Serj !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1264282289Serj IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1265282289Serj return status; 1266282289Serj 1267295093Ssmh /* Global alarm triggered */ 1268282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1269282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1270282289Serj ®); 1271282289Serj 1272282289Serj if (status != IXGBE_SUCCESS) 1273282289Serj return status; 1274282289Serj 1275282289Serj /* If high temperature failure, then return over temp error and exit */ 1276282289Serj if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1277282289Serj /* power down the PHY in case the PHY FW didn't already */ 1278282289Serj ixgbe_set_copper_phy_power(hw, FALSE); 1279282289Serj return IXGBE_ERR_OVERTEMP; 1280295093Ssmh } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 1281295093Ssmh /* device fault alarm triggered */ 1282295093Ssmh status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 1283295093Ssmh IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1284295093Ssmh ®); 1285295093Ssmh 1286295093Ssmh if (status != IXGBE_SUCCESS) 1287295093Ssmh return status; 1288295093Ssmh 1289295093Ssmh /* if device fault was due to high temp alarm handle and exit */ 1290295093Ssmh if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 1291295093Ssmh /* power down the PHY in case the PHY FW didn't */ 1292295093Ssmh ixgbe_set_copper_phy_power(hw, FALSE); 1293295093Ssmh return IXGBE_ERR_OVERTEMP; 1294295093Ssmh } 1295282289Serj } 1296282289Serj 1297282289Serj /* Vendor alarm 2 triggered */ 1298282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1299282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1300282289Serj 1301282289Serj if (status != IXGBE_SUCCESS || 1302282289Serj !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1303282289Serj return status; 1304282289Serj 1305282289Serj /* link connect/disconnect event occurred */ 1306282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1307282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1308282289Serj 1309282289Serj if (status != IXGBE_SUCCESS) 1310282289Serj return status; 1311282289Serj 1312282289Serj /* Indicate LSC */ 1313282289Serj if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1314282289Serj *lsc = TRUE; 1315282289Serj 1316282289Serj return IXGBE_SUCCESS; 1317282289Serj} 1318282289Serj 1319282289Serj/** 1320282289Serj * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1321282289Serj * @hw: pointer to hardware structure 1322282289Serj * 1323282289Serj * Enable link status change and temperature failure alarm for the external 1324282289Serj * Base T PHY 1325282289Serj * 1326282289Serj * Returns PHY access status 1327282289Serj */ 1328282289Serjstatic s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1329282289Serj{ 1330282289Serj u32 status; 1331282289Serj u16 reg; 1332282289Serj bool lsc; 1333282289Serj 1334282289Serj /* Clear interrupt flags */ 1335282289Serj status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1336282289Serj 1337282289Serj /* Enable link status change alarm */ 1338282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1339282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1340282289Serj 1341282289Serj if (status != IXGBE_SUCCESS) 1342282289Serj return status; 1343282289Serj 1344282289Serj reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1345282289Serj 1346282289Serj status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1347282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1348282289Serj 1349282289Serj if (status != IXGBE_SUCCESS) 1350282289Serj return status; 1351282289Serj 1352282289Serj /* Enables high temperature failure alarm */ 1353282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1354282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1355282289Serj ®); 1356282289Serj 1357282289Serj if (status != IXGBE_SUCCESS) 1358282289Serj return status; 1359282289Serj 1360282289Serj reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1361282289Serj 1362282289Serj status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1363282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1364282289Serj reg); 1365282289Serj 1366282289Serj if (status != IXGBE_SUCCESS) 1367282289Serj return status; 1368282289Serj 1369282289Serj /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1370282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1371282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1372282289Serj ®); 1373282289Serj 1374282289Serj if (status != IXGBE_SUCCESS) 1375282289Serj return status; 1376282289Serj 1377282289Serj reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1378282289Serj IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1379282289Serj 1380282289Serj status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1381282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1382282289Serj reg); 1383282289Serj 1384282289Serj if (status != IXGBE_SUCCESS) 1385282289Serj return status; 1386282289Serj 1387282289Serj /* Enable chip-wide vendor alarm */ 1388282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1389282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1390282289Serj ®); 1391282289Serj 1392282289Serj if (status != IXGBE_SUCCESS) 1393282289Serj return status; 1394282289Serj 1395282289Serj reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1396282289Serj 1397282289Serj status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1398282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1399282289Serj reg); 1400282289Serj 1401282289Serj return status; 1402282289Serj} 1403282289Serj 1404282289Serj/** 1405282289Serj * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1406282289Serj * @hw: pointer to hardware structure 1407282289Serj * @speed: link speed 1408282289Serj * 1409282289Serj * Configures the integrated KR PHY. 1410282289Serj **/ 1411282289Serjstatic s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1412282289Serj ixgbe_link_speed speed) 1413282289Serj{ 1414282289Serj s32 status; 1415282289Serj u32 reg_val; 1416282289Serj 1417282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1418282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1419282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1420282289Serj if (status) 1421282289Serj return status; 1422282289Serj 1423282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1424282289Serj reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1425282289Serj IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1426282289Serj 1427282289Serj /* Advertise 10G support. */ 1428282289Serj if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1429282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1430282289Serj 1431282289Serj /* Advertise 1G support. */ 1432282289Serj if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1433282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1434282289Serj 1435282289Serj /* Restart auto-negotiation. */ 1436282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1437282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1438282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1439282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1440282289Serj 1441282289Serj return status; 1442282289Serj} 1443282289Serj 1444282289Serj/** 1445282289Serj * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1446282289Serj * @hw: pointer to hardware structure 1447282289Serj * 1448282289Serj * Initialize any function pointers that were not able to be 1449282289Serj * set during init_shared_code because the PHY/SFP type was 1450282289Serj * not known. Perform the SFP init if necessary. 1451282289Serj */ 1452282289Serjs32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1453282289Serj{ 1454282289Serj struct ixgbe_phy_info *phy = &hw->phy; 1455282289Serj ixgbe_link_speed speed; 1456282289Serj s32 ret_val; 1457282289Serj 1458282289Serj DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 1459282289Serj 1460282289Serj hw->mac.ops.set_lan_id(hw); 1461282289Serj 1462282289Serj if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1463282289Serj phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1464282289Serj ixgbe_setup_mux_ctl(hw); 1465282289Serj 1466282289Serj /* Save NW management interface connected on board. This is used 1467282289Serj * to determine internal PHY mode. 1468282289Serj */ 1469282289Serj phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1470282289Serj if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1471282289Serj speed = IXGBE_LINK_SPEED_10GB_FULL | 1472282289Serj IXGBE_LINK_SPEED_1GB_FULL; 1473282289Serj } 1474282289Serj phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 1475282289Serj } 1476282289Serj 1477282289Serj /* Identify the PHY or SFP module */ 1478282289Serj ret_val = phy->ops.identify(hw); 1479282289Serj if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 1480282289Serj return ret_val; 1481282289Serj 1482282289Serj /* Setup function pointers based on detected hardware */ 1483282289Serj ixgbe_init_mac_link_ops_X550em(hw); 1484282289Serj if (phy->sfp_type != ixgbe_sfp_type_unknown) 1485282289Serj phy->ops.reset = NULL; 1486282289Serj 1487282289Serj /* Set functions pointers based on phy type */ 1488282289Serj switch (hw->phy.type) { 1489282289Serj case ixgbe_phy_x550em_kx4: 1490292674Ssbruno phy->ops.setup_link = NULL; 1491282289Serj phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1492282289Serj phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1493282289Serj break; 1494282289Serj case ixgbe_phy_x550em_kr: 1495282289Serj phy->ops.setup_link = ixgbe_setup_kr_x550em; 1496282289Serj phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1497282289Serj phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1498282289Serj break; 1499282289Serj case ixgbe_phy_x550em_ext_t: 1500282289Serj /* Save NW management interface connected on board. This is used 1501282289Serj * to determine internal PHY mode 1502282289Serj */ 1503282289Serj phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1504282289Serj 1505282289Serj /* If internal link mode is XFI, then setup iXFI internal link, 1506282289Serj * else setup KR now. 1507282289Serj */ 1508282289Serj if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1509282289Serj phy->ops.setup_internal_link = 1510282289Serj ixgbe_setup_internal_phy_t_x550em; 1511282289Serj } else { 1512282289Serj speed = IXGBE_LINK_SPEED_10GB_FULL | 1513282289Serj IXGBE_LINK_SPEED_1GB_FULL; 1514282289Serj ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1515282289Serj } 1516282289Serj 1517292674Ssbruno /* setup SW LPLU only for first revision */ 1518292674Ssbruno if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, 1519292674Ssbruno IXGBE_FUSES0_GROUP(0)))) 1520292674Ssbruno phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 1521292674Ssbruno 1522282289Serj phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1523282289Serj phy->ops.reset = ixgbe_reset_phy_t_X550em; 1524282289Serj break; 1525282289Serj default: 1526282289Serj break; 1527282289Serj } 1528282289Serj return ret_val; 1529282289Serj} 1530282289Serj 1531282289Serj/** 1532282289Serj * ixgbe_reset_hw_X550em - Perform hardware reset 1533282289Serj * @hw: pointer to hardware structure 1534282289Serj * 1535282289Serj * Resets the hardware by resetting the transmit and receive units, masks 1536282289Serj * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1537282289Serj * reset. 1538282289Serj */ 1539282289Serjs32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1540282289Serj{ 1541282289Serj ixgbe_link_speed link_speed; 1542282289Serj s32 status; 1543282289Serj u32 ctrl = 0; 1544282289Serj u32 i; 1545282289Serj u32 hlreg0; 1546282289Serj bool link_up = FALSE; 1547282289Serj 1548282289Serj DEBUGFUNC("ixgbe_reset_hw_X550em"); 1549282289Serj 1550282289Serj /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1551282289Serj status = hw->mac.ops.stop_adapter(hw); 1552282289Serj if (status != IXGBE_SUCCESS) 1553282289Serj return status; 1554282289Serj 1555282289Serj /* flush pending Tx transactions */ 1556282289Serj ixgbe_clear_tx_pending(hw); 1557282289Serj 1558292674Ssbruno if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1559292674Ssbruno /* Config MDIO clock speed before the first MDIO PHY access */ 1560292674Ssbruno hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1561292674Ssbruno hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1562292674Ssbruno IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1563292674Ssbruno } 1564292674Ssbruno 1565282289Serj /* PHY ops must be identified and initialized prior to reset */ 1566282289Serj status = hw->phy.ops.init(hw); 1567282289Serj 1568282289Serj if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1569282289Serj return status; 1570282289Serj 1571282289Serj /* start the external PHY */ 1572282289Serj if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1573282289Serj status = ixgbe_init_ext_t_x550em(hw); 1574282289Serj if (status) 1575282289Serj return status; 1576282289Serj } 1577282289Serj 1578282289Serj /* Setup SFP module if there is one present. */ 1579282289Serj if (hw->phy.sfp_setup_needed) { 1580282289Serj status = hw->mac.ops.setup_sfp(hw); 1581282289Serj hw->phy.sfp_setup_needed = FALSE; 1582282289Serj } 1583282289Serj 1584282289Serj if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1585282289Serj return status; 1586282289Serj 1587282289Serj /* Reset PHY */ 1588282289Serj if (!hw->phy.reset_disable && hw->phy.ops.reset) 1589282289Serj hw->phy.ops.reset(hw); 1590282289Serj 1591282289Serjmac_reset_top: 1592282289Serj /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1593282289Serj * If link reset is used when link is up, it might reset the PHY when 1594282289Serj * mng is using it. If link is down or the flag to force full link 1595282289Serj * reset is set, then perform link reset. 1596282289Serj */ 1597282289Serj ctrl = IXGBE_CTRL_LNK_RST; 1598282289Serj if (!hw->force_full_reset) { 1599282289Serj hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1600282289Serj if (link_up) 1601282289Serj ctrl = IXGBE_CTRL_RST; 1602282289Serj } 1603282289Serj 1604282289Serj ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1605282289Serj IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1606282289Serj IXGBE_WRITE_FLUSH(hw); 1607282289Serj 1608282289Serj /* Poll for reset bit to self-clear meaning reset is complete */ 1609282289Serj for (i = 0; i < 10; i++) { 1610282289Serj usec_delay(1); 1611282289Serj ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1612282289Serj if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1613282289Serj break; 1614282289Serj } 1615282289Serj 1616282289Serj if (ctrl & IXGBE_CTRL_RST_MASK) { 1617282289Serj status = IXGBE_ERR_RESET_FAILED; 1618282289Serj DEBUGOUT("Reset polling failed to complete.\n"); 1619282289Serj } 1620282289Serj 1621282289Serj msec_delay(50); 1622282289Serj 1623282289Serj /* Double resets are required for recovery from certain error 1624282289Serj * conditions. Between resets, it is necessary to stall to 1625282289Serj * allow time for any pending HW events to complete. 1626282289Serj */ 1627282289Serj if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1628282289Serj hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1629282289Serj goto mac_reset_top; 1630282289Serj } 1631282289Serj 1632282289Serj /* Store the permanent mac address */ 1633282289Serj hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1634282289Serj 1635282289Serj /* Store MAC address from RAR0, clear receive address registers, and 1636282289Serj * clear the multicast table. Also reset num_rar_entries to 128, 1637282289Serj * since we modify this value when programming the SAN MAC address. 1638282289Serj */ 1639282289Serj hw->mac.num_rar_entries = 128; 1640282289Serj hw->mac.ops.init_rx_addrs(hw); 1641282289Serj 1642282289Serj if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1643282289Serj ixgbe_setup_mux_ctl(hw); 1644282289Serj 1645282289Serj return status; 1646282289Serj} 1647282289Serj 1648282289Serj/** 1649282289Serj * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1650282289Serj * @hw: pointer to hardware structure 1651282289Serj */ 1652282289Serjs32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1653282289Serj{ 1654282289Serj u32 status; 1655282289Serj u16 reg; 1656282289Serj 1657282289Serj status = hw->phy.ops.read_reg(hw, 1658282289Serj IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1659282289Serj IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1660282289Serj ®); 1661282289Serj 1662282289Serj if (status != IXGBE_SUCCESS) 1663282289Serj return status; 1664282289Serj 1665282289Serj /* If PHY FW reset completed bit is set then this is the first 1666282289Serj * SW instance after a power on so the PHY FW must be un-stalled. 1667282289Serj */ 1668282289Serj if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1669282289Serj status = hw->phy.ops.read_reg(hw, 1670282289Serj IXGBE_MDIO_GLOBAL_RES_PR_10, 1671282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1672282289Serj ®); 1673282289Serj 1674282289Serj if (status != IXGBE_SUCCESS) 1675282289Serj return status; 1676282289Serj 1677282289Serj reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1678282289Serj 1679282289Serj status = hw->phy.ops.write_reg(hw, 1680282289Serj IXGBE_MDIO_GLOBAL_RES_PR_10, 1681282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1682282289Serj reg); 1683282289Serj 1684282289Serj if (status != IXGBE_SUCCESS) 1685282289Serj return status; 1686282289Serj } 1687282289Serj 1688282289Serj return status; 1689282289Serj} 1690282289Serj 1691282289Serj/** 1692282289Serj * ixgbe_setup_kr_x550em - Configure the KR PHY. 1693282289Serj * @hw: pointer to hardware structure 1694282289Serj * 1695282289Serj * Configures the integrated KR PHY. 1696282289Serj **/ 1697282289Serjs32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1698282289Serj{ 1699282289Serj return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1700282289Serj} 1701282289Serj 1702282289Serj/** 1703282289Serj * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 1704282289Serj * @hw: pointer to hardware structure 1705282289Serj * 1706282289Serj * Configure the external PHY and the integrated KR PHY for SFP support. 1707282289Serj **/ 1708282289Serjs32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1709282289Serj ixgbe_link_speed speed, 1710282289Serj bool autoneg_wait_to_complete) 1711282289Serj{ 1712282289Serj s32 ret_val; 1713282289Serj u16 reg_slice, reg_val; 1714282289Serj bool setup_linear = FALSE; 1715282289Serj UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 1716282289Serj 1717282289Serj /* Check if SFP module is supported and linear */ 1718282289Serj ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1719282289Serj 1720282289Serj /* If no SFP module present, then return success. Return success since 1721282289Serj * there is no reason to configure CS4227 and SFP not present error is 1722282289Serj * not excepted in the setup MAC link flow. 1723282289Serj */ 1724282289Serj if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1725282289Serj return IXGBE_SUCCESS; 1726282289Serj 1727282289Serj if (ret_val != IXGBE_SUCCESS) 1728282289Serj return ret_val; 1729282289Serj 1730292674Ssbruno if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1731292674Ssbruno /* Configure CS4227 LINE side to 10G SR. */ 1732292674Ssbruno reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + 1733292674Ssbruno (hw->bus.lan_id << 12); 1734292674Ssbruno reg_val = IXGBE_CS4227_SPEED_10G; 1735292674Ssbruno ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1736292674Ssbruno reg_val); 1737282289Serj 1738292674Ssbruno reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 1739292674Ssbruno (hw->bus.lan_id << 12); 1740282289Serj reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1741292674Ssbruno ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1742292674Ssbruno reg_val); 1743282289Serj 1744292674Ssbruno /* Configure CS4227 for HOST connection rate then type. */ 1745292674Ssbruno reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + 1746292674Ssbruno (hw->bus.lan_id << 12); 1747292674Ssbruno reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 1748292674Ssbruno IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G; 1749292674Ssbruno ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1750292674Ssbruno reg_val); 1751282289Serj 1752292674Ssbruno reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + 1753292674Ssbruno (hw->bus.lan_id << 12); 1754292674Ssbruno if (setup_linear) 1755292674Ssbruno reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1756292674Ssbruno else 1757292674Ssbruno reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1758292674Ssbruno ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1759292674Ssbruno reg_val); 1760282289Serj 1761292674Ssbruno /* Setup XFI internal link. */ 1762282289Serj ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); 1763292674Ssbruno } else { 1764292674Ssbruno /* Configure internal PHY for KR/KX. */ 1765292674Ssbruno ixgbe_setup_kr_speed_x550em(hw, speed); 1766282289Serj 1767292674Ssbruno /* Configure CS4227 LINE side to proper mode. */ 1768292674Ssbruno reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + 1769292674Ssbruno (hw->bus.lan_id << 12); 1770292674Ssbruno if (setup_linear) 1771292674Ssbruno reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1772292674Ssbruno else 1773292674Ssbruno reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1774292674Ssbruno ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1775292674Ssbruno reg_val); 1776292674Ssbruno } 1777282289Serj return ret_val; 1778282289Serj} 1779282289Serj 1780282289Serj/** 1781282289Serj * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1782282289Serj * @hw: pointer to hardware structure 1783282289Serj * @speed: the link speed to force 1784282289Serj * 1785282289Serj * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1786282289Serj * internal and external PHY at a specific speed, without autonegotiation. 1787282289Serj **/ 1788282289Serjstatic s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1789282289Serj{ 1790282289Serj s32 status; 1791282289Serj u32 reg_val; 1792282289Serj 1793282289Serj /* Disable AN and force speed to 10G Serial. */ 1794282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1795282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1796282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1797282289Serj if (status != IXGBE_SUCCESS) 1798282289Serj return status; 1799282289Serj 1800282289Serj reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1801282289Serj reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1802282289Serj 1803282289Serj /* Select forced link speed for internal PHY. */ 1804282289Serj switch (*speed) { 1805282289Serj case IXGBE_LINK_SPEED_10GB_FULL: 1806282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1807282289Serj break; 1808282289Serj case IXGBE_LINK_SPEED_1GB_FULL: 1809282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1810282289Serj break; 1811282289Serj default: 1812282289Serj /* Other link speeds are not supported by internal KR PHY. */ 1813282289Serj return IXGBE_ERR_LINK_SETUP; 1814282289Serj } 1815282289Serj 1816282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1817282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1818282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1819282289Serj if (status != IXGBE_SUCCESS) 1820282289Serj return status; 1821282289Serj 1822282289Serj /* Disable training protocol FSM. */ 1823282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1824282289Serj IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1825282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1826282289Serj if (status != IXGBE_SUCCESS) 1827282289Serj return status; 1828282289Serj reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1829282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1830282289Serj IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1831282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1832282289Serj if (status != IXGBE_SUCCESS) 1833282289Serj return status; 1834282289Serj 1835282289Serj /* Disable Flex from training TXFFE. */ 1836282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1837282289Serj IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1838282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1839282289Serj if (status != IXGBE_SUCCESS) 1840282289Serj return status; 1841282289Serj reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1842282289Serj reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1843282289Serj reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1844282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1845282289Serj IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1846282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1847282289Serj if (status != IXGBE_SUCCESS) 1848282289Serj return status; 1849282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1850282289Serj IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1851282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1852282289Serj if (status != IXGBE_SUCCESS) 1853282289Serj return status; 1854282289Serj reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1855282289Serj reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1856282289Serj reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1857282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1858282289Serj IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1859282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1860282289Serj if (status != IXGBE_SUCCESS) 1861282289Serj return status; 1862282289Serj 1863282289Serj /* Enable override for coefficients. */ 1864282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1865282289Serj IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1866282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1867282289Serj if (status != IXGBE_SUCCESS) 1868282289Serj return status; 1869282289Serj reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1870282289Serj reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1871282289Serj reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1872282289Serj reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1873282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1874282289Serj IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1875282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1876282289Serj if (status != IXGBE_SUCCESS) 1877282289Serj return status; 1878282289Serj 1879282289Serj /* Toggle port SW reset by AN reset. */ 1880282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1881282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1882282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1883282289Serj if (status != IXGBE_SUCCESS) 1884282289Serj return status; 1885282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1886282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 1887282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1888282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1889282289Serj 1890282289Serj return status; 1891282289Serj} 1892282289Serj 1893282289Serj/** 1894282289Serj * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 1895282289Serj * @hw: address of hardware structure 1896282289Serj * @link_up: address of boolean to indicate link status 1897282289Serj * 1898282289Serj * Returns error code if unable to get link status. 1899282289Serj */ 1900282289Serjstatic s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 1901282289Serj{ 1902282289Serj u32 ret; 1903282289Serj u16 autoneg_status; 1904282289Serj 1905282289Serj *link_up = FALSE; 1906282289Serj 1907282289Serj /* read this twice back to back to indicate current status */ 1908282289Serj ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1909282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1910282289Serj &autoneg_status); 1911282289Serj if (ret != IXGBE_SUCCESS) 1912282289Serj return ret; 1913282289Serj 1914282289Serj ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1915282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1916282289Serj &autoneg_status); 1917282289Serj if (ret != IXGBE_SUCCESS) 1918282289Serj return ret; 1919282289Serj 1920282289Serj *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 1921282289Serj 1922282289Serj return IXGBE_SUCCESS; 1923282289Serj} 1924282289Serj 1925282289Serj/** 1926282289Serj * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1927282289Serj * @hw: point to hardware structure 1928282289Serj * 1929282289Serj * Configures the link between the integrated KR PHY and the external X557 PHY 1930282289Serj * The driver will call this function when it gets a link status change 1931282289Serj * interrupt from the X557 PHY. This function configures the link speed 1932282289Serj * between the PHYs to match the link speed of the BASE-T link. 1933282289Serj * 1934282289Serj * A return of a non-zero value indicates an error, and the base driver should 1935282289Serj * not report link up. 1936282289Serj */ 1937282289Serjs32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1938282289Serj{ 1939282289Serj ixgbe_link_speed force_speed; 1940282289Serj bool link_up; 1941282289Serj u32 status; 1942282289Serj u16 speed; 1943282289Serj 1944282289Serj if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1945282289Serj return IXGBE_ERR_CONFIG; 1946282289Serj 1947282289Serj /* If link is not up, then there is no setup necessary so return */ 1948282289Serj status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1949282289Serj if (status != IXGBE_SUCCESS) 1950282289Serj return status; 1951282289Serj 1952282289Serj if (!link_up) 1953282289Serj return IXGBE_SUCCESS; 1954282289Serj 1955282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1956282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1957282289Serj &speed); 1958282289Serj if (status != IXGBE_SUCCESS) 1959282289Serj return status; 1960282289Serj 1961282289Serj /* If link is not still up, then no setup is necessary so return */ 1962282289Serj status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1963282289Serj if (status != IXGBE_SUCCESS) 1964282289Serj return status; 1965282289Serj if (!link_up) 1966282289Serj return IXGBE_SUCCESS; 1967282289Serj 1968282289Serj /* clear everything but the speed and duplex bits */ 1969282289Serj speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1970282289Serj 1971282289Serj switch (speed) { 1972282289Serj case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1973282289Serj force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1974282289Serj break; 1975282289Serj case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1976282289Serj force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1977282289Serj break; 1978282289Serj default: 1979282289Serj /* Internal PHY does not support anything else */ 1980282289Serj return IXGBE_ERR_INVALID_LINK_SETTINGS; 1981282289Serj } 1982282289Serj 1983282289Serj return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1984282289Serj} 1985282289Serj 1986282289Serj/** 1987282289Serj * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 1988282289Serj * @hw: pointer to hardware structure 1989282289Serj * 1990282289Serj * Configures the integrated KR PHY to use internal loopback mode. 1991282289Serj **/ 1992282289Serjs32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 1993282289Serj{ 1994282289Serj s32 status; 1995282289Serj u32 reg_val; 1996282289Serj 1997282289Serj /* Disable AN and force speed to 10G Serial. */ 1998282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 1999282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2000282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2001282289Serj if (status != IXGBE_SUCCESS) 2002282289Serj return status; 2003282289Serj reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2004282289Serj reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2005282289Serj reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 2006282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 2007282289Serj IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2008282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2009282289Serj if (status != IXGBE_SUCCESS) 2010282289Serj return status; 2011282289Serj 2012282289Serj /* Set near-end loopback clocks. */ 2013282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 2014282289Serj IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2015282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2016282289Serj if (status != IXGBE_SUCCESS) 2017282289Serj return status; 2018282289Serj reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 2019282289Serj reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 2020282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 2021282289Serj IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2022282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2023282289Serj if (status != IXGBE_SUCCESS) 2024282289Serj return status; 2025282289Serj 2026282289Serj /* Set loopback enable. */ 2027282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 2028282289Serj IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2029282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2030282289Serj if (status != IXGBE_SUCCESS) 2031282289Serj return status; 2032282289Serj reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 2033282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 2034282289Serj IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2035282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2036282289Serj if (status != IXGBE_SUCCESS) 2037282289Serj return status; 2038282289Serj 2039282289Serj /* Training bypass. */ 2040282289Serj status = ixgbe_read_iosf_sb_reg_x550(hw, 2041282289Serj IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2042282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2043282289Serj if (status != IXGBE_SUCCESS) 2044282289Serj return status; 2045282289Serj reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 2046282289Serj status = ixgbe_write_iosf_sb_reg_x550(hw, 2047282289Serj IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2048282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2049282289Serj 2050282289Serj return status; 2051282289Serj} 2052282289Serj 2053282289Serj/** 2054282289Serj * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2055282289Serj * assuming that the semaphore is already obtained. 2056282289Serj * @hw: pointer to hardware structure 2057282289Serj * @offset: offset of word in the EEPROM to read 2058282289Serj * @data: word read from the EEPROM 2059282289Serj * 2060282289Serj * Reads a 16 bit word from the EEPROM using the hostif. 2061282289Serj **/ 2062282289Serjs32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2063282289Serj u16 *data) 2064282289Serj{ 2065282289Serj s32 status; 2066282289Serj struct ixgbe_hic_read_shadow_ram buffer; 2067282289Serj 2068282289Serj DEBUGFUNC("ixgbe_read_ee_hostif_data_X550"); 2069282289Serj buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2070282289Serj buffer.hdr.req.buf_lenh = 0; 2071282289Serj buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2072282289Serj buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2073282289Serj 2074282289Serj /* convert offset from words to bytes */ 2075282289Serj buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2076282289Serj /* one word */ 2077282289Serj buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2078282289Serj 2079282289Serj status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2080282289Serj sizeof(buffer), 2081282289Serj IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2082282289Serj 2083282289Serj if (status) 2084282289Serj return status; 2085282289Serj 2086282289Serj *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 2087282289Serj FW_NVM_DATA_OFFSET); 2088282289Serj 2089282289Serj return 0; 2090282289Serj} 2091282289Serj 2092282289Serj/** 2093282289Serj * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2094282289Serj * @hw: pointer to hardware structure 2095282289Serj * @offset: offset of word in the EEPROM to read 2096282289Serj * @data: word read from the EEPROM 2097282289Serj * 2098282289Serj * Reads a 16 bit word from the EEPROM using the hostif. 2099282289Serj **/ 2100282289Serjs32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2101282289Serj u16 *data) 2102282289Serj{ 2103282289Serj s32 status = IXGBE_SUCCESS; 2104282289Serj 2105282289Serj DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 2106282289Serj 2107282289Serj if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2108282289Serj IXGBE_SUCCESS) { 2109282289Serj status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 2110282289Serj hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2111282289Serj } else { 2112282289Serj status = IXGBE_ERR_SWFW_SYNC; 2113282289Serj } 2114282289Serj 2115282289Serj return status; 2116282289Serj} 2117282289Serj 2118282289Serj/** 2119282289Serj * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 2120282289Serj * @hw: pointer to hardware structure 2121282289Serj * @offset: offset of word in the EEPROM to read 2122282289Serj * @words: number of words 2123282289Serj * @data: word(s) read from the EEPROM 2124282289Serj * 2125282289Serj * Reads a 16 bit word(s) from the EEPROM using the hostif. 2126282289Serj **/ 2127282289Serjs32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2128282289Serj u16 offset, u16 words, u16 *data) 2129282289Serj{ 2130282289Serj struct ixgbe_hic_read_shadow_ram buffer; 2131282289Serj u32 current_word = 0; 2132282289Serj u16 words_to_read; 2133282289Serj s32 status; 2134282289Serj u32 i; 2135282289Serj 2136282289Serj DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 2137282289Serj 2138282289Serj /* Take semaphore for the entire operation. */ 2139282289Serj status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2140282289Serj if (status) { 2141282289Serj DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 2142282289Serj return status; 2143282289Serj } 2144282289Serj while (words) { 2145282289Serj if (words > FW_MAX_READ_BUFFER_SIZE / 2) 2146282289Serj words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 2147282289Serj else 2148282289Serj words_to_read = words; 2149282289Serj 2150282289Serj buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2151282289Serj buffer.hdr.req.buf_lenh = 0; 2152282289Serj buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2153282289Serj buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2154282289Serj 2155282289Serj /* convert offset from words to bytes */ 2156282289Serj buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 2157282289Serj buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 2158282289Serj 2159282289Serj status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2160282289Serj sizeof(buffer), 2161282289Serj IXGBE_HI_COMMAND_TIMEOUT, 2162282289Serj FALSE); 2163282289Serj 2164282289Serj if (status) { 2165282289Serj DEBUGOUT("Host interface command failed\n"); 2166282289Serj goto out; 2167282289Serj } 2168282289Serj 2169282289Serj for (i = 0; i < words_to_read; i++) { 2170282289Serj u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 2171282289Serj 2 * i; 2172282289Serj u32 value = IXGBE_READ_REG(hw, reg); 2173282289Serj 2174282289Serj data[current_word] = (u16)(value & 0xffff); 2175282289Serj current_word++; 2176282289Serj i++; 2177282289Serj if (i < words_to_read) { 2178282289Serj value >>= 16; 2179282289Serj data[current_word] = (u16)(value & 0xffff); 2180282289Serj current_word++; 2181282289Serj } 2182282289Serj } 2183282289Serj words -= words_to_read; 2184282289Serj } 2185282289Serj 2186282289Serjout: 2187282289Serj hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2188282289Serj return status; 2189282289Serj} 2190282289Serj 2191282289Serj/** 2192282289Serj * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2193282289Serj * @hw: pointer to hardware structure 2194282289Serj * @offset: offset of word in the EEPROM to write 2195282289Serj * @data: word write to the EEPROM 2196282289Serj * 2197282289Serj * Write a 16 bit word to the EEPROM using the hostif. 2198282289Serj **/ 2199282289Serjs32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2200282289Serj u16 data) 2201282289Serj{ 2202282289Serj s32 status; 2203282289Serj struct ixgbe_hic_write_shadow_ram buffer; 2204282289Serj 2205282289Serj DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 2206282289Serj 2207282289Serj buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 2208282289Serj buffer.hdr.req.buf_lenh = 0; 2209282289Serj buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 2210282289Serj buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2211282289Serj 2212282289Serj /* one word */ 2213282289Serj buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2214282289Serj buffer.data = data; 2215282289Serj buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2216282289Serj 2217282289Serj status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2218282289Serj sizeof(buffer), 2219282289Serj IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2220282289Serj 2221282289Serj return status; 2222282289Serj} 2223282289Serj 2224282289Serj/** 2225282289Serj * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2226282289Serj * @hw: pointer to hardware structure 2227282289Serj * @offset: offset of word in the EEPROM to write 2228282289Serj * @data: word write to the EEPROM 2229282289Serj * 2230282289Serj * Write a 16 bit word to the EEPROM using the hostif. 2231282289Serj **/ 2232282289Serjs32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2233282289Serj u16 data) 2234282289Serj{ 2235282289Serj s32 status = IXGBE_SUCCESS; 2236282289Serj 2237282289Serj DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 2238282289Serj 2239282289Serj if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2240282289Serj IXGBE_SUCCESS) { 2241282289Serj status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 2242282289Serj hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2243282289Serj } else { 2244282289Serj DEBUGOUT("write ee hostif failed to get semaphore"); 2245282289Serj status = IXGBE_ERR_SWFW_SYNC; 2246282289Serj } 2247282289Serj 2248282289Serj return status; 2249282289Serj} 2250282289Serj 2251282289Serj/** 2252282289Serj * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 2253282289Serj * @hw: pointer to hardware structure 2254282289Serj * @offset: offset of word in the EEPROM to write 2255282289Serj * @words: number of words 2256282289Serj * @data: word(s) write to the EEPROM 2257282289Serj * 2258282289Serj * Write a 16 bit word(s) to the EEPROM using the hostif. 2259282289Serj **/ 2260282289Serjs32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2261282289Serj u16 offset, u16 words, u16 *data) 2262282289Serj{ 2263282289Serj s32 status = IXGBE_SUCCESS; 2264282289Serj u32 i = 0; 2265282289Serj 2266282289Serj DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 2267282289Serj 2268282289Serj /* Take semaphore for the entire operation. */ 2269282289Serj status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2270282289Serj if (status != IXGBE_SUCCESS) { 2271282289Serj DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 2272282289Serj goto out; 2273282289Serj } 2274282289Serj 2275282289Serj for (i = 0; i < words; i++) { 2276282289Serj status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 2277282289Serj data[i]); 2278282289Serj 2279282289Serj if (status != IXGBE_SUCCESS) { 2280282289Serj DEBUGOUT("Eeprom buffered write failed\n"); 2281282289Serj break; 2282282289Serj } 2283282289Serj } 2284282289Serj 2285282289Serj hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2286282289Serjout: 2287282289Serj 2288282289Serj return status; 2289282289Serj} 2290282289Serj 2291282289Serj/** 2292282289Serj * ixgbe_checksum_ptr_x550 - Checksum one pointer region 2293282289Serj * @hw: pointer to hardware structure 2294282289Serj * @ptr: pointer offset in eeprom 2295282289Serj * @size: size of section pointed by ptr, if 0 first word will be used as size 2296282289Serj * @csum: address of checksum to update 2297282289Serj * 2298282289Serj * Returns error status for any failure 2299282289Serj */ 2300282289Serjstatic s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 2301282289Serj u16 size, u16 *csum, u16 *buffer, 2302282289Serj u32 buffer_size) 2303282289Serj{ 2304282289Serj u16 buf[256]; 2305282289Serj s32 status; 2306282289Serj u16 length, bufsz, i, start; 2307282289Serj u16 *local_buffer; 2308282289Serj 2309282289Serj bufsz = sizeof(buf) / sizeof(buf[0]); 2310282289Serj 2311282289Serj /* Read a chunk at the pointer location */ 2312282289Serj if (!buffer) { 2313282289Serj status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 2314282289Serj if (status) { 2315282289Serj DEBUGOUT("Failed to read EEPROM image\n"); 2316282289Serj return status; 2317282289Serj } 2318282289Serj local_buffer = buf; 2319282289Serj } else { 2320282289Serj if (buffer_size < ptr) 2321282289Serj return IXGBE_ERR_PARAM; 2322282289Serj local_buffer = &buffer[ptr]; 2323282289Serj } 2324282289Serj 2325282289Serj if (size) { 2326282289Serj start = 0; 2327282289Serj length = size; 2328282289Serj } else { 2329282289Serj start = 1; 2330282289Serj length = local_buffer[0]; 2331282289Serj 2332282289Serj /* Skip pointer section if length is invalid. */ 2333282289Serj if (length == 0xFFFF || length == 0 || 2334282289Serj (ptr + length) >= hw->eeprom.word_size) 2335282289Serj return IXGBE_SUCCESS; 2336282289Serj } 2337282289Serj 2338282289Serj if (buffer && ((u32)start + (u32)length > buffer_size)) 2339282289Serj return IXGBE_ERR_PARAM; 2340282289Serj 2341282289Serj for (i = start; length; i++, length--) { 2342282289Serj if (i == bufsz && !buffer) { 2343282289Serj ptr += bufsz; 2344282289Serj i = 0; 2345282289Serj if (length < bufsz) 2346282289Serj bufsz = length; 2347282289Serj 2348282289Serj /* Read a chunk at the pointer location */ 2349282289Serj status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 2350282289Serj bufsz, buf); 2351282289Serj if (status) { 2352282289Serj DEBUGOUT("Failed to read EEPROM image\n"); 2353282289Serj return status; 2354282289Serj } 2355282289Serj } 2356282289Serj *csum += local_buffer[i]; 2357282289Serj } 2358282289Serj return IXGBE_SUCCESS; 2359282289Serj} 2360282289Serj 2361282289Serj/** 2362282289Serj * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 2363282289Serj * @hw: pointer to hardware structure 2364282289Serj * @buffer: pointer to buffer containing calculated checksum 2365282289Serj * @buffer_size: size of buffer 2366282289Serj * 2367282289Serj * Returns a negative error code on error, or the 16-bit checksum 2368282289Serj **/ 2369282289Serjs32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 2370282289Serj{ 2371282289Serj u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 2372282289Serj u16 *local_buffer; 2373282289Serj s32 status; 2374282289Serj u16 checksum = 0; 2375282289Serj u16 pointer, i, size; 2376282289Serj 2377282289Serj DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 2378282289Serj 2379282289Serj hw->eeprom.ops.init_params(hw); 2380282289Serj 2381282289Serj if (!buffer) { 2382282289Serj /* Read pointer area */ 2383282289Serj status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 2384282289Serj IXGBE_EEPROM_LAST_WORD + 1, 2385282289Serj eeprom_ptrs); 2386282289Serj if (status) { 2387282289Serj DEBUGOUT("Failed to read EEPROM image\n"); 2388282289Serj return status; 2389282289Serj } 2390282289Serj local_buffer = eeprom_ptrs; 2391282289Serj } else { 2392282289Serj if (buffer_size < IXGBE_EEPROM_LAST_WORD) 2393282289Serj return IXGBE_ERR_PARAM; 2394282289Serj local_buffer = buffer; 2395282289Serj } 2396282289Serj 2397282289Serj /* 2398282289Serj * For X550 hardware include 0x0-0x41 in the checksum, skip the 2399282289Serj * checksum word itself 2400282289Serj */ 2401282289Serj for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 2402282289Serj if (i != IXGBE_EEPROM_CHECKSUM) 2403282289Serj checksum += local_buffer[i]; 2404282289Serj 2405282289Serj /* 2406282289Serj * Include all data from pointers 0x3, 0x6-0xE. This excludes the 2407282289Serj * FW, PHY module, and PCIe Expansion/Option ROM pointers. 2408282289Serj */ 2409282289Serj for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 2410282289Serj if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 2411282289Serj continue; 2412282289Serj 2413282289Serj pointer = local_buffer[i]; 2414282289Serj 2415282289Serj /* Skip pointer section if the pointer is invalid. */ 2416282289Serj if (pointer == 0xFFFF || pointer == 0 || 2417282289Serj pointer >= hw->eeprom.word_size) 2418282289Serj continue; 2419282289Serj 2420282289Serj switch (i) { 2421282289Serj case IXGBE_PCIE_GENERAL_PTR: 2422282289Serj size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 2423282289Serj break; 2424282289Serj case IXGBE_PCIE_CONFIG0_PTR: 2425282289Serj case IXGBE_PCIE_CONFIG1_PTR: 2426282289Serj size = IXGBE_PCIE_CONFIG_SIZE; 2427282289Serj break; 2428282289Serj default: 2429282289Serj size = 0; 2430282289Serj break; 2431282289Serj } 2432282289Serj 2433282289Serj status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 2434282289Serj buffer, buffer_size); 2435282289Serj if (status) 2436282289Serj return status; 2437282289Serj } 2438282289Serj 2439282289Serj checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2440282289Serj 2441282289Serj return (s32)checksum; 2442282289Serj} 2443282289Serj 2444282289Serj/** 2445282289Serj * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 2446282289Serj * @hw: pointer to hardware structure 2447282289Serj * 2448282289Serj * Returns a negative error code on error, or the 16-bit checksum 2449282289Serj **/ 2450282289Serjs32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 2451282289Serj{ 2452282289Serj return ixgbe_calc_checksum_X550(hw, NULL, 0); 2453282289Serj} 2454282289Serj 2455282289Serj/** 2456282289Serj * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 2457282289Serj * @hw: pointer to hardware structure 2458282289Serj * @checksum_val: calculated checksum 2459282289Serj * 2460282289Serj * Performs checksum calculation and validates the EEPROM checksum. If the 2461282289Serj * caller does not need checksum_val, the value can be NULL. 2462282289Serj **/ 2463282289Serjs32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 2464282289Serj{ 2465282289Serj s32 status; 2466282289Serj u16 checksum; 2467282289Serj u16 read_checksum = 0; 2468282289Serj 2469282289Serj DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 2470282289Serj 2471282289Serj /* Read the first word from the EEPROM. If this times out or fails, do 2472282289Serj * not continue or we could be in for a very long wait while every 2473282289Serj * EEPROM read fails 2474282289Serj */ 2475282289Serj status = hw->eeprom.ops.read(hw, 0, &checksum); 2476282289Serj if (status) { 2477282289Serj DEBUGOUT("EEPROM read failed\n"); 2478282289Serj return status; 2479282289Serj } 2480282289Serj 2481282289Serj status = hw->eeprom.ops.calc_checksum(hw); 2482282289Serj if (status < 0) 2483282289Serj return status; 2484282289Serj 2485282289Serj checksum = (u16)(status & 0xffff); 2486282289Serj 2487282289Serj status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2488282289Serj &read_checksum); 2489282289Serj if (status) 2490282289Serj return status; 2491282289Serj 2492282289Serj /* Verify read checksum from EEPROM is the same as 2493282289Serj * calculated checksum 2494282289Serj */ 2495282289Serj if (read_checksum != checksum) { 2496282289Serj status = IXGBE_ERR_EEPROM_CHECKSUM; 2497282289Serj ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 2498282289Serj "Invalid EEPROM checksum"); 2499282289Serj } 2500282289Serj 2501282289Serj /* If the user cares, return the calculated checksum */ 2502282289Serj if (checksum_val) 2503282289Serj *checksum_val = checksum; 2504282289Serj 2505282289Serj return status; 2506282289Serj} 2507282289Serj 2508282289Serj/** 2509282289Serj * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 2510282289Serj * @hw: pointer to hardware structure 2511282289Serj * 2512282289Serj * After writing EEPROM to shadow RAM using EEWR register, software calculates 2513282289Serj * checksum and updates the EEPROM and instructs the hardware to update 2514282289Serj * the flash. 2515282289Serj **/ 2516282289Serjs32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 2517282289Serj{ 2518282289Serj s32 status; 2519282289Serj u16 checksum = 0; 2520282289Serj 2521282289Serj DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 2522282289Serj 2523282289Serj /* Read the first word from the EEPROM. If this times out or fails, do 2524282289Serj * not continue or we could be in for a very long wait while every 2525282289Serj * EEPROM read fails 2526282289Serj */ 2527282289Serj status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 2528282289Serj if (status) { 2529282289Serj DEBUGOUT("EEPROM read failed\n"); 2530282289Serj return status; 2531282289Serj } 2532282289Serj 2533282289Serj status = ixgbe_calc_eeprom_checksum_X550(hw); 2534282289Serj if (status < 0) 2535282289Serj return status; 2536282289Serj 2537282289Serj checksum = (u16)(status & 0xffff); 2538282289Serj 2539282289Serj status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2540282289Serj checksum); 2541282289Serj if (status) 2542282289Serj return status; 2543282289Serj 2544282289Serj status = ixgbe_update_flash_X550(hw); 2545282289Serj 2546282289Serj return status; 2547282289Serj} 2548282289Serj 2549282289Serj/** 2550282289Serj * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 2551282289Serj * @hw: pointer to hardware structure 2552282289Serj * 2553282289Serj * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 2554282289Serj **/ 2555282289Serjs32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 2556282289Serj{ 2557282289Serj s32 status = IXGBE_SUCCESS; 2558282289Serj union ixgbe_hic_hdr2 buffer; 2559282289Serj 2560282289Serj DEBUGFUNC("ixgbe_update_flash_X550"); 2561282289Serj 2562282289Serj buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 2563282289Serj buffer.req.buf_lenh = 0; 2564282289Serj buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 2565282289Serj buffer.req.checksum = FW_DEFAULT_CHECKSUM; 2566282289Serj 2567282289Serj status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2568282289Serj sizeof(buffer), 2569282289Serj IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2570282289Serj 2571282289Serj return status; 2572282289Serj} 2573282289Serj 2574282289Serj/** 2575282289Serj * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 2576282289Serj * @hw: pointer to hardware structure 2577282289Serj * 2578282289Serj * Determines physical layer capabilities of the current configuration. 2579282289Serj **/ 2580282289Serju32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 2581282289Serj{ 2582282289Serj u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2583282289Serj u16 ext_ability = 0; 2584282289Serj 2585282289Serj DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 2586282289Serj 2587282289Serj hw->phy.ops.identify(hw); 2588282289Serj 2589282289Serj switch (hw->phy.type) { 2590282289Serj case ixgbe_phy_x550em_kr: 2591282289Serj physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 2592282289Serj IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2593282289Serj break; 2594282289Serj case ixgbe_phy_x550em_kx4: 2595282289Serj physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2596282289Serj IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2597282289Serj break; 2598282289Serj case ixgbe_phy_x550em_ext_t: 2599282289Serj hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2600282289Serj IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2601282289Serj &ext_ability); 2602282289Serj if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2603282289Serj physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2604282289Serj if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2605282289Serj physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2606282289Serj break; 2607282289Serj default: 2608282289Serj break; 2609282289Serj } 2610282289Serj 2611282289Serj if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 2612282289Serj physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2613282289Serj 2614282289Serj return physical_layer; 2615282289Serj} 2616282289Serj 2617282289Serj/** 2618282289Serj * ixgbe_get_bus_info_x550em - Set PCI bus info 2619282289Serj * @hw: pointer to hardware structure 2620282289Serj * 2621282289Serj * Sets bus link width and speed to unknown because X550em is 2622282289Serj * not a PCI device. 2623282289Serj **/ 2624282289Serjs32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 2625282289Serj{ 2626282289Serj 2627282289Serj DEBUGFUNC("ixgbe_get_bus_info_x550em"); 2628282289Serj 2629282289Serj hw->bus.width = ixgbe_bus_width_unknown; 2630282289Serj hw->bus.speed = ixgbe_bus_speed_unknown; 2631282289Serj 2632282289Serj hw->mac.ops.set_lan_id(hw); 2633282289Serj 2634282289Serj return IXGBE_SUCCESS; 2635282289Serj} 2636282289Serj 2637282289Serj/** 2638282289Serj * ixgbe_disable_rx_x550 - Disable RX unit 2639282289Serj * 2640282289Serj * Enables the Rx DMA unit for x550 2641282289Serj **/ 2642282289Serjvoid ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 2643282289Serj{ 2644282289Serj u32 rxctrl, pfdtxgswc; 2645282289Serj s32 status; 2646282289Serj struct ixgbe_hic_disable_rxen fw_cmd; 2647282289Serj 2648282289Serj DEBUGFUNC("ixgbe_enable_rx_dma_x550"); 2649282289Serj 2650282289Serj rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2651282289Serj if (rxctrl & IXGBE_RXCTRL_RXEN) { 2652282289Serj pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 2653282289Serj if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 2654282289Serj pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 2655282289Serj IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 2656282289Serj hw->mac.set_lben = TRUE; 2657282289Serj } else { 2658282289Serj hw->mac.set_lben = FALSE; 2659282289Serj } 2660282289Serj 2661282289Serj fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 2662282289Serj fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 2663282289Serj fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 2664282289Serj fw_cmd.port_number = (u8)hw->bus.lan_id; 2665282289Serj 2666282289Serj status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2667282289Serj sizeof(struct ixgbe_hic_disable_rxen), 2668282289Serj IXGBE_HI_COMMAND_TIMEOUT, TRUE); 2669282289Serj 2670282289Serj /* If we fail - disable RX using register write */ 2671282289Serj if (status) { 2672282289Serj rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2673282289Serj if (rxctrl & IXGBE_RXCTRL_RXEN) { 2674282289Serj rxctrl &= ~IXGBE_RXCTRL_RXEN; 2675282289Serj IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 2676282289Serj } 2677282289Serj } 2678282289Serj } 2679282289Serj} 2680282289Serj 2681282289Serj/** 2682282289Serj * ixgbe_enter_lplu_x550em - Transition to low power states 2683282289Serj * @hw: pointer to hardware structure 2684282289Serj * 2685282289Serj * Configures Low Power Link Up on transition to low power states 2686282289Serj * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2687282289Serj * X557 PHY immediately prior to entering LPLU. 2688282289Serj **/ 2689282289Serjs32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2690282289Serj{ 2691282289Serj u16 an_10g_cntl_reg, autoneg_reg, speed; 2692282289Serj s32 status; 2693282289Serj ixgbe_link_speed lcd_speed; 2694282289Serj u32 save_autoneg; 2695282289Serj bool link_up; 2696282289Serj 2697292674Ssbruno /* SW LPLU not required on later HW revisions. */ 2698292674Ssbruno if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))) 2699292674Ssbruno return IXGBE_SUCCESS; 2700292674Ssbruno 2701282289Serj /* If blocked by MNG FW, then don't restart AN */ 2702282289Serj if (ixgbe_check_reset_blocked(hw)) 2703282289Serj return IXGBE_SUCCESS; 2704282289Serj 2705282289Serj status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2706282289Serj if (status != IXGBE_SUCCESS) 2707282289Serj return status; 2708282289Serj 2709282289Serj status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 2710282289Serj 2711282289Serj if (status != IXGBE_SUCCESS) 2712282289Serj return status; 2713282289Serj 2714282289Serj /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 2715282289Serj * disabled, then force link down by entering low power mode. 2716282289Serj */ 2717282289Serj if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2718282289Serj !(hw->wol_enabled || ixgbe_mng_present(hw))) 2719282289Serj return ixgbe_set_copper_phy_power(hw, FALSE); 2720282289Serj 2721282289Serj /* Determine LCD */ 2722282289Serj status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 2723282289Serj 2724282289Serj if (status != IXGBE_SUCCESS) 2725282289Serj return status; 2726282289Serj 2727282289Serj /* If no valid LCD link speed, then force link down and exit. */ 2728282289Serj if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 2729282289Serj return ixgbe_set_copper_phy_power(hw, FALSE); 2730282289Serj 2731282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2732282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2733282289Serj &speed); 2734282289Serj 2735282289Serj if (status != IXGBE_SUCCESS) 2736282289Serj return status; 2737282289Serj 2738282289Serj /* If no link now, speed is invalid so take link down */ 2739282289Serj status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2740282289Serj if (status != IXGBE_SUCCESS) 2741282289Serj return ixgbe_set_copper_phy_power(hw, FALSE); 2742282289Serj 2743282289Serj /* clear everything but the speed bits */ 2744282289Serj speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 2745282289Serj 2746282289Serj /* If current speed is already LCD, then exit. */ 2747282289Serj if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 2748282289Serj (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 2749282289Serj ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 2750282289Serj (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 2751282289Serj return status; 2752282289Serj 2753282289Serj /* Clear AN completed indication */ 2754282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 2755282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2756282289Serj &autoneg_reg); 2757282289Serj 2758282289Serj if (status != IXGBE_SUCCESS) 2759282289Serj return status; 2760282289Serj 2761282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 2762282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2763282289Serj &an_10g_cntl_reg); 2764282289Serj 2765282289Serj if (status != IXGBE_SUCCESS) 2766282289Serj return status; 2767282289Serj 2768282289Serj status = hw->phy.ops.read_reg(hw, 2769282289Serj IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 2770282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2771282289Serj &autoneg_reg); 2772282289Serj 2773282289Serj if (status != IXGBE_SUCCESS) 2774282289Serj return status; 2775282289Serj 2776282289Serj save_autoneg = hw->phy.autoneg_advertised; 2777282289Serj 2778282289Serj /* Setup link at least common link speed */ 2779282289Serj status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 2780282289Serj 2781282289Serj /* restore autoneg from before setting lplu speed */ 2782282289Serj hw->phy.autoneg_advertised = save_autoneg; 2783282289Serj 2784282289Serj return status; 2785282289Serj} 2786282289Serj 2787282289Serj/** 2788282289Serj * ixgbe_get_lcd_x550em - Determine lowest common denominator 2789282289Serj * @hw: pointer to hardware structure 2790282289Serj * @lcd_speed: pointer to lowest common link speed 2791282289Serj * 2792282289Serj * Determine lowest common link speed with link partner. 2793282289Serj **/ 2794282289Serjs32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 2795282289Serj{ 2796282289Serj u16 an_lp_status; 2797282289Serj s32 status; 2798282289Serj u16 word = hw->eeprom.ctrl_word_3; 2799282289Serj 2800282289Serj *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2801282289Serj 2802282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2803282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2804282289Serj &an_lp_status); 2805282289Serj 2806282289Serj if (status != IXGBE_SUCCESS) 2807282289Serj return status; 2808282289Serj 2809282289Serj /* If link partner advertised 1G, return 1G */ 2810282289Serj if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2811282289Serj *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2812282289Serj return status; 2813282289Serj } 2814282289Serj 2815282289Serj /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2816282289Serj if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2817282289Serj (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2818282289Serj return status; 2819282289Serj 2820282289Serj /* Link partner not capable of lower speeds, return 10G */ 2821282289Serj *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2822282289Serj return status; 2823282289Serj} 2824282289Serj 2825282289Serj/** 2826282289Serj * ixgbe_setup_fc_X550em - Set up flow control 2827282289Serj * @hw: pointer to hardware structure 2828282289Serj * 2829282289Serj * Called at init time to set up flow control. 2830282289Serj **/ 2831282289Serjs32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 2832282289Serj{ 2833282289Serj s32 ret_val = IXGBE_SUCCESS; 2834282289Serj u32 pause, asm_dir, reg_val; 2835282289Serj 2836282289Serj DEBUGFUNC("ixgbe_setup_fc_X550em"); 2837282289Serj 2838282289Serj /* Validate the requested mode */ 2839282289Serj if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2840282289Serj ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 2841282289Serj "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2842282289Serj ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2843282289Serj goto out; 2844282289Serj } 2845282289Serj 2846282289Serj /* 10gig parts do not have a word in the EEPROM to determine the 2847282289Serj * default flow control setting, so we explicitly set it to full. 2848282289Serj */ 2849282289Serj if (hw->fc.requested_mode == ixgbe_fc_default) 2850282289Serj hw->fc.requested_mode = ixgbe_fc_full; 2851282289Serj 2852282289Serj /* Determine PAUSE and ASM_DIR bits. */ 2853282289Serj switch (hw->fc.requested_mode) { 2854282289Serj case ixgbe_fc_none: 2855282289Serj pause = 0; 2856282289Serj asm_dir = 0; 2857282289Serj break; 2858282289Serj case ixgbe_fc_tx_pause: 2859282289Serj pause = 0; 2860282289Serj asm_dir = 1; 2861282289Serj break; 2862282289Serj case ixgbe_fc_rx_pause: 2863282289Serj /* Rx Flow control is enabled and Tx Flow control is 2864282289Serj * disabled by software override. Since there really 2865282289Serj * isn't a way to advertise that we are capable of RX 2866282289Serj * Pause ONLY, we will advertise that we support both 2867282289Serj * symmetric and asymmetric Rx PAUSE, as such we fall 2868282289Serj * through to the fc_full statement. Later, we will 2869282289Serj * disable the adapter's ability to send PAUSE frames. 2870282289Serj */ 2871282289Serj case ixgbe_fc_full: 2872282289Serj pause = 1; 2873282289Serj asm_dir = 1; 2874282289Serj break; 2875282289Serj default: 2876282289Serj ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2877282289Serj "Flow control param set incorrectly\n"); 2878282289Serj ret_val = IXGBE_ERR_CONFIG; 2879282289Serj goto out; 2880282289Serj } 2881282289Serj 2882292674Ssbruno if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 2883282289Serj ret_val = ixgbe_read_iosf_sb_reg_x550(hw, 2884282289Serj IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2885282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2886282289Serj if (ret_val != IXGBE_SUCCESS) 2887282289Serj goto out; 2888282289Serj reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2889282289Serj IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2890282289Serj if (pause) 2891282289Serj reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2892282289Serj if (asm_dir) 2893282289Serj reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2894282289Serj ret_val = ixgbe_write_iosf_sb_reg_x550(hw, 2895282289Serj IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2896282289Serj IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2897282289Serj 2898292674Ssbruno /* This device does not fully support AN. */ 2899292674Ssbruno hw->fc.disable_fc_autoneg = TRUE; 2900282289Serj } 2901282289Serj 2902282289Serjout: 2903282289Serj return ret_val; 2904282289Serj} 2905282289Serj 2906282289Serj/** 2907282289Serj * ixgbe_set_mux - Set mux for port 1 access with CS4227 2908282289Serj * @hw: pointer to hardware structure 2909282289Serj * @state: set mux if 1, clear if 0 2910282289Serj */ 2911282289Serjstatic void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 2912282289Serj{ 2913282289Serj u32 esdp; 2914282289Serj 2915282289Serj if (!hw->bus.lan_id) 2916282289Serj return; 2917282289Serj esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2918282289Serj if (state) 2919282289Serj esdp |= IXGBE_ESDP_SDP1; 2920282289Serj else 2921282289Serj esdp &= ~IXGBE_ESDP_SDP1; 2922282289Serj IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2923282289Serj IXGBE_WRITE_FLUSH(hw); 2924282289Serj} 2925282289Serj 2926282289Serj/** 2927282289Serj * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 2928282289Serj * @hw: pointer to hardware structure 2929282289Serj * @mask: Mask to specify which semaphore to acquire 2930282289Serj * 2931282289Serj * Acquires the SWFW semaphore and sets the I2C MUX 2932282289Serj **/ 2933282289Serjs32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2934282289Serj{ 2935282289Serj s32 status; 2936282289Serj 2937282289Serj DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 2938282289Serj 2939282289Serj status = ixgbe_acquire_swfw_sync_X540(hw, mask); 2940282289Serj if (status) 2941282289Serj return status; 2942282289Serj 2943282289Serj if (mask & IXGBE_GSSR_I2C_MASK) 2944282289Serj ixgbe_set_mux(hw, 1); 2945282289Serj 2946282289Serj return IXGBE_SUCCESS; 2947282289Serj} 2948282289Serj 2949282289Serj/** 2950282289Serj * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 2951282289Serj * @hw: pointer to hardware structure 2952282289Serj * @mask: Mask to specify which semaphore to release 2953282289Serj * 2954282289Serj * Releases the SWFW semaphore and sets the I2C MUX 2955282289Serj **/ 2956282289Serjvoid ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2957282289Serj{ 2958282289Serj DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 2959282289Serj 2960282289Serj if (mask & IXGBE_GSSR_I2C_MASK) 2961282289Serj ixgbe_set_mux(hw, 0); 2962282289Serj 2963282289Serj ixgbe_release_swfw_sync_X540(hw, mask); 2964282289Serj} 2965282289Serj 2966282289Serj/** 2967282289Serj * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2968282289Serj * @hw: pointer to hardware structure 2969282289Serj * 2970282289Serj * Handle external Base T PHY interrupt. If high temperature 2971282289Serj * failure alarm then return error, else if link status change 2972282289Serj * then setup internal/external PHY link 2973282289Serj * 2974282289Serj * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2975282289Serj * failure alarm, else return PHY access status. 2976282289Serj */ 2977282289Serjs32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2978282289Serj{ 2979282289Serj bool lsc; 2980282289Serj u32 status; 2981282289Serj 2982282289Serj status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2983282289Serj 2984282289Serj if (status != IXGBE_SUCCESS) 2985282289Serj return status; 2986282289Serj 2987282289Serj if (lsc) 2988282289Serj return ixgbe_setup_internal_phy(hw); 2989282289Serj 2990282289Serj return IXGBE_SUCCESS; 2991282289Serj} 2992282289Serj 2993282289Serj/** 2994282289Serj * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 2995282289Serj * @hw: pointer to hardware structure 2996282289Serj * @speed: new link speed 2997282289Serj * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 2998282289Serj * 2999282289Serj * Setup internal/external PHY link speed based on link speed, then set 3000282289Serj * external PHY auto advertised link speed. 3001282289Serj * 3002282289Serj * Returns error status for any failure 3003282289Serj **/ 3004282289Serjs32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 3005282289Serj ixgbe_link_speed speed, 3006282289Serj bool autoneg_wait_to_complete) 3007282289Serj{ 3008282289Serj s32 status; 3009282289Serj ixgbe_link_speed force_speed; 3010282289Serj 3011282289Serj DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 3012282289Serj 3013282289Serj /* Setup internal/external PHY link speed to iXFI (10G), unless 3014282289Serj * only 1G is auto advertised then setup KX link. 3015282289Serj */ 3016282289Serj if (speed & IXGBE_LINK_SPEED_10GB_FULL) 3017282289Serj force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3018282289Serj else 3019282289Serj force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3020282289Serj 3021282289Serj /* If internal link mode is XFI, then setup XFI internal link. */ 3022282289Serj if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3023282289Serj status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 3024282289Serj 3025282289Serj if (status != IXGBE_SUCCESS) 3026282289Serj return status; 3027282289Serj } 3028282289Serj 3029282289Serj return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 3030282289Serj} 3031282289Serj 3032282289Serj/** 3033282289Serj * ixgbe_check_link_t_X550em - Determine link and speed status 3034282289Serj * @hw: pointer to hardware structure 3035282289Serj * @speed: pointer to link speed 3036282289Serj * @link_up: TRUE when link is up 3037282289Serj * @link_up_wait_to_complete: bool used to wait for link up or not 3038282289Serj * 3039282289Serj * Check that both the MAC and X557 external PHY have link. 3040282289Serj **/ 3041282289Serjs32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3042282289Serj bool *link_up, bool link_up_wait_to_complete) 3043282289Serj{ 3044282289Serj u32 status; 3045282289Serj u16 autoneg_status; 3046282289Serj 3047282289Serj if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3048282289Serj return IXGBE_ERR_CONFIG; 3049282289Serj 3050282289Serj status = ixgbe_check_mac_link_generic(hw, speed, link_up, 3051282289Serj link_up_wait_to_complete); 3052282289Serj 3053282289Serj /* If check link fails or MAC link is not up, then return */ 3054282289Serj if (status != IXGBE_SUCCESS || !(*link_up)) 3055282289Serj return status; 3056282289Serj 3057282289Serj /* MAC link is up, so check external PHY link. 3058282289Serj * Read this twice back to back to indicate current status. 3059282289Serj */ 3060282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3061282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3062282289Serj &autoneg_status); 3063282289Serj 3064282289Serj if (status != IXGBE_SUCCESS) 3065282289Serj return status; 3066282289Serj 3067282289Serj status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3068282289Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3069282289Serj &autoneg_status); 3070282289Serj 3071282289Serj if (status != IXGBE_SUCCESS) 3072282289Serj return status; 3073282289Serj 3074282289Serj /* If external PHY link is not up, then indicate link not up */ 3075282289Serj if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 3076282289Serj *link_up = FALSE; 3077282289Serj 3078282289Serj return IXGBE_SUCCESS; 3079282289Serj} 3080282289Serj 3081282289Serj/** 3082282289Serj * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 3083282289Serj * @hw: pointer to hardware structure 3084282289Serj **/ 3085282289Serjs32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 3086282289Serj{ 3087282289Serj s32 status; 3088282289Serj 3089282289Serj status = ixgbe_reset_phy_generic(hw); 3090282289Serj 3091282289Serj if (status != IXGBE_SUCCESS) 3092282289Serj return status; 3093282289Serj 3094282289Serj /* Configure Link Status Alarm and Temperature Threshold interrupts */ 3095282289Serj return ixgbe_enable_lasi_ext_t_x550em(hw); 3096282289Serj} 3097282289Serj 3098282289Serj/** 3099282289Serj * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 3100282289Serj * @hw: pointer to hardware structure 3101282289Serj * @led_idx: led number to turn on 3102282289Serj **/ 3103282289Serjs32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3104282289Serj{ 3105282289Serj u16 phy_data; 3106282289Serj 3107282289Serj DEBUGFUNC("ixgbe_led_on_t_X550em"); 3108282289Serj 3109282289Serj if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3110282289Serj return IXGBE_ERR_PARAM; 3111282289Serj 3112282289Serj /* To turn on the LED, set mode to ON. */ 3113282289Serj ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3114282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3115282289Serj phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 3116282289Serj ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3117282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3118282289Serj 3119282289Serj return IXGBE_SUCCESS; 3120282289Serj} 3121282289Serj 3122282289Serj/** 3123282289Serj * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 3124282289Serj * @hw: pointer to hardware structure 3125282289Serj * @led_idx: led number to turn off 3126282289Serj **/ 3127282289Serjs32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3128282289Serj{ 3129282289Serj u16 phy_data; 3130282289Serj 3131282289Serj DEBUGFUNC("ixgbe_led_off_t_X550em"); 3132282289Serj 3133282289Serj if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3134282289Serj return IXGBE_ERR_PARAM; 3135282289Serj 3136282289Serj /* To turn on the LED, set mode to ON. */ 3137282289Serj ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3138282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3139282289Serj phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 3140282289Serj ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3141282289Serj IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3142282289Serj 3143282289Serj return IXGBE_SUCCESS; 3144282289Serj} 3145282289Serj 3146