1179055Sjfv/****************************************************************************** 2171384Sjfv 3282289Serj Copyright (c) 2001-2015, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: releng/11.0/sys/dev/ixgbe/ixgbe_phy.h 292674 2015-12-23 22:45:17Z sbruno $*/ 34171384Sjfv 35171384Sjfv#ifndef _IXGBE_PHY_H_ 36171384Sjfv#define _IXGBE_PHY_H_ 37171384Sjfv 38171384Sjfv#include "ixgbe_type.h" 39247822Sjfv#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 40247822Sjfv#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2 41247822Sjfv#define IXGBE_I2C_EEPROM_BANK_LEN 0xFF 42171384Sjfv 43185352Sjfv/* EEPROM byte offsets */ 44230775Sjfv#define IXGBE_SFF_IDENTIFIER 0x0 45230775Sjfv#define IXGBE_SFF_IDENTIFIER_SFP 0x3 46230775Sjfv#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 47230775Sjfv#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 48230775Sjfv#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 49230775Sjfv#define IXGBE_SFF_1GBE_COMP_CODES 0x6 50230775Sjfv#define IXGBE_SFF_10GBE_COMP_CODES 0x3 51230775Sjfv#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8 52230775Sjfv#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C 53247822Sjfv#define IXGBE_SFF_SFF_8472_SWAP 0x5C 54247822Sjfv#define IXGBE_SFF_SFF_8472_COMP 0x5E 55247822Sjfv#define IXGBE_SFF_SFF_8472_OSCB 0x6E 56247822Sjfv#define IXGBE_SFF_SFF_8472_ESCB 0x76 57280182Sjfv#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD 58280182Sjfv#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5 59280182Sjfv#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6 60280182Sjfv#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7 61280182Sjfv#define IXGBE_SFF_QSFP_CONNECTOR 0x82 62280182Sjfv#define IXGBE_SFF_QSFP_10GBE_COMP 0x83 63280182Sjfv#define IXGBE_SFF_QSFP_1GBE_COMP 0x86 64280182Sjfv#define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92 65280182Sjfv#define IXGBE_SFF_QSFP_DEVICE_TECH 0x93 66185352Sjfv 67185352Sjfv/* Bitmasks */ 68230775Sjfv#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4 69230775Sjfv#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8 70230775Sjfv#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 71230775Sjfv#define IXGBE_SFF_1GBASESX_CAPABLE 0x1 72230775Sjfv#define IXGBE_SFF_1GBASELX_CAPABLE 0x2 73230775Sjfv#define IXGBE_SFF_1GBASET_CAPABLE 0x8 74230775Sjfv#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 75230775Sjfv#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 76247822Sjfv#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8 77247822Sjfv#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8 78247822Sjfv#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0 79280182Sjfv#define IXGBE_SFF_ADDRESSING_MODE 0x4 80280182Sjfv#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1 81280182Sjfv#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8 82280182Sjfv#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23 83280182Sjfv#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0 84230775Sjfv#define IXGBE_I2C_EEPROM_READ_MASK 0x100 85230775Sjfv#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 86230775Sjfv#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 87230775Sjfv#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 88230775Sjfv#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 89230775Sjfv#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 90185352Sjfv 91280182Sjfv#define IXGBE_CS4227 0xBE /* CS4227 address */ 92282289Serj#define IXGBE_CS4227_GLOBAL_ID_LSB 0 93282289Serj#define IXGBE_CS4227_SCRATCH 2 94282289Serj#define IXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5 95292674Ssbruno#define IXGBE_CS4227_RESET_PENDING 0x1357 96292674Ssbruno#define IXGBE_CS4227_RESET_COMPLETE 0x5AA5 97292674Ssbruno#define IXGBE_CS4227_RETRIES 15 98292674Ssbruno#define IXGBE_CS4227_EFUSE_STATUS 0x0181 99282289Serj#define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to program speed */ 100282289Serj#define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to program EDC */ 101282289Serj#define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to program speed */ 102282289Serj#define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */ 103292674Ssbruno#define IXGBE_CS4227_EEPROM_STATUS 0x5001 104292674Ssbruno#define IXGBE_CS4227_EEPROM_LOAD_OK 0x0001 105292674Ssbruno#define IXGBE_CS4227_SPEED_1G 0x8000 106292674Ssbruno#define IXGBE_CS4227_SPEED_10G 0 107280182Sjfv#define IXGBE_CS4227_EDC_MODE_CX1 0x0002 108280182Sjfv#define IXGBE_CS4227_EDC_MODE_SR 0x0004 109292674Ssbruno#define IXGBE_CS4227_EDC_MODE_DIAG 0x0008 110282289Serj#define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */ 111292674Ssbruno#define IXGBE_CS4227_RESET_DELAY 450 /* milliseconds */ 112282289Serj#define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */ 113282289Serj#define IXGBE_PE 0xE0 /* Port expander address */ 114282289Serj#define IXGBE_PE_OUTPUT 1 /* Output register offset */ 115282289Serj#define IXGBE_PE_CONFIG 3 /* Config register offset */ 116282289Serj#define IXGBE_PE_BIT1 (1 << 1) 117280182Sjfv 118215911Sjfv/* Flow control defines */ 119230775Sjfv#define IXGBE_TAF_SYM_PAUSE 0x400 120230775Sjfv#define IXGBE_TAF_ASM_PAUSE 0x800 121215911Sjfv 122185352Sjfv/* Bit-shift macros */ 123230775Sjfv#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24 124230775Sjfv#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16 125230775Sjfv#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8 126185352Sjfv 127185352Sjfv/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 128230775Sjfv#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 129230775Sjfv#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 130230775Sjfv#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 131230775Sjfv#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100 132185352Sjfv 133185352Sjfv/* I2C SDA and SCL timing parameters for standard mode */ 134230775Sjfv#define IXGBE_I2C_T_HD_STA 4 135230775Sjfv#define IXGBE_I2C_T_LOW 5 136230775Sjfv#define IXGBE_I2C_T_HIGH 4 137230775Sjfv#define IXGBE_I2C_T_SU_STA 5 138230775Sjfv#define IXGBE_I2C_T_HD_DATA 5 139230775Sjfv#define IXGBE_I2C_T_SU_DATA 1 140230775Sjfv#define IXGBE_I2C_T_RISE 1 141230775Sjfv#define IXGBE_I2C_T_FALL 1 142230775Sjfv#define IXGBE_I2C_T_SU_STO 4 143230775Sjfv#define IXGBE_I2C_T_BUF 5 144185352Sjfv 145280182Sjfv#ifndef IXGBE_SFP_DETECT_RETRIES 146280182Sjfv#define IXGBE_SFP_DETECT_RETRIES 10 147280182Sjfv 148280182Sjfv#endif /* IXGBE_SFP_DETECT_RETRIES */ 149230775Sjfv#define IXGBE_TN_LASI_STATUS_REG 0x9005 150230775Sjfv#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008 151185352Sjfv 152247822Sjfv/* SFP+ SFF-8472 Compliance */ 153247822Sjfv#define IXGBE_SFF_SFF_8472_UNSUP 0x00 154247822Sjfv 155179055Sjfvs32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 156171384Sjfvbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 157171384Sjfvenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 158171384Sjfvs32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 159171384Sjfvs32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 160171384Sjfvs32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 161251964Sjfvs32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 162251964Sjfv u16 *phy_data); 163251964Sjfvs32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 164251964Sjfv u16 phy_data); 165171384Sjfvs32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 166230775Sjfv u32 device_type, u16 *phy_data); 167171384Sjfvs32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 168230775Sjfv u32 device_type, u16 phy_data); 169179055Sjfvs32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); 170179055Sjfvs32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 171230775Sjfv ixgbe_link_speed speed, 172230775Sjfv bool autoneg_wait_to_complete); 173190873Sjfvs32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 174230775Sjfv ixgbe_link_speed *speed, 175230775Sjfv bool *autoneg); 176280182Sjfvs32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw); 177171384Sjfv 178179055Sjfv/* PHY specific */ 179179055Sjfvs32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 180230775Sjfv ixgbe_link_speed *speed, 181230775Sjfv bool *link_up); 182200239Sjfvs32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); 183179055Sjfvs32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 184230775Sjfv u16 *firmware_version); 185200239Sjfvs32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 186230775Sjfv u16 *firmware_version); 187179055Sjfv 188185352Sjfvs32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 189280182Sjfvs32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on); 190230775Sjfvs32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); 191185352Sjfvs32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 192280182Sjfvs32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw); 193280182Sjfvs32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 194185352Sjfvs32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 195230775Sjfv u16 *list_offset, 196230775Sjfv u16 *data_offset); 197205720Sjfvs32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); 198190873Sjfvs32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 199230775Sjfv u8 dev_addr, u8 *data); 200282289Serjs32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 201282289Serj u8 dev_addr, u8 *data); 202190873Sjfvs32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 203230775Sjfv u8 dev_addr, u8 data); 204282289Serjs32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 205282289Serj u8 dev_addr, u8 data); 206190873Sjfvs32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 207230775Sjfv u8 *eeprom_data); 208190873Sjfvs32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 209230775Sjfv u8 eeprom_data); 210230775Sjfvvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 211171384Sjfv#endif /* _IXGBE_PHY_H_ */ 212