ixgbe_dcb_82598.h revision 302408 
121308Sache/******************************************************************************
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3221308Sache******************************************************************************/
3321308Sache/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_dcb_82598.h 282289 2015-04-30 22:53:27Z erj $*/
3421308Sache
3547563Sache#ifndef _IXGBE_DCB_82598_H_
3621308Sache#define _IXGBE_DCB_82598_H_
3721308Sache
3821308Sache/* DCB register definitions */
3921308Sache
4021308Sache#define IXGBE_DPMCS_MTSOS_SHIFT	16
4121308Sache#define IXGBE_DPMCS_TDPAC	0x00000001 /* 0 Round Robin,
4221308Sache					    * 1 DFP - Deficit Fixed Priority */
4321308Sache#define IXGBE_DPMCS_TRM		0x00000010 /* Transmit Recycle Mode */
4421308Sache#define IXGBE_DPMCS_ARBDIS	0x00000040 /* DCB arbiter disable */
4521308Sache#define IXGBE_DPMCS_TSOEF	0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
4621308Sache
4721308Sache#define IXGBE_RUPPBMR_MQA	0x80000000 /* Enable UP to queue mapping */
4821308Sache
4921308Sache#define IXGBE_RT2CR_MCL_SHIFT	12 /* Offset to Max Credit Limit setting */
5021308Sache#define IXGBE_RT2CR_LSP		0x80000000 /* LSP enable bit */
5121308Sache
5221308Sache#define IXGBE_RDRXCTL_MPBEN	0x00000010 /* DMA config for multiple packet
5321308Sache					    * buffers enable */
5421308Sache#define IXGBE_RDRXCTL_MCEN	0x00000040 /* DMA config for multiple cores
5521308Sache					    * (RSS) enable */
5621308Sache
5721308Sache#define IXGBE_TDTQ2TCCR_MCL_SHIFT	12
5821308Sache#define IXGBE_TDTQ2TCCR_BWG_SHIFT	9
5947563Sache#define IXGBE_TDTQ2TCCR_GSP	0x40000000
6021308Sache#define IXGBE_TDTQ2TCCR_LSP	0x80000000
6121308Sache
62#define IXGBE_TDPT2TCCR_MCL_SHIFT	12
63#define IXGBE_TDPT2TCCR_BWG_SHIFT	9
64#define IXGBE_TDPT2TCCR_GSP	0x40000000
65#define IXGBE_TDPT2TCCR_LSP	0x80000000
66
67#define IXGBE_PDPMCS_TPPAC	0x00000020 /* 0 Round Robin,
68					    * 1 DFP - Deficit Fixed Priority */
69#define IXGBE_PDPMCS_ARBDIS	0x00000040 /* Arbiter disable */
70#define IXGBE_PDPMCS_TRM	0x00000100 /* Transmit Recycle Mode enable */
71
72#define IXGBE_DTXCTL_ENDBUBD	0x00000004 /* Enable DBU buffer division */
73
74#define IXGBE_TXPBSIZE_40KB	0x0000A000 /* 40KB Packet Buffer */
75#define IXGBE_RXPBSIZE_48KB	0x0000C000 /* 48KB Packet Buffer */
76#define IXGBE_RXPBSIZE_64KB	0x00010000 /* 64KB Packet Buffer */
77#define IXGBE_RXPBSIZE_80KB	0x00014000 /* 80KB Packet Buffer */
78
79/* DCB driver APIs */
80
81/* DCB PFC */
82s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);
83
84/* DCB stats */
85s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *);
86s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *,
87				 struct ixgbe_hw_stats *, u8);
88s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *,
89				  struct ixgbe_hw_stats *, u8);
90
91/* DCB config arbiters */
92s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
93					   u8 *, u8 *);
94s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
95					   u8 *, u8 *);
96s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);
97
98/* DCB initialization */
99s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);
100#endif /* _IXGBE_DCB_82958_H_ */
101