1303628Ssbruno/* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2286441Srpaulo/* $FreeBSD: releng/11.0/sys/dev/iwm/if_iwmreg.h 303628 2016-08-01 17:51:35Z sbruno $ */ 3286441Srpaulo 4286441Srpaulo/****************************************************************************** 5286441Srpaulo * 6286441Srpaulo * This file is provided under a dual BSD/GPLv2 license. When using or 7286441Srpaulo * redistributing this file, you may do so under either license. 8286441Srpaulo * 9286441Srpaulo * GPL LICENSE SUMMARY 10286441Srpaulo * 11286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12286441Srpaulo * 13286441Srpaulo * This program is free software; you can redistribute it and/or modify 14286441Srpaulo * it under the terms of version 2 of the GNU General Public License as 15286441Srpaulo * published by the Free Software Foundation. 16286441Srpaulo * 17286441Srpaulo * This program is distributed in the hope that it will be useful, but 18286441Srpaulo * WITHOUT ANY WARRANTY; without even the implied warranty of 19286441Srpaulo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20286441Srpaulo * General Public License for more details. 21286441Srpaulo * 22286441Srpaulo * You should have received a copy of the GNU General Public License 23286441Srpaulo * along with this program; if not, write to the Free Software 24286441Srpaulo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25286441Srpaulo * USA 26286441Srpaulo * 27286441Srpaulo * The full GNU General Public License is included in this distribution 28286441Srpaulo * in the file called COPYING. 29286441Srpaulo * 30286441Srpaulo * Contact Information: 31286441Srpaulo * Intel Linux Wireless <ilw@linux.intel.com> 32286441Srpaulo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33286441Srpaulo * 34286441Srpaulo * BSD LICENSE 35286441Srpaulo * 36286441Srpaulo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37286441Srpaulo * All rights reserved. 38286441Srpaulo * 39286441Srpaulo * Redistribution and use in source and binary forms, with or without 40286441Srpaulo * modification, are permitted provided that the following conditions 41286441Srpaulo * are met: 42286441Srpaulo * 43286441Srpaulo * * Redistributions of source code must retain the above copyright 44286441Srpaulo * notice, this list of conditions and the following disclaimer. 45286441Srpaulo * * Redistributions in binary form must reproduce the above copyright 46286441Srpaulo * notice, this list of conditions and the following disclaimer in 47286441Srpaulo * the documentation and/or other materials provided with the 48286441Srpaulo * distribution. 49286441Srpaulo * * Neither the name Intel Corporation nor the names of its 50286441Srpaulo * contributors may be used to endorse or promote products derived 51286441Srpaulo * from this software without specific prior written permission. 52286441Srpaulo * 53286441Srpaulo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54286441Srpaulo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55286441Srpaulo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56286441Srpaulo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57286441Srpaulo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58286441Srpaulo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59286441Srpaulo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60286441Srpaulo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61286441Srpaulo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62286441Srpaulo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63286441Srpaulo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64286441Srpaulo * 65286441Srpaulo *****************************************************************************/ 66286441Srpaulo#ifndef __IF_IWM_REG_H__ 67286441Srpaulo#define __IF_IWM_REG_H__ 68286441Srpaulo 69286441Srpaulo#define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70286441Srpaulo#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71286441Srpaulo 72286441Srpaulo/* 73286441Srpaulo * BEGIN iwl-csr.h 74286441Srpaulo */ 75286441Srpaulo 76286441Srpaulo/* 77286441Srpaulo * CSR (control and status registers) 78286441Srpaulo * 79286441Srpaulo * CSR registers are mapped directly into PCI bus space, and are accessible 80286441Srpaulo * whenever platform supplies power to device, even when device is in 81286441Srpaulo * low power states due to driver-invoked device resets 82286441Srpaulo * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 83286441Srpaulo * 84286441Srpaulo * Use iwl_write32() and iwl_read32() family to access these registers; 85286441Srpaulo * these provide simple PCI bus access, without waking up the MAC. 86286441Srpaulo * Do not use iwl_write_direct32() family for these registers; 87286441Srpaulo * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 88286441Srpaulo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 89286441Srpaulo * the CSR registers. 90286441Srpaulo * 91286441Srpaulo * NOTE: Device does need to be awake in order to read this memory 92286441Srpaulo * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 93286441Srpaulo */ 94286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 95286441Srpaulo#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 96286441Srpaulo#define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 97286441Srpaulo#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 98286441Srpaulo#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 99286441Srpaulo#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 100286441Srpaulo#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 101286441Srpaulo#define IWM_CSR_GP_CNTRL (0x024) 102286441Srpaulo 103286441Srpaulo/* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 104286441Srpaulo#define IWM_CSR_INT_PERIODIC_REG (0x005) 105286441Srpaulo 106286441Srpaulo/* 107286441Srpaulo * Hardware revision info 108286441Srpaulo * Bit fields: 109286441Srpaulo * 31-16: Reserved 110286441Srpaulo * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 111286441Srpaulo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 112286441Srpaulo * 1-0: "Dash" (-) value, as in A-1, etc. 113286441Srpaulo */ 114286441Srpaulo#define IWM_CSR_HW_REV (0x028) 115286441Srpaulo 116286441Srpaulo/* 117286441Srpaulo * EEPROM and OTP (one-time-programmable) memory reads 118286441Srpaulo * 119286441Srpaulo * NOTE: Device must be awake, initialized via apm_ops.init(), 120286441Srpaulo * in order to read. 121286441Srpaulo */ 122286441Srpaulo#define IWM_CSR_EEPROM_REG (0x02c) 123286441Srpaulo#define IWM_CSR_EEPROM_GP (0x030) 124286441Srpaulo#define IWM_CSR_OTP_GP_REG (0x034) 125286441Srpaulo 126286441Srpaulo#define IWM_CSR_GIO_REG (0x03C) 127286441Srpaulo#define IWM_CSR_GP_UCODE_REG (0x048) 128286441Srpaulo#define IWM_CSR_GP_DRIVER_REG (0x050) 129286441Srpaulo 130286441Srpaulo/* 131286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox registers. 132286441Srpaulo * SET/CLR registers set/clear bit(s) if "1" is written. 133286441Srpaulo */ 134286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1 (0x054) 135286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 136286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 137286441Srpaulo#define IWM_CSR_UCODE_DRV_GP2 (0x060) 138286441Srpaulo 139303628Ssbruno#define IWM_CSR_MBOX_SET_REG (0x088) 140303628Ssbruno#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 141303628Ssbruno 142286441Srpaulo#define IWM_CSR_LED_REG (0x094) 143286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 144286441Srpaulo#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 145286441Srpaulo 146286441Srpaulo 147286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 148286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS (0x100) 149286441Srpaulo 150286441Srpaulo/* Analog phase-lock-loop configuration */ 151286441Srpaulo#define IWM_CSR_ANA_PLL_CFG (0x20c) 152286441Srpaulo 153286441Srpaulo/* 154286441Srpaulo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 155286441Srpaulo * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 156286441Srpaulo * See also IWM_CSR_HW_REV register. 157286441Srpaulo * Bit fields: 158286441Srpaulo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 159286441Srpaulo * 1-0: "Dash" (-) value, as in C-1, etc. 160286441Srpaulo */ 161286441Srpaulo#define IWM_CSR_HW_REV_WA_REG (0x22C) 162286441Srpaulo 163286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG (0x240) 164286441Srpaulo#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 165286441Srpaulo 166286441Srpaulo/* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 167286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 168286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 169286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 170286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 171286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 172286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 173286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 174286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 175286441Srpaulo 176286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 177286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 178286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 179286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 180286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 181286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 182286441Srpaulo 183286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 184286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 185286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 186286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 187286441Srpaulo#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 188303628Ssbruno#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 189303628Ssbruno#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 190286441Srpaulo 191286441Srpaulo#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 192286441Srpaulo#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 193286441Srpaulo 194286441Srpaulo/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 195286441Srpaulo * acknowledged (reset) by host writing "1" to flagged bits. */ 196286441Srpaulo#define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 197286441Srpaulo#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 198286441Srpaulo#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 199286441Srpaulo#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 200286441Srpaulo#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 201286441Srpaulo#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 202286441Srpaulo#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 203286441Srpaulo#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 204286441Srpaulo#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 205286441Srpaulo#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 206286441Srpaulo#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 207286441Srpaulo 208286441Srpaulo#define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 209286441Srpaulo IWM_CSR_INT_BIT_HW_ERR | \ 210286441Srpaulo IWM_CSR_INT_BIT_FH_TX | \ 211286441Srpaulo IWM_CSR_INT_BIT_SW_ERR | \ 212286441Srpaulo IWM_CSR_INT_BIT_RF_KILL | \ 213286441Srpaulo IWM_CSR_INT_BIT_SW_RX | \ 214286441Srpaulo IWM_CSR_INT_BIT_WAKEUP | \ 215286441Srpaulo IWM_CSR_INT_BIT_ALIVE | \ 216286441Srpaulo IWM_CSR_INT_BIT_RX_PERIODIC) 217286441Srpaulo 218286441Srpaulo/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 219286441Srpaulo#define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 220286441Srpaulo#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 221286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 222286441Srpaulo#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 223286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 224286441Srpaulo#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 225286441Srpaulo 226286441Srpaulo#define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 227286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 228286441Srpaulo IWM_CSR_FH_INT_BIT_RX_CHNL0) 229286441Srpaulo 230286441Srpaulo#define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 231286441Srpaulo IWM_CSR_FH_INT_BIT_TX_CHNL0) 232286441Srpaulo 233286441Srpaulo/* GPIO */ 234286441Srpaulo#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 235286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 236286441Srpaulo#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 237286441Srpaulo 238286441Srpaulo/* RESET */ 239286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 240286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 241286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 242286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 243286441Srpaulo#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 244286441Srpaulo#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 245286441Srpaulo 246286441Srpaulo/* 247286441Srpaulo * GP (general purpose) CONTROL REGISTER 248286441Srpaulo * Bit fields: 249286441Srpaulo * 27: HW_RF_KILL_SW 250286441Srpaulo * Indicates state of (platform's) hardware RF-Kill switch 251286441Srpaulo * 26-24: POWER_SAVE_TYPE 252286441Srpaulo * Indicates current power-saving mode: 253286441Srpaulo * 000 -- No power saving 254286441Srpaulo * 001 -- MAC power-down 255286441Srpaulo * 010 -- PHY (radio) power-down 256286441Srpaulo * 011 -- Error 257286441Srpaulo * 9-6: SYS_CONFIG 258286441Srpaulo * Indicates current system configuration, reflecting pins on chip 259286441Srpaulo * as forced high/low by device circuit board. 260286441Srpaulo * 4: GOING_TO_SLEEP 261286441Srpaulo * Indicates MAC is entering a power-saving sleep power-down. 262286441Srpaulo * Not a good time to access device-internal resources. 263286441Srpaulo * 3: MAC_ACCESS_REQ 264286441Srpaulo * Host sets this to request and maintain MAC wakeup, to allow host 265286441Srpaulo * access to device-internal resources. Host must wait for 266286441Srpaulo * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 267286441Srpaulo * device registers. 268286441Srpaulo * 2: INIT_DONE 269286441Srpaulo * Host sets this to put device into fully operational D0 power mode. 270286441Srpaulo * Host resets this after SW_RESET to put device into low power mode. 271286441Srpaulo * 0: MAC_CLOCK_READY 272286441Srpaulo * Indicates MAC (ucode processor, etc.) is powered up and can run. 273286441Srpaulo * Internal resources are accessible. 274286441Srpaulo * NOTE: This does not indicate that the processor is actually running. 275286441Srpaulo * NOTE: This does not indicate that device has completed 276286441Srpaulo * init or post-power-down restore of internal SRAM memory. 277286441Srpaulo * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 278286441Srpaulo * SRAM is restored and uCode is in normal operation mode. 279286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 280286441Srpaulo * do not need to save/restore it. 281286441Srpaulo * NOTE: After device reset, this bit remains "0" until host sets 282286441Srpaulo * INIT_DONE 283286441Srpaulo */ 284286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 285286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 286286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 287286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 288286441Srpaulo 289286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 290286441Srpaulo 291286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 292286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 293286441Srpaulo#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 294286441Srpaulo 295286441Srpaulo 296286441Srpaulo/* HW REV */ 297286441Srpaulo#define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 298286441Srpaulo#define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 299286441Srpaulo 300286441Srpaulo#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 301286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 302286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 303286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 304286441Srpaulo#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 305286441Srpaulo#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 306286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 307286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 308286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 309286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 310286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 311286441Srpaulo#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 312286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 313286441Srpaulo#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 314286441Srpaulo#define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 315286441Srpaulo#define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 316303628Ssbruno#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 317286441Srpaulo#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 318286441Srpaulo 319286441Srpaulo/* EEPROM REG */ 320286441Srpaulo#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 321286441Srpaulo#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 322286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 323286441Srpaulo#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 324286441Srpaulo 325286441Srpaulo/* EEPROM GP */ 326286441Srpaulo#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 327286441Srpaulo#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 328286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 329286441Srpaulo#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 330286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 331286441Srpaulo#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 332286441Srpaulo 333286441Srpaulo/* One-time-programmable memory general purpose reg */ 334286441Srpaulo#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 335286441Srpaulo#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 336286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 337286441Srpaulo#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 338286441Srpaulo 339286441Srpaulo/* GP REG */ 340286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 341286441Srpaulo#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 342286441Srpaulo#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 343286441Srpaulo#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 344286441Srpaulo#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 345286441Srpaulo 346286441Srpaulo 347286441Srpaulo/* CSR GIO */ 348286441Srpaulo#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 349286441Srpaulo 350286441Srpaulo/* 351286441Srpaulo * UCODE-DRIVER GP (general purpose) mailbox register 1 352286441Srpaulo * Host driver and uCode write and/or read this register to communicate with 353286441Srpaulo * each other. 354286441Srpaulo * Bit fields: 355286441Srpaulo * 4: UCODE_DISABLE 356286441Srpaulo * Host sets this to request permanent halt of uCode, same as 357286441Srpaulo * sending CARD_STATE command with "halt" bit set. 358286441Srpaulo * 3: CT_KILL_EXIT 359286441Srpaulo * Host sets this to request exit from CT_KILL state, i.e. host thinks 360286441Srpaulo * device temperature is low enough to continue normal operation. 361286441Srpaulo * 2: CMD_BLOCKED 362286441Srpaulo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 363286441Srpaulo * to release uCode to clear all Tx and command queues, enter 364286441Srpaulo * unassociated mode, and power down. 365286441Srpaulo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 366286441Srpaulo * 1: SW_BIT_RFKILL 367286441Srpaulo * Host sets this when issuing CARD_STATE command to request 368286441Srpaulo * device sleep. 369286441Srpaulo * 0: MAC_SLEEP 370286441Srpaulo * uCode sets this when preparing a power-saving power-down. 371286441Srpaulo * uCode resets this when power-up is complete and SRAM is sane. 372286441Srpaulo * NOTE: device saves internal SRAM data to host when powering down, 373286441Srpaulo * and must restore this data after powering back up. 374286441Srpaulo * MAC_SLEEP is the best indication that restore is complete. 375286441Srpaulo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 376286441Srpaulo * do not need to save/restore it. 377286441Srpaulo */ 378286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 379286441Srpaulo#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 380286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 381286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 382286441Srpaulo#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 383286441Srpaulo 384286441Srpaulo/* GP Driver */ 385286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 386286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 387286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 388286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 389286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 390286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 391286441Srpaulo 392286441Srpaulo#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 393286441Srpaulo 394286441Srpaulo/* GIO Chicken Bits (PCI Express bus link power management) */ 395286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 396286441Srpaulo#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 397286441Srpaulo 398286441Srpaulo/* LED */ 399286441Srpaulo#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 400286441Srpaulo#define IWM_CSR_LED_REG_TURN_ON (0x60) 401286441Srpaulo#define IWM_CSR_LED_REG_TURN_OFF (0x20) 402286441Srpaulo 403286441Srpaulo/* ANA_PLL */ 404286441Srpaulo#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 405286441Srpaulo 406286441Srpaulo/* HPET MEM debug */ 407286441Srpaulo#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 408286441Srpaulo 409286441Srpaulo/* DRAM INT TABLE */ 410286441Srpaulo#define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 411303628Ssbruno#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 412286441Srpaulo#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 413286441Srpaulo 414286441Srpaulo/* SECURE boot registers */ 415286441Srpaulo#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 416286441Srpauloenum iwm_secure_boot_config_reg { 417286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 418286441Srpaulo IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 419286441Srpaulo}; 420286441Srpaulo 421286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 422286441Srpaulo#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 423286441Srpauloenum iwm_secure_boot_status_reg { 424286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 425286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 426286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 427286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 428286441Srpaulo IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 429286441Srpaulo}; 430286441Srpaulo 431303628Ssbruno#define IWM_FH_UCODE_LOAD_STATUS 0x1af0 432303628Ssbruno#define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 433286441Srpauloenum iwm_secure_load_status_reg { 434303628Ssbruno IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 435303628Ssbruno IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 436303628Ssbruno IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 437303628Ssbruno IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 438303628Ssbruno IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 439286441Srpaulo}; 440303628Ssbruno#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 441286441Srpaulo 442303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 443303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 444303628Ssbruno#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 445303628Ssbruno#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 446286441Srpaulo 447303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 448303628Ssbruno#define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 449303628Ssbruno#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 450303628Ssbruno#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 451303628Ssbruno 452286441Srpaulo#define IWM_CSR_SECURE_TIME_OUT (100) 453286441Srpaulo 454303628Ssbruno/* extended range in FW SRAM */ 455303628Ssbruno#define IWM_FW_MEM_EXTENDED_START 0x40000 456303628Ssbruno#define IWM_FW_MEM_EXTENDED_END 0x57FFF 457303628Ssbruno 458303628Ssbruno/* FW chicken bits */ 459303628Ssbruno#define IWM_LMPM_CHICK 0xa01ff8 460303628Ssbruno#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 461303628Ssbruno 462286441Srpaulo#define IWM_FH_TCSR_0_REG0 (0x1D00) 463286441Srpaulo 464286441Srpaulo/* 465286441Srpaulo * HBUS (Host-side Bus) 466286441Srpaulo * 467286441Srpaulo * HBUS registers are mapped directly into PCI bus space, but are used 468286441Srpaulo * to indirectly access device's internal memory or registers that 469286441Srpaulo * may be powered-down. 470286441Srpaulo * 471286441Srpaulo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 472286441Srpaulo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 473286441Srpaulo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 474286441Srpaulo * internal resources. 475286441Srpaulo * 476286441Srpaulo * Do not use iwl_write32()/iwl_read32() family to access these registers; 477286441Srpaulo * these provide only simple PCI bus access, without waking up the MAC. 478286441Srpaulo */ 479286441Srpaulo#define IWM_HBUS_BASE (0x400) 480286441Srpaulo 481286441Srpaulo/* 482286441Srpaulo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 483286441Srpaulo * structures, error log, event log, verifying uCode load). 484286441Srpaulo * First write to address register, then read from or write to data register 485286441Srpaulo * to complete the job. Once the address register is set up, accesses to 486286441Srpaulo * data registers auto-increment the address by one dword. 487286441Srpaulo * Bit usage for address registers (read or write): 488286441Srpaulo * 0-31: memory address within device 489286441Srpaulo */ 490286441Srpaulo#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 491286441Srpaulo#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 492286441Srpaulo#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 493286441Srpaulo#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 494286441Srpaulo 495286441Srpaulo/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 496286441Srpaulo#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 497286441Srpaulo#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 498286441Srpaulo 499286441Srpaulo/* 500286441Srpaulo * Registers for accessing device's internal peripheral registers 501286441Srpaulo * (e.g. SCD, BSM, etc.). First write to address register, 502286441Srpaulo * then read from or write to data register to complete the job. 503286441Srpaulo * Bit usage for address registers (read or write): 504286441Srpaulo * 0-15: register address (offset) within device 505286441Srpaulo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 506286441Srpaulo */ 507286441Srpaulo#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 508286441Srpaulo#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 509286441Srpaulo#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 510286441Srpaulo#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 511286441Srpaulo 512303628Ssbruno/* enable the ID buf for read */ 513303628Ssbruno#define IWM_WFPM_PS_CTL_CLR 0xa0300c 514303628Ssbruno#define IWM_WFMP_MAC_ADDR_0 0xa03080 515303628Ssbruno#define IWM_WFMP_MAC_ADDR_1 0xa03084 516303628Ssbruno#define IWM_LMPM_PMG_EN 0xa01cec 517303628Ssbruno#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 518303628Ssbruno#define IWM_RFIC_REG_RD 0xad0470 519303628Ssbruno#define IWM_WFPM_CTRL_REG 0xa03030 520303628Ssbruno#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 521303628Ssbruno#define IWM_ENABLE_WFPM 0x80000000 522303628Ssbruno 523303628Ssbruno#define IWM_AUX_MISC_REG 0xa200b0 524303628Ssbruno#define IWM_HW_STEP_LOCATION_BITS 24 525303628Ssbruno 526303628Ssbruno#define IWM_AUX_MISC_MASTER1_EN 0xa20818 527303628Ssbruno#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 528303628Ssbruno#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 529303628Ssbruno#define IWM_RSA_ENABLE 0xa24b08 530303628Ssbruno#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 531303628Ssbruno#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 532303628Ssbruno#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 533303628Ssbruno#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 534303628Ssbruno#define IWM_SB_MODIFY_CFG_FLAG 0xa03088 535303628Ssbruno#define IWM_SB_CPU_1_STATUS 0xa01e30 536303628Ssbruno#define IWM_SB_CPU_2_STATUS 0Xa01e34 537303628Ssbruno 538286441Srpaulo/* Used to enable DBGM */ 539286441Srpaulo#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 540286441Srpaulo 541286441Srpaulo/* 542286441Srpaulo * Per-Tx-queue write pointer (index, really!) 543286441Srpaulo * Indicates index to next TFD that driver will fill (1 past latest filled). 544286441Srpaulo * Bit usage: 545286441Srpaulo * 0-7: queue write index 546286441Srpaulo * 11-8: queue selector 547286441Srpaulo */ 548286441Srpaulo#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 549286441Srpaulo 550286441Srpaulo/********************************************************** 551286441Srpaulo * CSR values 552286441Srpaulo **********************************************************/ 553286441Srpaulo /* 554286441Srpaulo * host interrupt timeout value 555286441Srpaulo * used with setting interrupt coalescing timer 556286441Srpaulo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 557286441Srpaulo * 558286441Srpaulo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 559286441Srpaulo */ 560286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 561286441Srpaulo#define IWM_HOST_INT_TIMEOUT_DEF (0x40) 562286441Srpaulo#define IWM_HOST_INT_TIMEOUT_MIN (0x0) 563286441Srpaulo#define IWM_HOST_INT_OPER_MODE (1 << 31) 564286441Srpaulo 565286441Srpaulo/***************************************************************************** 566286441Srpaulo * 7000/3000 series SHR DTS addresses * 567286441Srpaulo *****************************************************************************/ 568286441Srpaulo 569286441Srpaulo/* Diode Results Register Structure: */ 570286441Srpauloenum iwm_dtd_diode_reg { 571286441Srpaulo IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 572286441Srpaulo IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 573286441Srpaulo IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 574286441Srpaulo IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 575286441Srpaulo IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 576286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 577286441Srpaulo/* Those are the masks INSIDE the flags bit-field: */ 578286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 579286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 580286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 581286441Srpaulo IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 582286441Srpaulo}; 583286441Srpaulo 584286441Srpaulo/* 585286441Srpaulo * END iwl-csr.h 586286441Srpaulo */ 587286441Srpaulo 588286441Srpaulo/* 589286441Srpaulo * BEGIN iwl-fw.h 590286441Srpaulo */ 591286441Srpaulo 592286441Srpaulo/** 593301192Sadrian * enum iwm_ucode_tlv_flag - ucode API flags 594286441Srpaulo * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 595286441Srpaulo * was a separate TLV but moved here to save space. 596286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 597286441Srpaulo * treats good CRC threshold as a boolean 598286441Srpaulo * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 599286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 600286441Srpaulo * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 601286441Srpaulo * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 602286441Srpaulo * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 603286441Srpaulo * offload profile config command. 604286441Srpaulo * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 605286441Srpaulo * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 606286441Srpaulo * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 607286441Srpaulo * (rather than two) IPv6 addresses 608286441Srpaulo * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 609286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 610286441Srpaulo * from the probe request template. 611286441Srpaulo * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 612286441Srpaulo * connection when going back to D0 613286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 614286441Srpaulo * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 615286441Srpaulo * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 616286441Srpaulo * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 617286441Srpaulo * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 618286441Srpaulo * containing CAM (Continuous Active Mode) indication. 619286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 620286441Srpaulo * single bound interface). 621303628Ssbruno * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 622303628Ssbruno * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 623286441Srpaulo * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 624303628Ssbruno * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 625303628Ssbruno * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 626303628Ssbruno * 627286441Srpaulo */ 628286441Srpauloenum iwm_ucode_tlv_flag { 629286441Srpaulo IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 630286441Srpaulo IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 631286441Srpaulo IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 632286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 633286441Srpaulo IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 634286441Srpaulo IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 635286441Srpaulo IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 636286441Srpaulo IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 637286441Srpaulo IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 638286441Srpaulo IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 639286441Srpaulo IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 640286441Srpaulo IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 641286441Srpaulo IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 642286441Srpaulo IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 643286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 644286441Srpaulo IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 645286441Srpaulo IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 646286441Srpaulo IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 647286441Srpaulo IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 648286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 649303628Ssbruno IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 650303628Ssbruno IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 651286441Srpaulo IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 652303628Ssbruno IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 653286441Srpaulo IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 654303628Ssbruno IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 655303628Ssbruno IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 656303628Ssbruno IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 657286441Srpaulo}; 658286441Srpaulo 659303628Ssbruno#define IWM_UCODE_TLV_FLAG_BITS \ 660303628Ssbruno "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 661303628SsbrunoY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 662303628SsbrunoL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 663303628SsbrunoP2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 664303628Ssbruno 665303628Ssbruno/** 666303628Ssbruno * enum iwm_ucode_tlv_api - ucode api 667303628Ssbruno * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 668303628Ssbruno * longer than the passive one, which is essential for fragmented scan. 669303628Ssbruno * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 670303628Ssbruno * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 671303628Ssbruno * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 672303628Ssbruno * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 673303628Ssbruno * instead of 3. 674303628Ssbruno * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 675303628Ssbruno * (command version 3) that supports per-chain limits 676303628Ssbruno * 677303628Ssbruno * @IWM_NUM_UCODE_TLV_API: number of bits used 678303628Ssbruno */ 679303628Ssbrunoenum iwm_ucode_tlv_api { 680303628Ssbruno IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 681303628Ssbruno IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 682303628Ssbruno IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 683303628Ssbruno IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 684303628Ssbruno IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 685303628Ssbruno IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 686303628Ssbruno 687303628Ssbruno IWM_NUM_UCODE_TLV_API = 32 688303628Ssbruno}; 689303628Ssbruno 690303628Ssbruno#define IWM_UCODE_TLV_API_BITS \ 691303628Ssbruno "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 692303628Ssbruno 693303628Ssbruno/** 694303628Ssbruno * enum iwm_ucode_tlv_capa - ucode capabilities 695303628Ssbruno * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 696303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 697303628Ssbruno * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 698303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 699303628Ssbruno * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 700303628Ssbruno * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 701303628Ssbruno * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 702303628Ssbruno * tx power value into TPC Report action frame and Link Measurement Report 703303628Ssbruno * action frame 704303628Ssbruno * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 705303628Ssbruno * channel in DS parameter set element in probe requests. 706303628Ssbruno * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 707303628Ssbruno * probe requests. 708303628Ssbruno * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 709303628Ssbruno * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 710303628Ssbruno * which also implies support for the scheduler configuration command 711303628Ssbruno * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 712303628Ssbruno * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 713303628Ssbruno * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 714303628Ssbruno * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 715303628Ssbruno * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 716303628Ssbruno * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 717303628Ssbruno * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 718303628Ssbruno * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 719303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 720303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 721303628Ssbruno * sources for the MCC. This TLV bit is a future replacement to 722303628Ssbruno * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 723303628Ssbruno * is supported. 724303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 725303628Ssbruno * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 726303628Ssbruno * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 727303628Ssbruno * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 728303628Ssbruno * 0=no support) 729303628Ssbruno * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 730303628Ssbruno * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 731303628Ssbruno * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 732303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 733303628Ssbruno * antenna the beacon should be transmitted 734303628Ssbruno * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 735303628Ssbruno * from AP and will send it upon d0i3 exit. 736303628Ssbruno * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 737303628Ssbruno * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 738303628Ssbruno * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 739303628Ssbruno * thresholds reporting 740303628Ssbruno * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 741303628Ssbruno * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 742303628Ssbruno * regular image. 743303628Ssbruno * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 744303628Ssbruno * memory addresses from the firmware. 745303628Ssbruno * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 746303628Ssbruno * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 747303628Ssbruno * 0=no support) 748303628Ssbruno * 749303628Ssbruno * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 750303628Ssbruno */ 751303628Ssbrunoenum iwm_ucode_tlv_capa { 752303628Ssbruno IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 753303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 754303628Ssbruno IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 755303628Ssbruno IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 756303628Ssbruno IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 757303628Ssbruno IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 758303628Ssbruno IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 759303628Ssbruno IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 760303628Ssbruno IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 761303628Ssbruno IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 762303628Ssbruno IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 763303628Ssbruno IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 764303628Ssbruno IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 765303628Ssbruno IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 766303628Ssbruno IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 767303628Ssbruno IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 768303628Ssbruno IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 769303628Ssbruno IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 770303628Ssbruno IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 771303628Ssbruno IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 772303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 773303628Ssbruno IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 774303628Ssbruno IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 775303628Ssbruno IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 776303628Ssbruno IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 777303628Ssbruno IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 778303628Ssbruno IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 779303628Ssbruno IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 780303628Ssbruno IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 781303628Ssbruno IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 782303628Ssbruno IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 783303628Ssbruno IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 784303628Ssbruno IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 785303628Ssbruno IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 786303628Ssbruno IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 787303628Ssbruno IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 788303628Ssbruno IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 789303628Ssbruno IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 790303628Ssbruno IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 791303628Ssbruno 792303628Ssbruno IWM_NUM_UCODE_TLV_CAPA = 128 793303628Ssbruno}; 794303628Ssbruno 795286441Srpaulo/* The default calibrate table size if not specified by firmware file */ 796286441Srpaulo#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 797286441Srpaulo#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 798286441Srpaulo#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 799286441Srpaulo 800286441Srpaulo/* The default max probe length if not specified by the firmware file */ 801286441Srpaulo#define IWM_DEFAULT_MAX_PROBE_LENGTH 200 802286441Srpaulo 803286441Srpaulo/* 804286441Srpaulo * enumeration of ucode section. 805286441Srpaulo * This enumeration is used directly for older firmware (before 16.0). 806286441Srpaulo * For new firmware, there can be up to 4 sections (see below) but the 807286441Srpaulo * first one packaged into the firmware file is the DATA section and 808286441Srpaulo * some debugging code accesses that. 809286441Srpaulo */ 810286441Srpauloenum iwm_ucode_sec { 811286441Srpaulo IWM_UCODE_SECTION_DATA, 812286441Srpaulo IWM_UCODE_SECTION_INST, 813286441Srpaulo}; 814286441Srpaulo/* 815286441Srpaulo * For 16.0 uCode and above, there is no differentiation between sections, 816286441Srpaulo * just an offset to the HW address. 817286441Srpaulo */ 818303628Ssbruno#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 819303628Ssbruno#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 820286441Srpaulo 821286441Srpaulo/* uCode version contains 4 values: Major/Minor/API/Serial */ 822286441Srpaulo#define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 823286441Srpaulo#define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 824286441Srpaulo#define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 825286441Srpaulo#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 826286441Srpaulo 827286441Srpaulo/* 828286441Srpaulo * Calibration control struct. 829286441Srpaulo * Sent as part of the phy configuration command. 830286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 831286441Srpaulo * flow triggers. 832286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 833286441Srpaulo * event triggers. 834286441Srpaulo */ 835286441Srpaulostruct iwm_tlv_calib_ctrl { 836286441Srpaulo uint32_t flow_trigger; 837286441Srpaulo uint32_t event_trigger; 838286441Srpaulo} __packed; 839286441Srpaulo 840286441Srpauloenum iwm_fw_phy_cfg { 841286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 842286441Srpaulo IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 843286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 844286441Srpaulo IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 845286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 846286441Srpaulo IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 847286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 848286441Srpaulo IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 849286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 850286441Srpaulo IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 851286441Srpaulo}; 852286441Srpaulo 853286441Srpaulo#define IWM_UCODE_MAX_CS 1 854286441Srpaulo 855286441Srpaulo/** 856286441Srpaulo * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 857286441Srpaulo * @cipher: a cipher suite selector 858286441Srpaulo * @flags: cipher scheme flags (currently reserved for a future use) 859286441Srpaulo * @hdr_len: a size of MPDU security header 860286441Srpaulo * @pn_len: a size of PN 861286441Srpaulo * @pn_off: an offset of pn from the beginning of the security header 862286441Srpaulo * @key_idx_off: an offset of key index byte in the security header 863286441Srpaulo * @key_idx_mask: a bit mask of key_idx bits 864286441Srpaulo * @key_idx_shift: bit shift needed to get key_idx 865286441Srpaulo * @mic_len: mic length in bytes 866286441Srpaulo * @hw_cipher: a HW cipher index used in host commands 867286441Srpaulo */ 868286441Srpaulostruct iwm_fw_cipher_scheme { 869286441Srpaulo uint32_t cipher; 870286441Srpaulo uint8_t flags; 871286441Srpaulo uint8_t hdr_len; 872286441Srpaulo uint8_t pn_len; 873286441Srpaulo uint8_t pn_off; 874286441Srpaulo uint8_t key_idx_off; 875286441Srpaulo uint8_t key_idx_mask; 876286441Srpaulo uint8_t key_idx_shift; 877286441Srpaulo uint8_t mic_len; 878286441Srpaulo uint8_t hw_cipher; 879286441Srpaulo} __packed; 880286441Srpaulo 881286441Srpaulo/** 882286441Srpaulo * struct iwm_fw_cscheme_list - a cipher scheme list 883286441Srpaulo * @size: a number of entries 884286441Srpaulo * @cs: cipher scheme entries 885286441Srpaulo */ 886286441Srpaulostruct iwm_fw_cscheme_list { 887286441Srpaulo uint8_t size; 888286441Srpaulo struct iwm_fw_cipher_scheme cs[]; 889286441Srpaulo} __packed; 890286441Srpaulo 891286441Srpaulo/* 892286441Srpaulo * END iwl-fw.h 893286441Srpaulo */ 894286441Srpaulo 895286441Srpaulo/* 896286441Srpaulo * BEGIN iwl-fw-file.h 897286441Srpaulo */ 898286441Srpaulo 899286441Srpaulo/* v1/v2 uCode file layout */ 900286441Srpaulostruct iwm_ucode_header { 901286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 902286441Srpaulo union { 903286441Srpaulo struct { 904286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 905286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 906286441Srpaulo uint32_t init_size; /* bytes of init code */ 907286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 908286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 909286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 910286441Srpaulo } v1; 911286441Srpaulo struct { 912286441Srpaulo uint32_t build; /* build number */ 913286441Srpaulo uint32_t inst_size; /* bytes of runtime code */ 914286441Srpaulo uint32_t data_size; /* bytes of runtime data */ 915286441Srpaulo uint32_t init_size; /* bytes of init code */ 916286441Srpaulo uint32_t init_data_size; /* bytes of init data */ 917286441Srpaulo uint32_t boot_size; /* bytes of bootstrap code */ 918286441Srpaulo uint8_t data[0]; /* in same order as sizes */ 919286441Srpaulo } v2; 920286441Srpaulo } u; 921286441Srpaulo}; 922286441Srpaulo 923286441Srpaulo/* 924286441Srpaulo * new TLV uCode file layout 925286441Srpaulo * 926286441Srpaulo * The new TLV file format contains TLVs, that each specify 927286441Srpaulo * some piece of data. 928286441Srpaulo */ 929286441Srpaulo 930286441Srpauloenum iwm_ucode_tlv_type { 931286441Srpaulo IWM_UCODE_TLV_INVALID = 0, /* unused */ 932286441Srpaulo IWM_UCODE_TLV_INST = 1, 933286441Srpaulo IWM_UCODE_TLV_DATA = 2, 934286441Srpaulo IWM_UCODE_TLV_INIT = 3, 935286441Srpaulo IWM_UCODE_TLV_INIT_DATA = 4, 936286441Srpaulo IWM_UCODE_TLV_BOOT = 5, 937286441Srpaulo IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 938286441Srpaulo IWM_UCODE_TLV_PAN = 7, 939286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 940286441Srpaulo IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 941286441Srpaulo IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 942286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 943286441Srpaulo IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 944286441Srpaulo IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 945286441Srpaulo IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 946286441Srpaulo IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 947286441Srpaulo IWM_UCODE_TLV_WOWLAN_INST = 16, 948286441Srpaulo IWM_UCODE_TLV_WOWLAN_DATA = 17, 949286441Srpaulo IWM_UCODE_TLV_FLAGS = 18, 950286441Srpaulo IWM_UCODE_TLV_SEC_RT = 19, 951286441Srpaulo IWM_UCODE_TLV_SEC_INIT = 20, 952286441Srpaulo IWM_UCODE_TLV_SEC_WOWLAN = 21, 953286441Srpaulo IWM_UCODE_TLV_DEF_CALIB = 22, 954286441Srpaulo IWM_UCODE_TLV_PHY_SKU = 23, 955286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_RT = 24, 956286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 957286441Srpaulo IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 958286441Srpaulo IWM_UCODE_TLV_NUM_OF_CPU = 27, 959286441Srpaulo IWM_UCODE_TLV_CSCHEME = 28, 960286441Srpaulo 961286441Srpaulo /* 962286441Srpaulo * Following two are not in our base tag, but allow 963286441Srpaulo * handling ucode version 9. 964286441Srpaulo */ 965286441Srpaulo IWM_UCODE_TLV_API_CHANGES_SET = 29, 966303628Ssbruno IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 967303628Ssbruno 968303628Ssbruno IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 969303628Ssbruno IWM_UCODE_TLV_PAGING = 32, 970303628Ssbruno IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 971303628Ssbruno IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 972303628Ssbruno IWM_UCODE_TLV_FW_VERSION = 36, 973303628Ssbruno IWM_UCODE_TLV_FW_DBG_DEST = 38, 974303628Ssbruno IWM_UCODE_TLV_FW_DBG_CONF = 39, 975303628Ssbruno IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 976303628Ssbruno IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 977286441Srpaulo}; 978286441Srpaulo 979286441Srpaulostruct iwm_ucode_tlv { 980286441Srpaulo uint32_t type; /* see above */ 981286441Srpaulo uint32_t length; /* not including type/length fields */ 982286441Srpaulo uint8_t data[0]; 983286441Srpaulo}; 984286441Srpaulo 985303628Ssbrunostruct iwm_ucode_api { 986303628Ssbruno uint32_t api_index; 987303628Ssbruno uint32_t api_flags; 988303628Ssbruno} __packed; 989303628Ssbruno 990303628Ssbrunostruct iwm_ucode_capa { 991303628Ssbruno uint32_t api_index; 992303628Ssbruno uint32_t api_capa; 993303628Ssbruno} __packed; 994303628Ssbruno 995286441Srpaulo#define IWM_TLV_UCODE_MAGIC 0x0a4c5749 996286441Srpaulo 997286441Srpaulostruct iwm_tlv_ucode_header { 998286441Srpaulo /* 999286441Srpaulo * The TLV style ucode header is distinguished from 1000286441Srpaulo * the v1/v2 style header by first four bytes being 1001286441Srpaulo * zero, as such is an invalid combination of 1002286441Srpaulo * major/minor/API/serial versions. 1003286441Srpaulo */ 1004286441Srpaulo uint32_t zero; 1005286441Srpaulo uint32_t magic; 1006286441Srpaulo uint8_t human_readable[64]; 1007286441Srpaulo uint32_t ver; /* major/minor/API/serial */ 1008286441Srpaulo uint32_t build; 1009286441Srpaulo uint64_t ignore; 1010286441Srpaulo /* 1011286441Srpaulo * The data contained herein has a TLV layout, 1012286441Srpaulo * see above for the TLV header and types. 1013286441Srpaulo * Note that each TLV is padded to a length 1014286441Srpaulo * that is a multiple of 4 for alignment. 1015286441Srpaulo */ 1016286441Srpaulo uint8_t data[0]; 1017286441Srpaulo}; 1018286441Srpaulo 1019286441Srpaulo/* 1020286441Srpaulo * END iwl-fw-file.h 1021286441Srpaulo */ 1022286441Srpaulo 1023286441Srpaulo/* 1024286441Srpaulo * BEGIN iwl-prph.h 1025286441Srpaulo */ 1026286441Srpaulo 1027286441Srpaulo/* 1028286441Srpaulo * Registers in this file are internal, not PCI bus memory mapped. 1029286441Srpaulo * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1030286441Srpaulo */ 1031286441Srpaulo#define IWM_PRPH_BASE (0x00000) 1032286441Srpaulo#define IWM_PRPH_END (0xFFFFF) 1033286441Srpaulo 1034286441Srpaulo/* APMG (power management) constants */ 1035286441Srpaulo#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1036286441Srpaulo#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1037286441Srpaulo#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1038286441Srpaulo#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1039286441Srpaulo#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1040286441Srpaulo#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1041286441Srpaulo#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1042286441Srpaulo#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1043286441Srpaulo#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1044286441Srpaulo#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1045286441Srpaulo#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1046286441Srpaulo 1047286441Srpaulo#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1048286441Srpaulo#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1049286441Srpaulo#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1050286441Srpaulo 1051286441Srpaulo#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1052286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1053286441Srpaulo#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1054286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1055286441Srpaulo#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1056286441Srpaulo#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1057286441Srpaulo#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1058286441Srpaulo 1059286441Srpaulo#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1060286441Srpaulo 1061286441Srpaulo#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1062286441Srpaulo 1063286441Srpaulo/* Device system time */ 1064286441Srpaulo#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1065286441Srpaulo 1066286441Srpaulo/* Device NMI register */ 1067303628Ssbruno#define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1068303628Ssbruno#define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1069303628Ssbruno#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1070303628Ssbruno#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1071303628Ssbruno#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1072286441Srpaulo 1073303628Ssbruno/* 1074303628Ssbruno * Device reset for family 8000 1075303628Ssbruno * write to bit 24 in order to reset the CPU 1076303628Ssbruno */ 1077303628Ssbruno#define IWM_RELEASE_CPU_RESET 0x300c 1078303628Ssbruno#define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1079303628Ssbruno 1080303628Ssbruno 1081286441Srpaulo/***************************************************************************** 1082286441Srpaulo * 7000/3000 series SHR DTS addresses * 1083286441Srpaulo *****************************************************************************/ 1084286441Srpaulo 1085286441Srpaulo#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1086286441Srpaulo#define IWM_DTSC_CFG_MODE (0x00a10604) 1087286441Srpaulo#define IWM_DTSC_VREF_AVG (0x00a10648) 1088286441Srpaulo#define IWM_DTSC_VREF5_AVG (0x00a1064c) 1089286441Srpaulo#define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1090286441Srpaulo#define IWM_DTSC_PTAT_AVG (0x00a10650) 1091286441Srpaulo 1092286441Srpaulo 1093286441Srpaulo/** 1094286441Srpaulo * Tx Scheduler 1095286441Srpaulo * 1096286441Srpaulo * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1097286441Srpaulo * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1098286441Srpaulo * host DRAM. It steers each frame's Tx command (which contains the frame 1099286441Srpaulo * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1100286441Srpaulo * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1101286441Srpaulo * but one DMA channel may take input from several queues. 1102286441Srpaulo * 1103286441Srpaulo * Tx DMA FIFOs have dedicated purposes. 1104286441Srpaulo * 1105286441Srpaulo * For 5000 series and up, they are used differently 1106286441Srpaulo * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1107286441Srpaulo * 1108286441Srpaulo * 0 -- EDCA BK (background) frames, lowest priority 1109286441Srpaulo * 1 -- EDCA BE (best effort) frames, normal priority 1110286441Srpaulo * 2 -- EDCA VI (video) frames, higher priority 1111286441Srpaulo * 3 -- EDCA VO (voice) and management frames, highest priority 1112286441Srpaulo * 4 -- unused 1113286441Srpaulo * 5 -- unused 1114286441Srpaulo * 6 -- unused 1115286441Srpaulo * 7 -- Commands 1116286441Srpaulo * 1117286441Srpaulo * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1118286441Srpaulo * In addition, driver can map the remaining queues to Tx DMA/FIFO 1119286441Srpaulo * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1120286441Srpaulo * 1121286441Srpaulo * The driver sets up each queue to work in one of two modes: 1122286441Srpaulo * 1123286441Srpaulo * 1) Scheduler-Ack, in which the scheduler automatically supports a 1124286441Srpaulo * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1125286441Srpaulo * contains TFDs for a unique combination of Recipient Address (RA) 1126286441Srpaulo * and Traffic Identifier (TID), that is, traffic of a given 1127286441Srpaulo * Quality-Of-Service (QOS) priority, destined for a single station. 1128286441Srpaulo * 1129286441Srpaulo * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1130286441Srpaulo * each frame within the BA window, including whether it's been transmitted, 1131286441Srpaulo * and whether it's been acknowledged by the receiving station. The device 1132286441Srpaulo * automatically processes block-acks received from the receiving STA, 1133286441Srpaulo * and reschedules un-acked frames to be retransmitted (successful 1134286441Srpaulo * Tx completion may end up being out-of-order). 1135286441Srpaulo * 1136286441Srpaulo * The driver must maintain the queue's Byte Count table in host DRAM 1137286441Srpaulo * for this mode. 1138286441Srpaulo * This mode does not support fragmentation. 1139286441Srpaulo * 1140286441Srpaulo * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1141286441Srpaulo * The device may automatically retry Tx, but will retry only one frame 1142286441Srpaulo * at a time, until receiving ACK from receiving station, or reaching 1143286441Srpaulo * retry limit and giving up. 1144286441Srpaulo * 1145286441Srpaulo * The command queue (#4/#9) must use this mode! 1146286441Srpaulo * This mode does not require use of the Byte Count table in host DRAM. 1147286441Srpaulo * 1148286441Srpaulo * Driver controls scheduler operation via 3 means: 1149286441Srpaulo * 1) Scheduler registers 1150286441Srpaulo * 2) Shared scheduler data base in internal SRAM 1151286441Srpaulo * 3) Shared data in host DRAM 1152286441Srpaulo * 1153286441Srpaulo * Initialization: 1154286441Srpaulo * 1155286441Srpaulo * When loading, driver should allocate memory for: 1156286441Srpaulo * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1157286441Srpaulo * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1158286441Srpaulo * (1024 bytes for each queue). 1159286441Srpaulo * 1160286441Srpaulo * After receiving "Alive" response from uCode, driver must initialize 1161286441Srpaulo * the scheduler (especially for queue #4/#9, the command queue, otherwise 1162286441Srpaulo * the driver can't issue commands!): 1163286441Srpaulo */ 1164286441Srpaulo#define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1165286441Srpaulo 1166286441Srpaulo/** 1167286441Srpaulo * Max Tx window size is the max number of contiguous TFDs that the scheduler 1168286441Srpaulo * can keep track of at one time when creating block-ack chains of frames. 1169286441Srpaulo * Note that "64" matches the number of ack bits in a block-ack packet. 1170286441Srpaulo */ 1171286441Srpaulo#define IWM_SCD_WIN_SIZE 64 1172286441Srpaulo#define IWM_SCD_FRAME_LIMIT 64 1173286441Srpaulo 1174286441Srpaulo#define IWM_SCD_TXFIFO_POS_TID (0) 1175286441Srpaulo#define IWM_SCD_TXFIFO_POS_RA (4) 1176286441Srpaulo#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1177286441Srpaulo 1178286441Srpaulo/* agn SCD */ 1179286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1180286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1181286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1182286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1183286441Srpaulo#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1184286441Srpaulo 1185286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1186286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1187286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1188286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1189286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1190286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1191286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1192286441Srpaulo#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1193303628Ssbruno#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1194303628Ssbruno#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1195286441Srpaulo 1196286441Srpaulo/* Context Data */ 1197286441Srpaulo#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1198286441Srpaulo#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1199286441Srpaulo 1200286441Srpaulo/* Tx status */ 1201286441Srpaulo#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1202286441Srpaulo#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1203286441Srpaulo 1204286441Srpaulo/* Translation Data */ 1205286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1206286441Srpaulo#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1207286441Srpaulo 1208286441Srpaulo#define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1209286441Srpaulo (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1210286441Srpaulo 1211286441Srpaulo#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1212286441Srpaulo (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1213286441Srpaulo 1214286441Srpaulo#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1215286441Srpaulo ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1216286441Srpaulo 1217286441Srpaulo#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1218286441Srpaulo 1219286441Srpaulo#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1220286441Srpaulo#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1221286441Srpaulo#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1222286441Srpaulo#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1223286441Srpaulo#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1224286441Srpaulo#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1225286441Srpaulo#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1226286441Srpaulo#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1227286441Srpaulo#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1228303628Ssbruno#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1229303628Ssbruno#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1230286441Srpaulo 1231286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1232286441Srpaulo{ 1233286441Srpaulo if (chnl < 20) 1234286441Srpaulo return IWM_SCD_BASE + 0x18 + chnl * 4; 1235286441Srpaulo return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1236286441Srpaulo} 1237286441Srpaulo 1238286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1239286441Srpaulo{ 1240286441Srpaulo if (chnl < 20) 1241286441Srpaulo return IWM_SCD_BASE + 0x68 + chnl * 4; 1242286441Srpaulo return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1243286441Srpaulo} 1244286441Srpaulo 1245286441Srpaulostatic inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1246286441Srpaulo{ 1247286441Srpaulo if (chnl < 20) 1248286441Srpaulo return IWM_SCD_BASE + 0x10c + chnl * 4; 1249286441Srpaulo return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1250286441Srpaulo} 1251286441Srpaulo 1252286441Srpaulo/*********************** END TX SCHEDULER *************************************/ 1253286441Srpaulo 1254286441Srpaulo/* Oscillator clock */ 1255286441Srpaulo#define IWM_OSC_CLK (0xa04068) 1256286441Srpaulo#define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1257286441Srpaulo 1258286441Srpaulo/* 1259286441Srpaulo * END iwl-prph.h 1260286441Srpaulo */ 1261286441Srpaulo 1262286441Srpaulo/* 1263286441Srpaulo * BEGIN iwl-fh.h 1264286441Srpaulo */ 1265286441Srpaulo 1266286441Srpaulo/****************************/ 1267286441Srpaulo/* Flow Handler Definitions */ 1268286441Srpaulo/****************************/ 1269286441Srpaulo 1270286441Srpaulo/** 1271286441Srpaulo * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1272286441Srpaulo * Addresses are offsets from device's PCI hardware base address. 1273286441Srpaulo */ 1274286441Srpaulo#define IWM_FH_MEM_LOWER_BOUND (0x1000) 1275286441Srpaulo#define IWM_FH_MEM_UPPER_BOUND (0x2000) 1276286441Srpaulo 1277286441Srpaulo/** 1278286441Srpaulo * Keep-Warm (KW) buffer base address. 1279286441Srpaulo * 1280286441Srpaulo * Driver must allocate a 4KByte buffer that is for keeping the 1281286441Srpaulo * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1282286441Srpaulo * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1283286441Srpaulo * from going into a power-savings mode that would cause higher DRAM latency, 1284286441Srpaulo * and possible data over/under-runs, before all Tx/Rx is complete. 1285286441Srpaulo * 1286286441Srpaulo * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1287286441Srpaulo * of the buffer, which must be 4K aligned. Once this is set up, the device 1288286441Srpaulo * automatically invokes keep-warm accesses when normal accesses might not 1289286441Srpaulo * be sufficient to maintain fast DRAM response. 1290286441Srpaulo * 1291286441Srpaulo * Bit fields: 1292286441Srpaulo * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1293286441Srpaulo */ 1294286441Srpaulo#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1295286441Srpaulo 1296286441Srpaulo 1297286441Srpaulo/** 1298286441Srpaulo * TFD Circular Buffers Base (CBBC) addresses 1299286441Srpaulo * 1300286441Srpaulo * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1301286441Srpaulo * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1302286441Srpaulo * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1303286441Srpaulo * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1304286441Srpaulo * aligned (address bits 0-7 must be 0). 1305286441Srpaulo * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1306286441Srpaulo * for them are in different places. 1307286441Srpaulo * 1308286441Srpaulo * Bit fields in each pointer register: 1309286441Srpaulo * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1310286441Srpaulo */ 1311286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1312286441Srpaulo#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1313286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1314286441Srpaulo#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1315286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1316286441Srpaulo#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1317286441Srpaulo 1318286441Srpaulo/* Find TFD CB base pointer for given queue */ 1319286441Srpaulostatic inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1320286441Srpaulo{ 1321286441Srpaulo if (chnl < 16) 1322286441Srpaulo return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1323286441Srpaulo if (chnl < 20) 1324286441Srpaulo return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1325286441Srpaulo return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1326286441Srpaulo} 1327286441Srpaulo 1328286441Srpaulo 1329286441Srpaulo/** 1330286441Srpaulo * Rx SRAM Control and Status Registers (RSCSR) 1331286441Srpaulo * 1332286441Srpaulo * These registers provide handshake between driver and device for the Rx queue 1333286441Srpaulo * (this queue handles *all* command responses, notifications, Rx data, etc. 1334286441Srpaulo * sent from uCode to host driver). Unlike Tx, there is only one Rx 1335286441Srpaulo * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1336286441Srpaulo * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1337286441Srpaulo * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1338286441Srpaulo * mapping between RBDs and RBs. 1339286441Srpaulo * 1340286441Srpaulo * Driver must allocate host DRAM memory for the following, and set the 1341286441Srpaulo * physical address of each into device registers: 1342286441Srpaulo * 1343286441Srpaulo * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1344286441Srpaulo * entries (although any power of 2, up to 4096, is selectable by driver). 1345286441Srpaulo * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1346286441Srpaulo * (typically 4K, although 8K or 16K are also selectable by driver). 1347286441Srpaulo * Driver sets up RB size and number of RBDs in the CB via Rx config 1348286441Srpaulo * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1349286441Srpaulo * 1350286441Srpaulo * Bit fields within one RBD: 1351286441Srpaulo * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1352286441Srpaulo * 1353286441Srpaulo * Driver sets physical address [35:8] of base of RBD circular buffer 1354286441Srpaulo * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1355286441Srpaulo * 1356286441Srpaulo * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1357286441Srpaulo * (RBs) have been filled, via a "write pointer", actually the index of 1358286441Srpaulo * the RB's corresponding RBD within the circular buffer. Driver sets 1359286441Srpaulo * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1360286441Srpaulo * 1361286441Srpaulo * Bit fields in lower dword of Rx status buffer (upper dword not used 1362286441Srpaulo * by driver: 1363286441Srpaulo * 31-12: Not used by driver 1364286441Srpaulo * 11- 0: Index of last filled Rx buffer descriptor 1365286441Srpaulo * (device writes, driver reads this value) 1366286441Srpaulo * 1367286441Srpaulo * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1368286441Srpaulo * enter pointers to these RBs into contiguous RBD circular buffer entries, 1369286441Srpaulo * and update the device's "write" index register, 1370286441Srpaulo * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1371286441Srpaulo * 1372286441Srpaulo * This "write" index corresponds to the *next* RBD that the driver will make 1373286441Srpaulo * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1374286441Srpaulo * the circular buffer. This value should initially be 0 (before preparing any 1375286441Srpaulo * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1376286441Srpaulo * wrap back to 0 at the end of the circular buffer (but don't wrap before 1377286441Srpaulo * "read" index has advanced past 1! See below). 1378286441Srpaulo * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1379286441Srpaulo * 1380286441Srpaulo * As the device fills RBs (referenced from contiguous RBDs within the circular 1381286441Srpaulo * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1382286441Srpaulo * to tell the driver the index of the latest filled RBD. The driver must 1383286441Srpaulo * read this "read" index from DRAM after receiving an Rx interrupt from device 1384286441Srpaulo * 1385286441Srpaulo * The driver must also internally keep track of a third index, which is the 1386286441Srpaulo * next RBD to process. When receiving an Rx interrupt, driver should process 1387286441Srpaulo * all filled but unprocessed RBs up to, but not including, the RB 1388286441Srpaulo * corresponding to the "read" index. For example, if "read" index becomes "1", 1389286441Srpaulo * driver may process the RB pointed to by RBD 0. Depending on volume of 1390286441Srpaulo * traffic, there may be many RBs to process. 1391286441Srpaulo * 1392286441Srpaulo * If read index == write index, device thinks there is no room to put new data. 1393286441Srpaulo * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1394286441Srpaulo * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1395286441Srpaulo * and "read" indexes; that is, make sure that there are no more than 254 1396286441Srpaulo * buffers waiting to be filled. 1397286441Srpaulo */ 1398286441Srpaulo#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1399286441Srpaulo#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1400286441Srpaulo#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1401286441Srpaulo 1402286441Srpaulo/** 1403286441Srpaulo * Physical base address of 8-byte Rx Status buffer. 1404286441Srpaulo * Bit fields: 1405286441Srpaulo * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1406286441Srpaulo */ 1407286441Srpaulo#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1408286441Srpaulo 1409286441Srpaulo/** 1410286441Srpaulo * Physical base address of Rx Buffer Descriptor Circular Buffer. 1411286441Srpaulo * Bit fields: 1412286441Srpaulo * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1413286441Srpaulo */ 1414286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1415286441Srpaulo 1416286441Srpaulo/** 1417286441Srpaulo * Rx write pointer (index, really!). 1418286441Srpaulo * Bit fields: 1419286441Srpaulo * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1420286441Srpaulo * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1421286441Srpaulo */ 1422286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1423286441Srpaulo#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1424286441Srpaulo 1425286441Srpaulo#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1426286441Srpaulo#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1427286441Srpaulo 1428286441Srpaulo/** 1429286441Srpaulo * Rx Config/Status Registers (RCSR) 1430286441Srpaulo * Rx Config Reg for channel 0 (only channel used) 1431286441Srpaulo * 1432286441Srpaulo * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1433286441Srpaulo * normal operation (see bit fields). 1434286441Srpaulo * 1435286441Srpaulo * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1436286441Srpaulo * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1437286441Srpaulo * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1438286441Srpaulo * 1439286441Srpaulo * Bit fields: 1440286441Srpaulo * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1441286441Srpaulo * '10' operate normally 1442286441Srpaulo * 29-24: reserved 1443286441Srpaulo * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1444286441Srpaulo * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1445286441Srpaulo * 19-18: reserved 1446286441Srpaulo * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1447286441Srpaulo * '10' 12K, '11' 16K. 1448286441Srpaulo * 15-14: reserved 1449286441Srpaulo * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1450286441Srpaulo * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1451286441Srpaulo * typical value 0x10 (about 1/2 msec) 1452286441Srpaulo * 3- 0: reserved 1453286441Srpaulo */ 1454286441Srpaulo#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1455286441Srpaulo#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1456286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1457286441Srpaulo 1458286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1459286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1460286441Srpaulo#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1461286441Srpaulo 1462286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1463286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1464286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1465286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1466286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1467286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1468286441Srpaulo 1469286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1470286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1471286441Srpaulo#define IWM_RX_RB_TIMEOUT (0x11) 1472286441Srpaulo 1473286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1474286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1475286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1476286441Srpaulo 1477286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1478286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1479286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1480286441Srpaulo#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1481286441Srpaulo 1482286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1483286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1484286441Srpaulo#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1485286441Srpaulo 1486286441Srpaulo/** 1487286441Srpaulo * Rx Shared Status Registers (RSSR) 1488286441Srpaulo * 1489286441Srpaulo * After stopping Rx DMA channel (writing 0 to 1490286441Srpaulo * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1491286441Srpaulo * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1492286441Srpaulo * 1493286441Srpaulo * Bit fields: 1494286441Srpaulo * 24: 1 = Channel 0 is idle 1495286441Srpaulo * 1496286441Srpaulo * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1497286441Srpaulo * contain default values that should not be altered by the driver. 1498286441Srpaulo */ 1499286441Srpaulo#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1500286441Srpaulo#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1501286441Srpaulo 1502286441Srpaulo#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1503286441Srpaulo#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1504286441Srpaulo#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1505286441Srpaulo (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1506286441Srpaulo 1507286441Srpaulo#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1508286441Srpaulo 1509286441Srpaulo#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1510286441Srpaulo 1511286441Srpaulo/* TFDB Area - TFDs buffer table */ 1512286441Srpaulo#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1513286441Srpaulo#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1514286441Srpaulo#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1515286441Srpaulo#define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1516286441Srpaulo#define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1517286441Srpaulo 1518286441Srpaulo/** 1519286441Srpaulo * Transmit DMA Channel Control/Status Registers (TCSR) 1520286441Srpaulo * 1521286441Srpaulo * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1522286441Srpaulo * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1523286441Srpaulo * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1524286441Srpaulo * 1525286441Srpaulo * To use a Tx DMA channel, driver must initialize its 1526286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1527286441Srpaulo * 1528286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1529286441Srpaulo * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1530286441Srpaulo * 1531286441Srpaulo * All other bits should be 0. 1532286441Srpaulo * 1533286441Srpaulo * Bit fields: 1534286441Srpaulo * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1535286441Srpaulo * '10' operate normally 1536286441Srpaulo * 29- 4: Reserved, set to "0" 1537286441Srpaulo * 3: Enable internal DMA requests (1, normal operation), disable (0) 1538286441Srpaulo * 2- 0: Reserved, set to "0" 1539286441Srpaulo */ 1540286441Srpaulo#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1541286441Srpaulo#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1542286441Srpaulo 1543286441Srpaulo/* Find Control/Status reg for given Tx DMA/FIFO channel */ 1544286441Srpaulo#define IWM_FH_TCSR_CHNL_NUM (8) 1545286441Srpaulo 1546286441Srpaulo/* TCSR: tx_config register values */ 1547286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1548286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1549286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1550286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1551286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1552286441Srpaulo (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1553286441Srpaulo 1554286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1555286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1556286441Srpaulo 1557286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1558286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1559286441Srpaulo 1560286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1561286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1562286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1563286441Srpaulo 1564286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1565286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1566286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1567286441Srpaulo 1568286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1569286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1570286441Srpaulo#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1571286441Srpaulo 1572286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1573286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1574286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1575286441Srpaulo 1576286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1577286441Srpaulo#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1578286441Srpaulo 1579286441Srpaulo/** 1580286441Srpaulo * Tx Shared Status Registers (TSSR) 1581286441Srpaulo * 1582286441Srpaulo * After stopping Tx DMA channel (writing 0 to 1583286441Srpaulo * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1584286441Srpaulo * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1585286441Srpaulo * (channel's buffers empty | no pending requests). 1586286441Srpaulo * 1587286441Srpaulo * Bit fields: 1588286441Srpaulo * 31-24: 1 = Channel buffers empty (channel 7:0) 1589286441Srpaulo * 23-16: 1 = No pending requests (channel 7:0) 1590286441Srpaulo */ 1591286441Srpaulo#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1592286441Srpaulo#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1593286441Srpaulo 1594286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1595286441Srpaulo 1596286441Srpaulo/** 1597286441Srpaulo * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1598286441Srpaulo * 31: Indicates an address error when accessed to internal memory 1599286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1600286441Srpaulo * 30: Indicates that Host did not send the expected number of dwords to FH 1601286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1602286441Srpaulo * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1603286441Srpaulo * command was received from the scheduler while the TRB was already full 1604286441Srpaulo * with previous command 1605286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1606286441Srpaulo * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1607286441Srpaulo * bit is set, it indicates that the FH has received a full indication 1608286441Srpaulo * from the RTC TxFIFO and the current value of the TxCredit counter was 1609286441Srpaulo * not equal to zero. This mean that the credit mechanism was not 1610286441Srpaulo * synchronized to the TxFIFO status 1611286441Srpaulo * uCode/driver must write "1" in order to clear this flag 1612286441Srpaulo */ 1613286441Srpaulo#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1614286441Srpaulo#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1615286441Srpaulo 1616286441Srpaulo#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1617286441Srpaulo 1618286441Srpaulo/* Tx service channels */ 1619286441Srpaulo#define IWM_FH_SRVC_CHNL (9) 1620286441Srpaulo#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1621286441Srpaulo#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1622286441Srpaulo#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1623286441Srpaulo (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1624286441Srpaulo 1625286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1626286441Srpaulo#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1627286441Srpaulo (_chan) * 4) 1628286441Srpaulo 1629286441Srpaulo/* Instruct FH to increment the retry count of a packet when 1630286441Srpaulo * it is brought from the memory to TX-FIFO 1631286441Srpaulo */ 1632286441Srpaulo#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1633286441Srpaulo 1634286441Srpaulo#define IWM_RX_QUEUE_SIZE 256 1635286441Srpaulo#define IWM_RX_QUEUE_MASK 255 1636286441Srpaulo#define IWM_RX_QUEUE_SIZE_LOG 8 1637286441Srpaulo 1638286441Srpaulo/* 1639286441Srpaulo * RX related structures and functions 1640286441Srpaulo */ 1641286441Srpaulo#define IWM_RX_FREE_BUFFERS 64 1642286441Srpaulo#define IWM_RX_LOW_WATERMARK 8 1643286441Srpaulo 1644286441Srpaulo/** 1645286441Srpaulo * struct iwm_rb_status - reseve buffer status 1646286441Srpaulo * host memory mapped FH registers 1647286441Srpaulo * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1648286441Srpaulo * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1649286441Srpaulo * @finished_rb_num [0:11] - Indicates the index of the current RB 1650286441Srpaulo * in which the last frame was written to 1651286441Srpaulo * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1652286441Srpaulo * which was transferred 1653286441Srpaulo */ 1654286441Srpaulostruct iwm_rb_status { 1655286441Srpaulo uint16_t closed_rb_num; 1656286441Srpaulo uint16_t closed_fr_num; 1657286441Srpaulo uint16_t finished_rb_num; 1658286441Srpaulo uint16_t finished_fr_nam; 1659286441Srpaulo uint32_t unused; 1660286441Srpaulo} __packed; 1661286441Srpaulo 1662286441Srpaulo 1663286441Srpaulo#define IWM_TFD_QUEUE_SIZE_MAX (256) 1664286441Srpaulo#define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1665286441Srpaulo#define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1666286441Srpaulo IWM_TFD_QUEUE_SIZE_BC_DUP) 1667286441Srpaulo#define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1668286441Srpaulo#define IWM_NUM_OF_TBS 20 1669286441Srpaulo 1670286441Srpaulostatic inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1671286441Srpaulo{ 1672286441Srpaulo return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1673286441Srpaulo} 1674286441Srpaulo/** 1675286441Srpaulo * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1676286441Srpaulo * 1677286441Srpaulo * This structure contains dma address and length of transmission address 1678286441Srpaulo * 1679286441Srpaulo * @lo: low [31:0] portion of the dma address of TX buffer 1680286441Srpaulo * every even is unaligned on 16 bit boundary 1681286441Srpaulo * @hi_n_len 0-3 [35:32] portion of dma 1682286441Srpaulo * 4-15 length of the tx buffer 1683286441Srpaulo */ 1684286441Srpaulostruct iwm_tfd_tb { 1685286441Srpaulo uint32_t lo; 1686286441Srpaulo uint16_t hi_n_len; 1687286441Srpaulo} __packed; 1688286441Srpaulo 1689286441Srpaulo/** 1690286441Srpaulo * struct iwm_tfd 1691286441Srpaulo * 1692286441Srpaulo * Transmit Frame Descriptor (TFD) 1693286441Srpaulo * 1694286441Srpaulo * @ __reserved1[3] reserved 1695286441Srpaulo * @ num_tbs 0-4 number of active tbs 1696286441Srpaulo * 5 reserved 1697286441Srpaulo * 6-7 padding (not used) 1698286441Srpaulo * @ tbs[20] transmit frame buffer descriptors 1699286441Srpaulo * @ __pad padding 1700286441Srpaulo * 1701286441Srpaulo * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1702286441Srpaulo * Both driver and device share these circular buffers, each of which must be 1703286441Srpaulo * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1704286441Srpaulo * 1705286441Srpaulo * Driver must indicate the physical address of the base of each 1706286441Srpaulo * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1707286441Srpaulo * 1708286441Srpaulo * Each TFD contains pointer/size information for up to 20 data buffers 1709286441Srpaulo * in host DRAM. These buffers collectively contain the (one) frame described 1710286441Srpaulo * by the TFD. Each buffer must be a single contiguous block of memory within 1711286441Srpaulo * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1712286441Srpaulo * of (4K - 4). The concatenates all of a TFD's buffers into a single 1713286441Srpaulo * Tx frame, up to 8 KBytes in size. 1714286441Srpaulo * 1715286441Srpaulo * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1716286441Srpaulo */ 1717286441Srpaulostruct iwm_tfd { 1718286441Srpaulo uint8_t __reserved1[3]; 1719286441Srpaulo uint8_t num_tbs; 1720286441Srpaulo struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1721286441Srpaulo uint32_t __pad; 1722286441Srpaulo} __packed; 1723286441Srpaulo 1724286441Srpaulo/* Keep Warm Size */ 1725286441Srpaulo#define IWM_KW_SIZE 0x1000 /* 4k */ 1726286441Srpaulo 1727286441Srpaulo/* Fixed (non-configurable) rx data from phy */ 1728286441Srpaulo 1729286441Srpaulo/** 1730286441Srpaulo * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1731286441Srpaulo * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1732286441Srpaulo * @tfd_offset 0-12 - tx command byte count 1733286441Srpaulo * 12-16 - station index 1734286441Srpaulo */ 1735286441Srpaulostruct iwm_agn_scd_bc_tbl { 1736286441Srpaulo uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1737286441Srpaulo} __packed; 1738286441Srpaulo 1739286441Srpaulo/* 1740286441Srpaulo * END iwl-fh.h 1741286441Srpaulo */ 1742286441Srpaulo 1743286441Srpaulo/* 1744286441Srpaulo * BEGIN mvm/fw-api.h 1745286441Srpaulo */ 1746286441Srpaulo 1747303628Ssbruno/* Maximum number of Tx queues. */ 1748303628Ssbruno#define IWM_MVM_MAX_QUEUES 31 1749286441Srpaulo 1750286441Srpaulo/* Tx queue numbers */ 1751286441Srpauloenum { 1752286441Srpaulo IWM_MVM_OFFCHANNEL_QUEUE = 8, 1753286441Srpaulo IWM_MVM_CMD_QUEUE = 9, 1754303628Ssbruno IWM_MVM_AUX_QUEUE = 15, 1755286441Srpaulo}; 1756286441Srpaulo 1757301192Sadrianenum iwm_mvm_tx_fifo { 1758301192Sadrian IWM_MVM_TX_FIFO_BK = 0, 1759301192Sadrian IWM_MVM_TX_FIFO_BE, 1760301192Sadrian IWM_MVM_TX_FIFO_VI, 1761301192Sadrian IWM_MVM_TX_FIFO_VO, 1762301192Sadrian IWM_MVM_TX_FIFO_MCAST = 5, 1763301192Sadrian IWM_MVM_TX_FIFO_CMD = 7, 1764301192Sadrian}; 1765286441Srpaulo 1766286441Srpaulo#define IWM_MVM_STATION_COUNT 16 1767286441Srpaulo 1768286441Srpaulo/* commands */ 1769286441Srpauloenum { 1770286441Srpaulo IWM_MVM_ALIVE = 0x1, 1771286441Srpaulo IWM_REPLY_ERROR = 0x2, 1772286441Srpaulo 1773286441Srpaulo IWM_INIT_COMPLETE_NOTIF = 0x4, 1774286441Srpaulo 1775286441Srpaulo /* PHY context commands */ 1776286441Srpaulo IWM_PHY_CONTEXT_CMD = 0x8, 1777286441Srpaulo IWM_DBG_CFG = 0x9, 1778286441Srpaulo 1779303628Ssbruno /* UMAC scan commands */ 1780303628Ssbruno IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1781303628Ssbruno IWM_SCAN_CFG_CMD = 0xc, 1782303628Ssbruno IWM_SCAN_REQ_UMAC = 0xd, 1783303628Ssbruno IWM_SCAN_ABORT_UMAC = 0xe, 1784303628Ssbruno IWM_SCAN_COMPLETE_UMAC = 0xf, 1785303628Ssbruno 1786286441Srpaulo /* station table */ 1787286441Srpaulo IWM_ADD_STA_KEY = 0x17, 1788286441Srpaulo IWM_ADD_STA = 0x18, 1789286441Srpaulo IWM_REMOVE_STA = 0x19, 1790286441Srpaulo 1791286441Srpaulo /* TX */ 1792286441Srpaulo IWM_TX_CMD = 0x1c, 1793286441Srpaulo IWM_TXPATH_FLUSH = 0x1e, 1794286441Srpaulo IWM_MGMT_MCAST_KEY = 0x1f, 1795286441Srpaulo 1796303628Ssbruno /* scheduler config */ 1797303628Ssbruno IWM_SCD_QUEUE_CFG = 0x1d, 1798303628Ssbruno 1799286441Srpaulo /* global key */ 1800286441Srpaulo IWM_WEP_KEY = 0x20, 1801286441Srpaulo 1802286441Srpaulo /* MAC and Binding commands */ 1803286441Srpaulo IWM_MAC_CONTEXT_CMD = 0x28, 1804286441Srpaulo IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1805286441Srpaulo IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1806286441Srpaulo IWM_BINDING_CONTEXT_CMD = 0x2b, 1807286441Srpaulo IWM_TIME_QUOTA_CMD = 0x2c, 1808286441Srpaulo IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1809286441Srpaulo 1810286441Srpaulo IWM_LQ_CMD = 0x4e, 1811286441Srpaulo 1812286441Srpaulo /* Calibration */ 1813286441Srpaulo IWM_TEMPERATURE_NOTIFICATION = 0x62, 1814286441Srpaulo IWM_CALIBRATION_CFG_CMD = 0x65, 1815286441Srpaulo IWM_CALIBRATION_RES_NOTIFICATION = 0x66, 1816286441Srpaulo IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67, 1817286441Srpaulo IWM_RADIO_VERSION_NOTIFICATION = 0x68, 1818286441Srpaulo 1819286441Srpaulo /* Scan offload */ 1820286441Srpaulo IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1821286441Srpaulo IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1822303628Ssbruno IWM_HOT_SPOT_CMD = 0x53, 1823303628Ssbruno IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1824303628Ssbruno IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1825286441Srpaulo IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1826286441Srpaulo IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1827303628Ssbruno IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1828286441Srpaulo 1829286441Srpaulo /* Phy */ 1830286441Srpaulo IWM_PHY_CONFIGURATION_CMD = 0x6a, 1831286441Srpaulo IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1832286441Srpaulo /* IWM_PHY_DB_CMD = 0x6c, */ 1833286441Srpaulo 1834286441Srpaulo /* Power - legacy power table command */ 1835286441Srpaulo IWM_POWER_TABLE_CMD = 0x77, 1836286441Srpaulo IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1837286441Srpaulo 1838286441Srpaulo /* Thermal Throttling*/ 1839286441Srpaulo IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1840286441Srpaulo 1841286441Srpaulo /* Scanning */ 1842286441Srpaulo IWM_SCAN_REQUEST_CMD = 0x80, 1843286441Srpaulo IWM_SCAN_ABORT_CMD = 0x81, 1844286441Srpaulo IWM_SCAN_START_NOTIFICATION = 0x82, 1845286441Srpaulo IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1846286441Srpaulo IWM_SCAN_COMPLETE_NOTIFICATION = 0x84, 1847286441Srpaulo 1848286441Srpaulo /* NVM */ 1849286441Srpaulo IWM_NVM_ACCESS_CMD = 0x88, 1850286441Srpaulo 1851286441Srpaulo IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1852286441Srpaulo 1853286441Srpaulo IWM_BEACON_NOTIFICATION = 0x90, 1854286441Srpaulo IWM_BEACON_TEMPLATE_CMD = 0x91, 1855286441Srpaulo IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1856286441Srpaulo IWM_BT_CONFIG = 0x9b, 1857286441Srpaulo IWM_STATISTICS_NOTIFICATION = 0x9d, 1858286441Srpaulo IWM_REDUCE_TX_POWER_CMD = 0x9f, 1859286441Srpaulo 1860286441Srpaulo /* RF-KILL commands and notifications */ 1861286441Srpaulo IWM_CARD_STATE_CMD = 0xa0, 1862286441Srpaulo IWM_CARD_STATE_NOTIFICATION = 0xa1, 1863286441Srpaulo 1864286441Srpaulo IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1865286441Srpaulo 1866303628Ssbruno IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1867303628Ssbruno 1868286441Srpaulo /* Power - new power table command */ 1869286441Srpaulo IWM_MAC_PM_POWER_TABLE = 0xa9, 1870286441Srpaulo 1871286441Srpaulo IWM_REPLY_RX_PHY_CMD = 0xc0, 1872286441Srpaulo IWM_REPLY_RX_MPDU_CMD = 0xc1, 1873286441Srpaulo IWM_BA_NOTIF = 0xc5, 1874286441Srpaulo 1875303628Ssbruno /* Location Aware Regulatory */ 1876303628Ssbruno IWM_MCC_UPDATE_CMD = 0xc8, 1877303628Ssbruno IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1878303628Ssbruno 1879286441Srpaulo /* BT Coex */ 1880286441Srpaulo IWM_BT_COEX_PRIO_TABLE = 0xcc, 1881286441Srpaulo IWM_BT_COEX_PROT_ENV = 0xcd, 1882286441Srpaulo IWM_BT_PROFILE_NOTIFICATION = 0xce, 1883286441Srpaulo IWM_BT_COEX_CI = 0x5d, 1884286441Srpaulo 1885286441Srpaulo IWM_REPLY_SF_CFG_CMD = 0xd1, 1886286441Srpaulo IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1887286441Srpaulo 1888303628Ssbruno /* DTS measurements */ 1889303628Ssbruno IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1890303628Ssbruno IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1891303628Ssbruno 1892286441Srpaulo IWM_REPLY_DEBUG_CMD = 0xf0, 1893286441Srpaulo IWM_DEBUG_LOG_MSG = 0xf7, 1894286441Srpaulo 1895286441Srpaulo IWM_MCAST_FILTER_CMD = 0xd0, 1896286441Srpaulo 1897286441Srpaulo /* D3 commands/notifications */ 1898286441Srpaulo IWM_D3_CONFIG_CMD = 0xd3, 1899286441Srpaulo IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1900286441Srpaulo IWM_OFFLOADS_QUERY_CMD = 0xd5, 1901286441Srpaulo IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1902286441Srpaulo 1903286441Srpaulo /* for WoWLAN in particular */ 1904286441Srpaulo IWM_WOWLAN_PATTERNS = 0xe0, 1905286441Srpaulo IWM_WOWLAN_CONFIGURATION = 0xe1, 1906286441Srpaulo IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1907286441Srpaulo IWM_WOWLAN_TKIP_PARAM = 0xe3, 1908286441Srpaulo IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1909286441Srpaulo IWM_WOWLAN_GET_STATUSES = 0xe5, 1910286441Srpaulo IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1911286441Srpaulo 1912286441Srpaulo /* and for NetDetect */ 1913286441Srpaulo IWM_NET_DETECT_CONFIG_CMD = 0x54, 1914286441Srpaulo IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1915286441Srpaulo IWM_NET_DETECT_PROFILES_CMD = 0x57, 1916286441Srpaulo IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1917286441Srpaulo IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1918286441Srpaulo 1919286441Srpaulo IWM_REPLY_MAX = 0xff, 1920286441Srpaulo}; 1921286441Srpaulo 1922286441Srpaulo/** 1923286441Srpaulo * struct iwm_cmd_response - generic response struct for most commands 1924286441Srpaulo * @status: status of the command asked, changes for each one 1925286441Srpaulo */ 1926286441Srpaulostruct iwm_cmd_response { 1927286441Srpaulo uint32_t status; 1928286441Srpaulo}; 1929286441Srpaulo 1930286441Srpaulo/* 1931286441Srpaulo * struct iwm_tx_ant_cfg_cmd 1932286441Srpaulo * @valid: valid antenna configuration 1933286441Srpaulo */ 1934286441Srpaulostruct iwm_tx_ant_cfg_cmd { 1935286441Srpaulo uint32_t valid; 1936286441Srpaulo} __packed; 1937286441Srpaulo 1938286441Srpaulo/** 1939286441Srpaulo * struct iwm_reduce_tx_power_cmd - TX power reduction command 1940286441Srpaulo * IWM_REDUCE_TX_POWER_CMD = 0x9f 1941286441Srpaulo * @flags: (reserved for future implementation) 1942286441Srpaulo * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1943286441Srpaulo * @pwr_restriction: TX power restriction in dBms. 1944286441Srpaulo */ 1945286441Srpaulostruct iwm_reduce_tx_power_cmd { 1946286441Srpaulo uint8_t flags; 1947286441Srpaulo uint8_t mac_context_id; 1948286441Srpaulo uint16_t pwr_restriction; 1949286441Srpaulo} __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1950286441Srpaulo 1951286441Srpaulo/* 1952286441Srpaulo * Calibration control struct. 1953286441Srpaulo * Sent as part of the phy configuration command. 1954286441Srpaulo * @flow_trigger: bitmap for which calibrations to perform according to 1955286441Srpaulo * flow triggers. 1956286441Srpaulo * @event_trigger: bitmap for which calibrations to perform according to 1957286441Srpaulo * event triggers. 1958286441Srpaulo */ 1959286441Srpaulostruct iwm_calib_ctrl { 1960286441Srpaulo uint32_t flow_trigger; 1961286441Srpaulo uint32_t event_trigger; 1962286441Srpaulo} __packed; 1963286441Srpaulo 1964286441Srpaulo/* This enum defines the bitmap of various calibrations to enable in both 1965286441Srpaulo * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1966286441Srpaulo */ 1967286441Srpauloenum iwm_calib_cfg { 1968286441Srpaulo IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1969286441Srpaulo IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1970286441Srpaulo IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1971286441Srpaulo IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1972286441Srpaulo IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1973286441Srpaulo IWM_CALIB_CFG_DC_IDX = (1 << 5), 1974286441Srpaulo IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1975286441Srpaulo IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1976286441Srpaulo IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1977286441Srpaulo IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1978286441Srpaulo IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1979286441Srpaulo IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1980286441Srpaulo IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1981286441Srpaulo IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1982286441Srpaulo IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1983286441Srpaulo IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1984286441Srpaulo IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1985286441Srpaulo IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1986286441Srpaulo IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1987286441Srpaulo}; 1988286441Srpaulo 1989286441Srpaulo/* 1990286441Srpaulo * Phy configuration command. 1991286441Srpaulo */ 1992286441Srpaulostruct iwm_phy_cfg_cmd { 1993286441Srpaulo uint32_t phy_cfg; 1994286441Srpaulo struct iwm_calib_ctrl calib_control; 1995286441Srpaulo} __packed; 1996286441Srpaulo 1997286441Srpaulo#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1998286441Srpaulo#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1999286441Srpaulo#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2000286441Srpaulo#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2001286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 2002286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 2003286441Srpaulo#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 2004286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 2005286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 2006286441Srpaulo#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 2007286441Srpaulo 2008301192Sadrian/* 2009301192Sadrian * PHY db 2010301192Sadrian */ 2011286441Srpaulo 2012301192Sadrianenum iwm_phy_db_section_type { 2013301192Sadrian IWM_PHY_DB_CFG = 1, 2014301192Sadrian IWM_PHY_DB_CALIB_NCH, 2015301192Sadrian IWM_PHY_DB_UNUSED, 2016301192Sadrian IWM_PHY_DB_CALIB_CHG_PAPD, 2017301192Sadrian IWM_PHY_DB_CALIB_CHG_TXP, 2018301192Sadrian IWM_PHY_DB_MAX 2019301192Sadrian}; 2020301192Sadrian 2021301192Sadrian#define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */ 2022301192Sadrian 2023301192Sadrian/* 2024301192Sadrian * phy db - configure operational ucode 2025301192Sadrian */ 2026301192Sadrianstruct iwm_phy_db_cmd { 2027301192Sadrian uint16_t type; 2028301192Sadrian uint16_t length; 2029301192Sadrian uint8_t data[]; 2030301192Sadrian} __packed; 2031301192Sadrian 2032301192Sadrian/* for parsing of tx power channel group data that comes from the firmware */ 2033301192Sadrianstruct iwm_phy_db_chg_txp { 2034301192Sadrian uint32_t space; 2035301192Sadrian uint16_t max_channel_idx; 2036301192Sadrian} __packed; 2037301192Sadrian 2038301192Sadrian/* 2039301192Sadrian * phy db - Receive phy db chunk after calibrations 2040301192Sadrian */ 2041301192Sadrianstruct iwm_calib_res_notif_phy_db { 2042301192Sadrian uint16_t type; 2043301192Sadrian uint16_t length; 2044301192Sadrian uint8_t data[]; 2045301192Sadrian} __packed; 2046301192Sadrian 2047301192Sadrian 2048286441Srpaulo/* Target of the IWM_NVM_ACCESS_CMD */ 2049286441Srpauloenum { 2050286441Srpaulo IWM_NVM_ACCESS_TARGET_CACHE = 0, 2051286441Srpaulo IWM_NVM_ACCESS_TARGET_OTP = 1, 2052286441Srpaulo IWM_NVM_ACCESS_TARGET_EEPROM = 2, 2053286441Srpaulo}; 2054286441Srpaulo 2055286441Srpaulo/* Section types for IWM_NVM_ACCESS_CMD */ 2056286441Srpauloenum { 2057286441Srpaulo IWM_NVM_SECTION_TYPE_HW = 0, 2058286441Srpaulo IWM_NVM_SECTION_TYPE_SW, 2059286441Srpaulo IWM_NVM_SECTION_TYPE_PAPD, 2060303628Ssbruno IWM_NVM_SECTION_TYPE_REGULATORY, 2061286441Srpaulo IWM_NVM_SECTION_TYPE_CALIBRATION, 2062286441Srpaulo IWM_NVM_SECTION_TYPE_PRODUCTION, 2063286441Srpaulo IWM_NVM_SECTION_TYPE_POST_FCS_CALIB, 2064303628Ssbruno /* 7, 8, 9 unknown */ 2065303628Ssbruno IWM_NVM_SECTION_TYPE_HW_8000 = 10, 2066303628Ssbruno IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 2067303628Ssbruno IWM_NVM_SECTION_TYPE_PHY_SKU, 2068286441Srpaulo IWM_NVM_NUM_OF_SECTIONS, 2069286441Srpaulo}; 2070286441Srpaulo 2071286441Srpaulo/** 2072286441Srpaulo * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2073286441Srpaulo * @op_code: 0 - read, 1 - write 2074286441Srpaulo * @target: IWM_NVM_ACCESS_TARGET_* 2075286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 2076286441Srpaulo * @offset: offset in bytes into the section 2077286441Srpaulo * @length: in bytes, to read/write 2078286441Srpaulo * @data: if write operation, the data to write. On read its empty 2079286441Srpaulo */ 2080286441Srpaulostruct iwm_nvm_access_cmd { 2081286441Srpaulo uint8_t op_code; 2082286441Srpaulo uint8_t target; 2083286441Srpaulo uint16_t type; 2084286441Srpaulo uint16_t offset; 2085286441Srpaulo uint16_t length; 2086286441Srpaulo uint8_t data[]; 2087286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2088286441Srpaulo 2089286441Srpaulo/** 2090286441Srpaulo * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2091286441Srpaulo * @offset: offset in bytes into the section 2092286441Srpaulo * @length: in bytes, either how much was written or read 2093286441Srpaulo * @type: IWM_NVM_SECTION_TYPE_* 2094286441Srpaulo * @status: 0 for success, fail otherwise 2095286441Srpaulo * @data: if read operation, the data returned. Empty on write. 2096286441Srpaulo */ 2097286441Srpaulostruct iwm_nvm_access_resp { 2098286441Srpaulo uint16_t offset; 2099286441Srpaulo uint16_t length; 2100286441Srpaulo uint16_t type; 2101286441Srpaulo uint16_t status; 2102286441Srpaulo uint8_t data[]; 2103286441Srpaulo} __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2104286441Srpaulo 2105286441Srpaulo/* IWM_MVM_ALIVE 0x1 */ 2106286441Srpaulo 2107286441Srpaulo/* alive response is_valid values */ 2108286441Srpaulo#define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2109286441Srpaulo#define IWM_ALIVE_RESP_RFKILL (1 << 1) 2110286441Srpaulo 2111286441Srpaulo/* alive response ver_type values */ 2112286441Srpauloenum { 2113286441Srpaulo IWM_FW_TYPE_HW = 0, 2114286441Srpaulo IWM_FW_TYPE_PROT = 1, 2115286441Srpaulo IWM_FW_TYPE_AP = 2, 2116286441Srpaulo IWM_FW_TYPE_WOWLAN = 3, 2117286441Srpaulo IWM_FW_TYPE_TIMING = 4, 2118286441Srpaulo IWM_FW_TYPE_WIPAN = 5 2119286441Srpaulo}; 2120286441Srpaulo 2121286441Srpaulo/* alive response ver_subtype values */ 2122286441Srpauloenum { 2123286441Srpaulo IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2124286441Srpaulo IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2125286441Srpaulo IWM_FW_SUBTYPE_REDUCED = 2, 2126286441Srpaulo IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2127286441Srpaulo IWM_FW_SUBTYPE_WOWLAN = 4, 2128286441Srpaulo IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2129286441Srpaulo IWM_FW_SUBTYPE_WIPAN = 6, 2130286441Srpaulo IWM_FW_SUBTYPE_INITIALIZE = 9 2131286441Srpaulo}; 2132286441Srpaulo 2133286441Srpaulo#define IWM_ALIVE_STATUS_ERR 0xDEAD 2134286441Srpaulo#define IWM_ALIVE_STATUS_OK 0xCAFE 2135286441Srpaulo 2136286441Srpaulo#define IWM_ALIVE_FLG_RFKILL (1 << 0) 2137286441Srpaulo 2138303628Ssbrunostruct iwm_mvm_alive_resp_v1 { 2139286441Srpaulo uint16_t status; 2140286441Srpaulo uint16_t flags; 2141286441Srpaulo uint8_t ucode_minor; 2142286441Srpaulo uint8_t ucode_major; 2143286441Srpaulo uint16_t id; 2144286441Srpaulo uint8_t api_minor; 2145286441Srpaulo uint8_t api_major; 2146286441Srpaulo uint8_t ver_subtype; 2147286441Srpaulo uint8_t ver_type; 2148286441Srpaulo uint8_t mac; 2149286441Srpaulo uint8_t opt; 2150286441Srpaulo uint16_t reserved2; 2151286441Srpaulo uint32_t timestamp; 2152286441Srpaulo uint32_t error_event_table_ptr; /* SRAM address for error log */ 2153286441Srpaulo uint32_t log_event_table_ptr; /* SRAM address for event log */ 2154286441Srpaulo uint32_t cpu_register_ptr; 2155286441Srpaulo uint32_t dbgm_config_ptr; 2156286441Srpaulo uint32_t alive_counter_ptr; 2157286441Srpaulo uint32_t scd_base_ptr; /* SRAM address for SCD */ 2158286441Srpaulo} __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2159286441Srpaulo 2160303628Ssbrunostruct iwm_mvm_alive_resp_v2 { 2161303628Ssbruno uint16_t status; 2162303628Ssbruno uint16_t flags; 2163303628Ssbruno uint8_t ucode_minor; 2164303628Ssbruno uint8_t ucode_major; 2165303628Ssbruno uint16_t id; 2166303628Ssbruno uint8_t api_minor; 2167303628Ssbruno uint8_t api_major; 2168303628Ssbruno uint8_t ver_subtype; 2169303628Ssbruno uint8_t ver_type; 2170303628Ssbruno uint8_t mac; 2171303628Ssbruno uint8_t opt; 2172303628Ssbruno uint16_t reserved2; 2173303628Ssbruno uint32_t timestamp; 2174303628Ssbruno uint32_t error_event_table_ptr; /* SRAM address for error log */ 2175303628Ssbruno uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2176303628Ssbruno uint32_t cpu_register_ptr; 2177303628Ssbruno uint32_t dbgm_config_ptr; 2178303628Ssbruno uint32_t alive_counter_ptr; 2179303628Ssbruno uint32_t scd_base_ptr; /* SRAM address for SCD */ 2180303628Ssbruno uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2181303628Ssbruno uint32_t st_fwrd_size; 2182303628Ssbruno uint8_t umac_minor; /* UMAC version: minor */ 2183303628Ssbruno uint8_t umac_major; /* UMAC version: major */ 2184303628Ssbruno uint16_t umac_id; /* UMAC version: id */ 2185303628Ssbruno uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2186303628Ssbruno uint32_t dbg_print_buff_addr; 2187303628Ssbruno} __packed; /* ALIVE_RES_API_S_VER_2 */ 2188303628Ssbruno 2189303628Ssbrunostruct iwm_mvm_alive_resp_v3 { 2190303628Ssbruno uint16_t status; 2191303628Ssbruno uint16_t flags; 2192303628Ssbruno uint32_t ucode_minor; 2193303628Ssbruno uint32_t ucode_major; 2194303628Ssbruno uint8_t ver_subtype; 2195303628Ssbruno uint8_t ver_type; 2196303628Ssbruno uint8_t mac; 2197303628Ssbruno uint8_t opt; 2198303628Ssbruno uint32_t timestamp; 2199303628Ssbruno uint32_t error_event_table_ptr; /* SRAM address for error log */ 2200303628Ssbruno uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2201303628Ssbruno uint32_t cpu_register_ptr; 2202303628Ssbruno uint32_t dbgm_config_ptr; 2203303628Ssbruno uint32_t alive_counter_ptr; 2204303628Ssbruno uint32_t scd_base_ptr; /* SRAM address for SCD */ 2205303628Ssbruno uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2206303628Ssbruno uint32_t st_fwrd_size; 2207303628Ssbruno uint32_t umac_minor; /* UMAC version: minor */ 2208303628Ssbruno uint32_t umac_major; /* UMAC version: major */ 2209303628Ssbruno uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2210303628Ssbruno uint32_t dbg_print_buff_addr; 2211303628Ssbruno} __packed; /* ALIVE_RES_API_S_VER_3 */ 2212303628Ssbruno 2213286441Srpaulo/* Error response/notification */ 2214286441Srpauloenum { 2215286441Srpaulo IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2216286441Srpaulo IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2217286441Srpaulo IWM_FW_ERR_SERVICE = 0x2, 2218286441Srpaulo IWM_FW_ERR_ARC_MEMORY = 0x3, 2219286441Srpaulo IWM_FW_ERR_ARC_CODE = 0x4, 2220286441Srpaulo IWM_FW_ERR_WATCH_DOG = 0x5, 2221286441Srpaulo IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2222286441Srpaulo IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2223286441Srpaulo IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2224286441Srpaulo IWM_FW_ERR_UNEXPECTED = 0xFE, 2225286441Srpaulo IWM_FW_ERR_FATAL = 0xFF 2226286441Srpaulo}; 2227286441Srpaulo 2228286441Srpaulo/** 2229286441Srpaulo * struct iwm_error_resp - FW error indication 2230286441Srpaulo * ( IWM_REPLY_ERROR = 0x2 ) 2231286441Srpaulo * @error_type: one of IWM_FW_ERR_* 2232298955Spfg * @cmd_id: the command ID for which the error occurred 2233286441Srpaulo * @bad_cmd_seq_num: sequence number of the erroneous command 2234286441Srpaulo * @error_service: which service created the error, applicable only if 2235286441Srpaulo * error_type = 2, otherwise 0 2236286441Srpaulo * @timestamp: TSF in usecs. 2237286441Srpaulo */ 2238286441Srpaulostruct iwm_error_resp { 2239286441Srpaulo uint32_t error_type; 2240286441Srpaulo uint8_t cmd_id; 2241286441Srpaulo uint8_t reserved1; 2242286441Srpaulo uint16_t bad_cmd_seq_num; 2243286441Srpaulo uint32_t error_service; 2244286441Srpaulo uint64_t timestamp; 2245286441Srpaulo} __packed; 2246286441Srpaulo 2247286441Srpaulo 2248286441Srpaulo/* Common PHY, MAC and Bindings definitions */ 2249286441Srpaulo 2250286441Srpaulo#define IWM_MAX_MACS_IN_BINDING (3) 2251286441Srpaulo#define IWM_MAX_BINDINGS (4) 2252286441Srpaulo#define IWM_AUX_BINDING_INDEX (3) 2253286441Srpaulo#define IWM_MAX_PHYS (4) 2254286441Srpaulo 2255286441Srpaulo/* Used to extract ID and color from the context dword */ 2256286441Srpaulo#define IWM_FW_CTXT_ID_POS (0) 2257286441Srpaulo#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2258286441Srpaulo#define IWM_FW_CTXT_COLOR_POS (8) 2259286441Srpaulo#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2260286441Srpaulo#define IWM_FW_CTXT_INVALID (0xffffffff) 2261286441Srpaulo 2262286441Srpaulo#define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2263286441Srpaulo (_color << IWM_FW_CTXT_COLOR_POS)) 2264286441Srpaulo 2265286441Srpaulo/* Possible actions on PHYs, MACs and Bindings */ 2266286441Srpauloenum { 2267286441Srpaulo IWM_FW_CTXT_ACTION_STUB = 0, 2268286441Srpaulo IWM_FW_CTXT_ACTION_ADD, 2269286441Srpaulo IWM_FW_CTXT_ACTION_MODIFY, 2270286441Srpaulo IWM_FW_CTXT_ACTION_REMOVE, 2271286441Srpaulo IWM_FW_CTXT_ACTION_NUM 2272286441Srpaulo}; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2273286441Srpaulo 2274286441Srpaulo/* Time Events */ 2275286441Srpaulo 2276286441Srpaulo/* Time Event types, according to MAC type */ 2277286441Srpauloenum iwm_time_event_type { 2278286441Srpaulo /* BSS Station Events */ 2279286441Srpaulo IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2280286441Srpaulo IWM_TE_BSS_STA_ASSOC, 2281286441Srpaulo IWM_TE_BSS_EAP_DHCP_PROT, 2282286441Srpaulo IWM_TE_BSS_QUIET_PERIOD, 2283286441Srpaulo 2284286441Srpaulo /* P2P Device Events */ 2285286441Srpaulo IWM_TE_P2P_DEVICE_DISCOVERABLE, 2286286441Srpaulo IWM_TE_P2P_DEVICE_LISTEN, 2287286441Srpaulo IWM_TE_P2P_DEVICE_ACTION_SCAN, 2288286441Srpaulo IWM_TE_P2P_DEVICE_FULL_SCAN, 2289286441Srpaulo 2290286441Srpaulo /* P2P Client Events */ 2291286441Srpaulo IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2292286441Srpaulo IWM_TE_P2P_CLIENT_ASSOC, 2293286441Srpaulo IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2294286441Srpaulo 2295286441Srpaulo /* P2P GO Events */ 2296286441Srpaulo IWM_TE_P2P_GO_ASSOC_PROT, 2297286441Srpaulo IWM_TE_P2P_GO_REPETITIVE_NOA, 2298286441Srpaulo IWM_TE_P2P_GO_CT_WINDOW, 2299286441Srpaulo 2300286441Srpaulo /* WiDi Sync Events */ 2301286441Srpaulo IWM_TE_WIDI_TX_SYNC, 2302286441Srpaulo 2303286441Srpaulo IWM_TE_MAX 2304286441Srpaulo}; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2305286441Srpaulo 2306286441Srpaulo 2307286441Srpaulo 2308286441Srpaulo/* Time event - defines for command API v1 */ 2309286441Srpaulo 2310286441Srpaulo/* 2311286441Srpaulo * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2312286441Srpaulo * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2313286441Srpaulo * the first fragment is scheduled. 2314286441Srpaulo * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2315286441Srpaulo * the first 2 fragments are scheduled. 2316286441Srpaulo * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2317286441Srpaulo * number of fragments are valid. 2318286441Srpaulo * 2319286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2320286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2321286441Srpaulo * scheduled. 2322286441Srpaulo */ 2323286441Srpauloenum { 2324286441Srpaulo IWM_TE_V1_FRAG_NONE = 0, 2325286441Srpaulo IWM_TE_V1_FRAG_SINGLE = 1, 2326286441Srpaulo IWM_TE_V1_FRAG_DUAL = 2, 2327286441Srpaulo IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2328286441Srpaulo}; 2329286441Srpaulo 2330286441Srpaulo/* If a Time Event can be fragmented, this is the max number of fragments */ 2331286441Srpaulo#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2332286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2333286441Srpaulo#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2334286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2335286441Srpaulo#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2336286441Srpaulo 2337286441Srpaulo/* Time Event dependencies: none, on another TE, or in a specific time */ 2338286441Srpauloenum { 2339286441Srpaulo IWM_TE_V1_INDEPENDENT = 0, 2340286441Srpaulo IWM_TE_V1_DEP_OTHER = (1 << 0), 2341286441Srpaulo IWM_TE_V1_DEP_TSF = (1 << 1), 2342286441Srpaulo IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2343286441Srpaulo}; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2344286441Srpaulo 2345286441Srpaulo/* 2346286441Srpaulo * @IWM_TE_V1_NOTIF_NONE: no notifications 2347286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2348286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2349286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2350286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2351286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2352286441Srpaulo * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2353286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2354286441Srpaulo * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2355286441Srpaulo * 2356286441Srpaulo * Supported Time event notifications configuration. 2357286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2358286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2359286441Srpaulo * notification the status is always success. There is no start/end fragment 2360286441Srpaulo * notification for monolithic events. 2361286441Srpaulo */ 2362286441Srpauloenum { 2363286441Srpaulo IWM_TE_V1_NOTIF_NONE = 0, 2364286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2365286441Srpaulo IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2366286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2367286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2368286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2369286441Srpaulo IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2370286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2371286441Srpaulo IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2372303628Ssbruno IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2373286441Srpaulo}; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2374286441Srpaulo 2375286441Srpaulo 2376286441Srpaulo/** 2377286441Srpaulo * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2378286441Srpaulo * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2379286441Srpaulo * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2380286441Srpaulo * ( IWM_TIME_EVENT_CMD = 0x29 ) 2381286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2382286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2383286441Srpaulo * @id: this field has two meanings, depending on the action: 2384286441Srpaulo * If the action is ADD, then it means the type of event to add. 2385286441Srpaulo * For all other actions it is the unique event ID assigned when the 2386286441Srpaulo * event was added by the FW. 2387286441Srpaulo * @apply_time: When to start the Time Event (in GP2) 2388286441Srpaulo * @max_delay: maximum delay to event's start (apply time), in TU 2389286441Srpaulo * @depends_on: the unique ID of the event we depend on (if any) 2390286441Srpaulo * @interval: interval between repetitions, in TU 2391286441Srpaulo * @interval_reciprocal: 2^32 / interval 2392286441Srpaulo * @duration: duration of event in TU 2393286441Srpaulo * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2394286441Srpaulo * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2395286441Srpaulo * and IWM_TE_V1_EVENT_SOCIOPATHIC 2396286441Srpaulo * @is_present: 0 or 1, are we present or absent during the Time Event 2397286441Srpaulo * @max_frags: maximal number of fragments the Time Event can be divided to 2398286441Srpaulo * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2399286441Srpaulo */ 2400286441Srpaulostruct iwm_time_event_cmd_v1 { 2401286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2402286441Srpaulo uint32_t id_and_color; 2403286441Srpaulo uint32_t action; 2404286441Srpaulo uint32_t id; 2405286441Srpaulo /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2406286441Srpaulo uint32_t apply_time; 2407286441Srpaulo uint32_t max_delay; 2408286441Srpaulo uint32_t dep_policy; 2409286441Srpaulo uint32_t depends_on; 2410286441Srpaulo uint32_t is_present; 2411286441Srpaulo uint32_t max_frags; 2412286441Srpaulo uint32_t interval; 2413286441Srpaulo uint32_t interval_reciprocal; 2414286441Srpaulo uint32_t duration; 2415286441Srpaulo uint32_t repeat; 2416286441Srpaulo uint32_t notify; 2417286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2418286441Srpaulo 2419286441Srpaulo 2420286441Srpaulo/* Time event - defines for command API v2 */ 2421286441Srpaulo 2422286441Srpaulo/* 2423286441Srpaulo * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2424286441Srpaulo * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2425286441Srpaulo * the first fragment is scheduled. 2426286441Srpaulo * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2427286441Srpaulo * the first 2 fragments are scheduled. 2428286441Srpaulo * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2429286441Srpaulo * number of fragments are valid. 2430286441Srpaulo * 2431286441Srpaulo * Other than the constant defined above, specifying a fragmentation value 'x' 2432286441Srpaulo * means that the event can be fragmented but only the first 'x' will be 2433286441Srpaulo * scheduled. 2434286441Srpaulo */ 2435286441Srpauloenum { 2436286441Srpaulo IWM_TE_V2_FRAG_NONE = 0, 2437286441Srpaulo IWM_TE_V2_FRAG_SINGLE = 1, 2438286441Srpaulo IWM_TE_V2_FRAG_DUAL = 2, 2439286441Srpaulo IWM_TE_V2_FRAG_MAX = 0xfe, 2440286441Srpaulo IWM_TE_V2_FRAG_ENDLESS = 0xff 2441286441Srpaulo}; 2442286441Srpaulo 2443286441Srpaulo/* Repeat the time event endlessly (until removed) */ 2444286441Srpaulo#define IWM_TE_V2_REPEAT_ENDLESS 0xff 2445286441Srpaulo/* If a Time Event has bounded repetitions, this is the maximal value */ 2446286441Srpaulo#define IWM_TE_V2_REPEAT_MAX 0xfe 2447286441Srpaulo 2448286441Srpaulo#define IWM_TE_V2_PLACEMENT_POS 12 2449286441Srpaulo#define IWM_TE_V2_ABSENCE_POS 15 2450286441Srpaulo 2451286441Srpaulo/* Time event policy values (for time event cmd api v2) 2452286441Srpaulo * A notification (both event and fragment) includes a status indicating weather 2453286441Srpaulo * the FW was able to schedule the event or not. For fragment start/end 2454286441Srpaulo * notification the status is always success. There is no start/end fragment 2455286441Srpaulo * notification for monolithic events. 2456286441Srpaulo * 2457286441Srpaulo * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2458286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2459286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2460286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2461286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2462286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2463286441Srpaulo * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2464286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2465286441Srpaulo * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2466286441Srpaulo * @IWM_TE_V2_DEP_OTHER: depends on another time event 2467286441Srpaulo * @IWM_TE_V2_DEP_TSF: depends on a specific time 2468286441Srpaulo * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2469286441Srpaulo * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2470286441Srpaulo */ 2471286441Srpauloenum { 2472286441Srpaulo IWM_TE_V2_DEFAULT_POLICY = 0x0, 2473286441Srpaulo 2474286441Srpaulo /* notifications (event start/stop, fragment start/stop) */ 2475286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2476286441Srpaulo IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2477286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2478286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2479286441Srpaulo 2480286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2481286441Srpaulo IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2482286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2483286441Srpaulo IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2484286441Srpaulo 2485286441Srpaulo IWM_TE_V2_NOTIF_MSK = 0xff, 2486286441Srpaulo 2487286441Srpaulo /* placement characteristics */ 2488286441Srpaulo IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2489286441Srpaulo IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2490286441Srpaulo IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2491286441Srpaulo 2492286441Srpaulo /* are we present or absent during the Time Event. */ 2493286441Srpaulo IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2494286441Srpaulo}; 2495286441Srpaulo 2496286441Srpaulo/** 2497286441Srpaulo * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2498286441Srpaulo * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2499286441Srpaulo * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2500286441Srpaulo * ( IWM_TIME_EVENT_CMD = 0x29 ) 2501286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2502286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2503286441Srpaulo * @id: this field has two meanings, depending on the action: 2504286441Srpaulo * If the action is ADD, then it means the type of event to add. 2505286441Srpaulo * For all other actions it is the unique event ID assigned when the 2506286441Srpaulo * event was added by the FW. 2507286441Srpaulo * @apply_time: When to start the Time Event (in GP2) 2508286441Srpaulo * @max_delay: maximum delay to event's start (apply time), in TU 2509286441Srpaulo * @depends_on: the unique ID of the event we depend on (if any) 2510286441Srpaulo * @interval: interval between repetitions, in TU 2511286441Srpaulo * @duration: duration of event in TU 2512286441Srpaulo * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2513286441Srpaulo * @max_frags: maximal number of fragments the Time Event can be divided to 2514286441Srpaulo * @policy: defines whether uCode shall notify the host or other uCode modules 2515286441Srpaulo * on event and/or fragment start and/or end 2516286441Srpaulo * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2517286441Srpaulo * IWM_TE_EVENT_SOCIOPATHIC 2518286441Srpaulo * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2519286441Srpaulo */ 2520286441Srpaulostruct iwm_time_event_cmd_v2 { 2521286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2522286441Srpaulo uint32_t id_and_color; 2523286441Srpaulo uint32_t action; 2524286441Srpaulo uint32_t id; 2525286441Srpaulo /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2526286441Srpaulo uint32_t apply_time; 2527286441Srpaulo uint32_t max_delay; 2528286441Srpaulo uint32_t depends_on; 2529286441Srpaulo uint32_t interval; 2530286441Srpaulo uint32_t duration; 2531286441Srpaulo uint8_t repeat; 2532286441Srpaulo uint8_t max_frags; 2533286441Srpaulo uint16_t policy; 2534286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2535286441Srpaulo 2536286441Srpaulo/** 2537286441Srpaulo * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2538286441Srpaulo * @status: bit 0 indicates success, all others specify errors 2539286441Srpaulo * @id: the Time Event type 2540286441Srpaulo * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2541286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2542286441Srpaulo */ 2543286441Srpaulostruct iwm_time_event_resp { 2544286441Srpaulo uint32_t status; 2545286441Srpaulo uint32_t id; 2546286441Srpaulo uint32_t unique_id; 2547286441Srpaulo uint32_t id_and_color; 2548286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2549286441Srpaulo 2550286441Srpaulo/** 2551286441Srpaulo * struct iwm_time_event_notif - notifications of time event start/stop 2552286441Srpaulo * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2553286441Srpaulo * @timestamp: action timestamp in GP2 2554286441Srpaulo * @session_id: session's unique id 2555286441Srpaulo * @unique_id: unique id of the Time Event itself 2556286441Srpaulo * @id_and_color: ID and color of the relevant MAC 2557286441Srpaulo * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2558286441Srpaulo * @status: true if scheduled, false otherwise (not executed) 2559286441Srpaulo */ 2560286441Srpaulostruct iwm_time_event_notif { 2561286441Srpaulo uint32_t timestamp; 2562286441Srpaulo uint32_t session_id; 2563286441Srpaulo uint32_t unique_id; 2564286441Srpaulo uint32_t id_and_color; 2565286441Srpaulo uint32_t action; 2566286441Srpaulo uint32_t status; 2567286441Srpaulo} __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2568286441Srpaulo 2569286441Srpaulo 2570286441Srpaulo/* Bindings and Time Quota */ 2571286441Srpaulo 2572286441Srpaulo/** 2573286441Srpaulo * struct iwm_binding_cmd - configuring bindings 2574286441Srpaulo * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2575286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2576286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2577286441Srpaulo * @macs: array of MAC id and colors which belong to the binding 2578286441Srpaulo * @phy: PHY id and color which belongs to the binding 2579286441Srpaulo */ 2580286441Srpaulostruct iwm_binding_cmd { 2581286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2582286441Srpaulo uint32_t id_and_color; 2583286441Srpaulo uint32_t action; 2584286441Srpaulo /* IWM_BINDING_DATA_API_S_VER_1 */ 2585286441Srpaulo uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2586286441Srpaulo uint32_t phy; 2587286441Srpaulo} __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2588286441Srpaulo 2589286441Srpaulo/* The maximal number of fragments in the FW's schedule session */ 2590286441Srpaulo#define IWM_MVM_MAX_QUOTA 128 2591286441Srpaulo 2592286441Srpaulo/** 2593286441Srpaulo * struct iwm_time_quota_data - configuration of time quota per binding 2594286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2595286441Srpaulo * @quota: absolute time quota in TU. The scheduler will try to divide the 2596286441Srpaulo * remainig quota (after Time Events) according to this quota. 2597286441Srpaulo * @max_duration: max uninterrupted context duration in TU 2598286441Srpaulo */ 2599286441Srpaulostruct iwm_time_quota_data { 2600286441Srpaulo uint32_t id_and_color; 2601286441Srpaulo uint32_t quota; 2602286441Srpaulo uint32_t max_duration; 2603286441Srpaulo} __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2604286441Srpaulo 2605286441Srpaulo/** 2606286441Srpaulo * struct iwm_time_quota_cmd - configuration of time quota between bindings 2607286441Srpaulo * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2608286441Srpaulo * @quotas: allocations per binding 2609286441Srpaulo */ 2610286441Srpaulostruct iwm_time_quota_cmd { 2611286441Srpaulo struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2612286441Srpaulo} __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2613286441Srpaulo 2614286441Srpaulo 2615286441Srpaulo/* PHY context */ 2616286441Srpaulo 2617286441Srpaulo/* Supported bands */ 2618286441Srpaulo#define IWM_PHY_BAND_5 (0) 2619286441Srpaulo#define IWM_PHY_BAND_24 (1) 2620286441Srpaulo 2621286441Srpaulo/* Supported channel width, vary if there is VHT support */ 2622286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2623286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2624286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2625286441Srpaulo#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2626286441Srpaulo 2627286441Srpaulo/* 2628286441Srpaulo * Control channel position: 2629286441Srpaulo * For legacy set bit means upper channel, otherwise lower. 2630286441Srpaulo * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2631286441Srpaulo * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2632286441Srpaulo * center_freq 2633286441Srpaulo * | 2634286441Srpaulo * 40Mhz |_______|_______| 2635286441Srpaulo * 80Mhz |_______|_______|_______|_______| 2636286441Srpaulo * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2637286441Srpaulo * code 011 010 001 000 | 100 101 110 111 2638286441Srpaulo */ 2639286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2640286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2641286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2642286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2643286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2644286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2645286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2646286441Srpaulo#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2647286441Srpaulo 2648286441Srpaulo/* 2649286441Srpaulo * @band: IWM_PHY_BAND_* 2650286441Srpaulo * @channel: channel number 2651286441Srpaulo * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2652286441Srpaulo * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2653286441Srpaulo */ 2654286441Srpaulostruct iwm_fw_channel_info { 2655286441Srpaulo uint8_t band; 2656286441Srpaulo uint8_t channel; 2657286441Srpaulo uint8_t width; 2658286441Srpaulo uint8_t ctrl_pos; 2659286441Srpaulo} __packed; 2660286441Srpaulo 2661286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2662286441Srpaulo#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2663286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2664286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_POS (1) 2665286441Srpaulo#define IWM_PHY_RX_CHAIN_VALID_MSK \ 2666286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2667286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2668286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2669286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2670286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2671286441Srpaulo#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2672286441Srpaulo (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2673286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_POS (10) 2674286441Srpaulo#define IWM_PHY_RX_CHAIN_CNT_MSK \ 2675286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2676286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2677286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2678286441Srpaulo (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2679286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2680286441Srpaulo#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2681286441Srpaulo (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2682286441Srpaulo 2683286441Srpaulo/* TODO: fix the value, make it depend on firmware at runtime? */ 2684286441Srpaulo#define IWM_NUM_PHY_CTX 3 2685286441Srpaulo 2686286441Srpaulo/* TODO: complete missing documentation */ 2687286441Srpaulo/** 2688286441Srpaulo * struct iwm_phy_context_cmd - config of the PHY context 2689286441Srpaulo * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2690286441Srpaulo * @id_and_color: ID and color of the relevant Binding 2691286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2692286441Srpaulo * @apply_time: 0 means immediate apply and context switch. 2693286441Srpaulo * other value means apply new params after X usecs 2694286441Srpaulo * @tx_param_color: ??? 2695286441Srpaulo * @channel_info: 2696286441Srpaulo * @txchain_info: ??? 2697286441Srpaulo * @rxchain_info: ??? 2698286441Srpaulo * @acquisition_data: ??? 2699286441Srpaulo * @dsp_cfg_flags: set to 0 2700286441Srpaulo */ 2701286441Srpaulostruct iwm_phy_context_cmd { 2702286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 2703286441Srpaulo uint32_t id_and_color; 2704286441Srpaulo uint32_t action; 2705286441Srpaulo /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2706286441Srpaulo uint32_t apply_time; 2707286441Srpaulo uint32_t tx_param_color; 2708286441Srpaulo struct iwm_fw_channel_info ci; 2709286441Srpaulo uint32_t txchain_info; 2710286441Srpaulo uint32_t rxchain_info; 2711286441Srpaulo uint32_t acquisition_data; 2712286441Srpaulo uint32_t dsp_cfg_flags; 2713286441Srpaulo} __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2714286441Srpaulo 2715286441Srpaulo#define IWM_RX_INFO_PHY_CNT 8 2716286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2717286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2718286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2719286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2720286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2721286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2722286441Srpaulo#define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2723286441Srpaulo 2724286441Srpaulo#define IWM_RX_INFO_AGC_IDX 1 2725286441Srpaulo#define IWM_RX_INFO_RSSI_AB_IDX 2 2726286441Srpaulo#define IWM_OFDM_AGC_A_MSK 0x0000007f 2727286441Srpaulo#define IWM_OFDM_AGC_A_POS 0 2728286441Srpaulo#define IWM_OFDM_AGC_B_MSK 0x00003f80 2729286441Srpaulo#define IWM_OFDM_AGC_B_POS 7 2730286441Srpaulo#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2731286441Srpaulo#define IWM_OFDM_AGC_CODE_POS 20 2732286441Srpaulo#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2733286441Srpaulo#define IWM_OFDM_RSSI_A_POS 0 2734286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2735286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2736286441Srpaulo#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2737286441Srpaulo#define IWM_OFDM_RSSI_B_POS 16 2738286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2739286441Srpaulo#define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2740286441Srpaulo 2741286441Srpaulo/** 2742286441Srpaulo * struct iwm_rx_phy_info - phy info 2743286441Srpaulo * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2744286441Srpaulo * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2745286441Srpaulo * @cfg_phy_cnt: configurable DSP phy data byte count 2746286441Srpaulo * @stat_id: configurable DSP phy data set ID 2747286441Srpaulo * @reserved1: 2748286441Srpaulo * @system_timestamp: GP2 at on air rise 2749286441Srpaulo * @timestamp: TSF at on air rise 2750286441Srpaulo * @beacon_time_stamp: beacon at on-air rise 2751286441Srpaulo * @phy_flags: general phy flags: band, modulation, ... 2752286441Srpaulo * @channel: channel number 2753286441Srpaulo * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2754286441Srpaulo * @rate_n_flags: IWM_RATE_MCS_* 2755286441Srpaulo * @byte_count: frame's byte-count 2756286441Srpaulo * @frame_time: frame's time on the air, based on byte count and frame rate 2757286441Srpaulo * calculation 2758286441Srpaulo * @mac_active_msk: what MACs were active when the frame was received 2759286441Srpaulo * 2760286441Srpaulo * Before each Rx, the device sends this data. It contains PHY information 2761286441Srpaulo * about the reception of the packet. 2762286441Srpaulo */ 2763286441Srpaulostruct iwm_rx_phy_info { 2764286441Srpaulo uint8_t non_cfg_phy_cnt; 2765286441Srpaulo uint8_t cfg_phy_cnt; 2766286441Srpaulo uint8_t stat_id; 2767286441Srpaulo uint8_t reserved1; 2768286441Srpaulo uint32_t system_timestamp; 2769286441Srpaulo uint64_t timestamp; 2770286441Srpaulo uint32_t beacon_time_stamp; 2771286441Srpaulo uint16_t phy_flags; 2772286441Srpaulo#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2773286441Srpaulo uint16_t channel; 2774286441Srpaulo uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2775286441Srpaulo uint8_t rate; 2776286441Srpaulo uint8_t rflags; 2777286441Srpaulo uint16_t xrflags; 2778286441Srpaulo uint32_t byte_count; 2779286441Srpaulo uint16_t mac_active_msk; 2780286441Srpaulo uint16_t frame_time; 2781286441Srpaulo} __packed; 2782286441Srpaulo 2783286441Srpaulostruct iwm_rx_mpdu_res_start { 2784286441Srpaulo uint16_t byte_count; 2785286441Srpaulo uint16_t reserved; 2786286441Srpaulo} __packed; 2787286441Srpaulo 2788286441Srpaulo/** 2789286441Srpaulo * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2790286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2791286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2792286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2793286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2794286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2795286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2796286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2797286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2798286441Srpaulo * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2799286441Srpaulo */ 2800286441Srpauloenum iwm_rx_phy_flags { 2801286441Srpaulo IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2802286441Srpaulo IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2803286441Srpaulo IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2804286441Srpaulo IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2805286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2806286441Srpaulo IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2807286441Srpaulo IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2808286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2809286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2810286441Srpaulo IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2811286441Srpaulo}; 2812286441Srpaulo 2813286441Srpaulo/** 2814286441Srpaulo * enum iwm_mvm_rx_status - written by fw for each Rx packet 2815286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2816286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2817286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2818286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2819286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2820286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2821286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2822286441Srpaulo * in the driver. 2823286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2824286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2825286441Srpaulo * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2826286441Srpaulo * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2827286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2828286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2829286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2830286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2831286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2832286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2833286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2834286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2835286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2836286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2837286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2838286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2839286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2840286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2841286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2842286441Srpaulo * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2843286441Srpaulo * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2844286441Srpaulo */ 2845286441Srpauloenum iwm_mvm_rx_status { 2846286441Srpaulo IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2847286441Srpaulo IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2848286441Srpaulo IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2849286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2850286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2851286441Srpaulo IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2852286441Srpaulo IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2853286441Srpaulo IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2854286441Srpaulo IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2855286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2856286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2857286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2858286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2859286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2860286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2861286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2862286441Srpaulo IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2863286441Srpaulo IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2864286441Srpaulo IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2865286441Srpaulo IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2866286441Srpaulo IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2867286441Srpaulo IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2868286441Srpaulo IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2869286441Srpaulo IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2870286441Srpaulo IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2871286441Srpaulo IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2872286441Srpaulo IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2873286441Srpaulo}; 2874286441Srpaulo 2875286441Srpaulo/** 2876286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2877286441Srpaulo * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2878286441Srpaulo * @radio_flavor: 2879286441Srpaulo * @radio_step: 2880286441Srpaulo * @radio_dash: 2881286441Srpaulo */ 2882286441Srpaulostruct iwm_radio_version_notif { 2883286441Srpaulo uint32_t radio_flavor; 2884286441Srpaulo uint32_t radio_step; 2885286441Srpaulo uint32_t radio_dash; 2886286441Srpaulo} __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2887286441Srpaulo 2888286441Srpauloenum iwm_card_state_flags { 2889286441Srpaulo IWM_CARD_ENABLED = 0x00, 2890286441Srpaulo IWM_HW_CARD_DISABLED = 0x01, 2891286441Srpaulo IWM_SW_CARD_DISABLED = 0x02, 2892286441Srpaulo IWM_CT_KILL_CARD_DISABLED = 0x04, 2893286441Srpaulo IWM_HALT_CARD_DISABLED = 0x08, 2894286441Srpaulo IWM_CARD_DISABLED_MSK = 0x0f, 2895286441Srpaulo IWM_CARD_IS_RX_ON = 0x10, 2896286441Srpaulo}; 2897286441Srpaulo 2898286441Srpaulo/** 2899286441Srpaulo * struct iwm_radio_version_notif - information on the radio version 2900286441Srpaulo * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2901286441Srpaulo * @flags: %iwm_card_state_flags 2902286441Srpaulo */ 2903286441Srpaulostruct iwm_card_state_notif { 2904286441Srpaulo uint32_t flags; 2905286441Srpaulo} __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2906286441Srpaulo 2907286441Srpaulo/** 2908286441Srpaulo * struct iwm_missed_beacons_notif - information on missed beacons 2909286441Srpaulo * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2910286441Srpaulo * @mac_id: interface ID 2911286441Srpaulo * @consec_missed_beacons_since_last_rx: number of consecutive missed 2912286441Srpaulo * beacons since last RX. 2913286441Srpaulo * @consec_missed_beacons: number of consecutive missed beacons 2914286441Srpaulo * @num_expected_beacons: 2915286441Srpaulo * @num_recvd_beacons: 2916286441Srpaulo */ 2917286441Srpaulostruct iwm_missed_beacons_notif { 2918286441Srpaulo uint32_t mac_id; 2919286441Srpaulo uint32_t consec_missed_beacons_since_last_rx; 2920286441Srpaulo uint32_t consec_missed_beacons; 2921286441Srpaulo uint32_t num_expected_beacons; 2922286441Srpaulo uint32_t num_recvd_beacons; 2923286441Srpaulo} __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2924286441Srpaulo 2925286441Srpaulo/** 2926303628Ssbruno * struct iwm_mfuart_load_notif - mfuart image version & status 2927303628Ssbruno * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2928303628Ssbruno * @installed_ver: installed image version 2929303628Ssbruno * @external_ver: external image version 2930303628Ssbruno * @status: MFUART loading status 2931303628Ssbruno * @duration: MFUART loading time 2932303628Ssbruno*/ 2933303628Ssbrunostruct iwm_mfuart_load_notif { 2934303628Ssbruno uint32_t installed_ver; 2935303628Ssbruno uint32_t external_ver; 2936303628Ssbruno uint32_t status; 2937303628Ssbruno uint32_t duration; 2938303628Ssbruno} __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2939303628Ssbruno 2940303628Ssbruno/** 2941286441Srpaulo * struct iwm_set_calib_default_cmd - set default value for calibration. 2942286441Srpaulo * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2943286441Srpaulo * @calib_index: the calibration to set value for 2944286441Srpaulo * @length: of data 2945286441Srpaulo * @data: the value to set for the calibration result 2946286441Srpaulo */ 2947286441Srpaulostruct iwm_set_calib_default_cmd { 2948286441Srpaulo uint16_t calib_index; 2949286441Srpaulo uint16_t length; 2950286441Srpaulo uint8_t data[0]; 2951286441Srpaulo} __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2952286441Srpaulo 2953286441Srpaulo#define IWM_MAX_PORT_ID_NUM 2 2954286441Srpaulo#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2955286441Srpaulo 2956286441Srpaulo/** 2957286441Srpaulo * struct iwm_mcast_filter_cmd - configure multicast filter. 2958286441Srpaulo * @filter_own: Set 1 to filter out multicast packets sent by station itself 2959286441Srpaulo * @port_id: Multicast MAC addresses array specifier. This is a strange way 2960286441Srpaulo * to identify network interface adopted in host-device IF. 2961286441Srpaulo * It is used by FW as index in array of addresses. This array has 2962286441Srpaulo * IWM_MAX_PORT_ID_NUM members. 2963286441Srpaulo * @count: Number of MAC addresses in the array 2964286441Srpaulo * @pass_all: Set 1 to pass all multicast packets. 2965286441Srpaulo * @bssid: current association BSSID. 2966286441Srpaulo * @addr_list: Place holder for array of MAC addresses. 2967286441Srpaulo * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2968286441Srpaulo */ 2969286441Srpaulostruct iwm_mcast_filter_cmd { 2970286441Srpaulo uint8_t filter_own; 2971286441Srpaulo uint8_t port_id; 2972286441Srpaulo uint8_t count; 2973286441Srpaulo uint8_t pass_all; 2974286441Srpaulo uint8_t bssid[6]; 2975286441Srpaulo uint8_t reserved[2]; 2976286441Srpaulo uint8_t addr_list[0]; 2977286441Srpaulo} __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2978286441Srpaulo 2979286441Srpaulostruct iwm_mvm_statistics_dbg { 2980286441Srpaulo uint32_t burst_check; 2981286441Srpaulo uint32_t burst_count; 2982286441Srpaulo uint32_t wait_for_silence_timeout_cnt; 2983286441Srpaulo uint32_t reserved[3]; 2984286441Srpaulo} __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2985286441Srpaulo 2986286441Srpaulostruct iwm_mvm_statistics_div { 2987286441Srpaulo uint32_t tx_on_a; 2988286441Srpaulo uint32_t tx_on_b; 2989286441Srpaulo uint32_t exec_time; 2990286441Srpaulo uint32_t probe_time; 2991286441Srpaulo uint32_t rssi_ant; 2992286441Srpaulo uint32_t reserved2; 2993286441Srpaulo} __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2994286441Srpaulo 2995286441Srpaulostruct iwm_mvm_statistics_general_common { 2996286441Srpaulo uint32_t temperature; /* radio temperature */ 2997286441Srpaulo uint32_t temperature_m; /* radio voltage */ 2998286441Srpaulo struct iwm_mvm_statistics_dbg dbg; 2999286441Srpaulo uint32_t sleep_time; 3000286441Srpaulo uint32_t slots_out; 3001286441Srpaulo uint32_t slots_idle; 3002286441Srpaulo uint32_t ttl_timestamp; 3003286441Srpaulo struct iwm_mvm_statistics_div div; 3004286441Srpaulo uint32_t rx_enable_counter; 3005286441Srpaulo /* 3006286441Srpaulo * num_of_sos_states: 3007286441Srpaulo * count the number of times we have to re-tune 3008286441Srpaulo * in order to get out of bad PHY status 3009286441Srpaulo */ 3010286441Srpaulo uint32_t num_of_sos_states; 3011286441Srpaulo} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3012286441Srpaulo 3013286441Srpaulostruct iwm_mvm_statistics_rx_non_phy { 3014286441Srpaulo uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3015286441Srpaulo uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3016286441Srpaulo uint32_t non_bssid_frames; /* number of frames with BSSID that 3017286441Srpaulo * doesn't belong to the STA BSSID */ 3018286441Srpaulo uint32_t filtered_frames; /* count frames that were dumped in the 3019286441Srpaulo * filtering process */ 3020286441Srpaulo uint32_t non_channel_beacons; /* beacons with our bss id but not on 3021286441Srpaulo * our serving channel */ 3022286441Srpaulo uint32_t channel_beacons; /* beacons with our bss id and in our 3023286441Srpaulo * serving channel */ 3024286441Srpaulo uint32_t num_missed_bcon; /* number of missed beacons */ 3025286441Srpaulo uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3026286441Srpaulo * ADC was in saturation */ 3027286441Srpaulo uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3028286441Srpaulo * for INA */ 3029286441Srpaulo uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3030286441Srpaulo uint32_t interference_data_flag; /* flag for interference data 3031286441Srpaulo * availability. 1 when data is 3032286441Srpaulo * available. */ 3033286441Srpaulo uint32_t channel_load; /* counts RX Enable time in uSec */ 3034286441Srpaulo uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3035286441Srpaulo * and CCK) counter */ 3036286441Srpaulo uint32_t beacon_rssi_a; 3037286441Srpaulo uint32_t beacon_rssi_b; 3038286441Srpaulo uint32_t beacon_rssi_c; 3039286441Srpaulo uint32_t beacon_energy_a; 3040286441Srpaulo uint32_t beacon_energy_b; 3041286441Srpaulo uint32_t beacon_energy_c; 3042286441Srpaulo uint32_t num_bt_kills; 3043286441Srpaulo uint32_t mac_id; 3044286441Srpaulo uint32_t directed_data_mpdu; 3045286441Srpaulo} __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3046286441Srpaulo 3047286441Srpaulostruct iwm_mvm_statistics_rx_phy { 3048286441Srpaulo uint32_t ina_cnt; 3049286441Srpaulo uint32_t fina_cnt; 3050286441Srpaulo uint32_t plcp_err; 3051286441Srpaulo uint32_t crc32_err; 3052286441Srpaulo uint32_t overrun_err; 3053286441Srpaulo uint32_t early_overrun_err; 3054286441Srpaulo uint32_t crc32_good; 3055286441Srpaulo uint32_t false_alarm_cnt; 3056286441Srpaulo uint32_t fina_sync_err_cnt; 3057286441Srpaulo uint32_t sfd_timeout; 3058286441Srpaulo uint32_t fina_timeout; 3059286441Srpaulo uint32_t unresponded_rts; 3060286441Srpaulo uint32_t rxe_frame_limit_overrun; 3061286441Srpaulo uint32_t sent_ack_cnt; 3062286441Srpaulo uint32_t sent_cts_cnt; 3063286441Srpaulo uint32_t sent_ba_rsp_cnt; 3064286441Srpaulo uint32_t dsp_self_kill; 3065286441Srpaulo uint32_t mh_format_err; 3066286441Srpaulo uint32_t re_acq_main_rssi_sum; 3067286441Srpaulo uint32_t reserved; 3068286441Srpaulo} __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3069286441Srpaulo 3070286441Srpaulostruct iwm_mvm_statistics_rx_ht_phy { 3071286441Srpaulo uint32_t plcp_err; 3072286441Srpaulo uint32_t overrun_err; 3073286441Srpaulo uint32_t early_overrun_err; 3074286441Srpaulo uint32_t crc32_good; 3075286441Srpaulo uint32_t crc32_err; 3076286441Srpaulo uint32_t mh_format_err; 3077286441Srpaulo uint32_t agg_crc32_good; 3078286441Srpaulo uint32_t agg_mpdu_cnt; 3079286441Srpaulo uint32_t agg_cnt; 3080286441Srpaulo uint32_t unsupport_mcs; 3081286441Srpaulo} __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3082286441Srpaulo 3083286441Srpaulo#define IWM_MAX_CHAINS 3 3084286441Srpaulo 3085286441Srpaulostruct iwm_mvm_statistics_tx_non_phy_agg { 3086286441Srpaulo uint32_t ba_timeout; 3087286441Srpaulo uint32_t ba_reschedule_frames; 3088286441Srpaulo uint32_t scd_query_agg_frame_cnt; 3089286441Srpaulo uint32_t scd_query_no_agg; 3090286441Srpaulo uint32_t scd_query_agg; 3091286441Srpaulo uint32_t scd_query_mismatch; 3092286441Srpaulo uint32_t frame_not_ready; 3093286441Srpaulo uint32_t underrun; 3094286441Srpaulo uint32_t bt_prio_kill; 3095286441Srpaulo uint32_t rx_ba_rsp_cnt; 3096286441Srpaulo int8_t txpower[IWM_MAX_CHAINS]; 3097286441Srpaulo int8_t reserved; 3098286441Srpaulo uint32_t reserved2; 3099286441Srpaulo} __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3100286441Srpaulo 3101286441Srpaulostruct iwm_mvm_statistics_tx_channel_width { 3102286441Srpaulo uint32_t ext_cca_narrow_ch20[1]; 3103286441Srpaulo uint32_t ext_cca_narrow_ch40[2]; 3104286441Srpaulo uint32_t ext_cca_narrow_ch80[3]; 3105286441Srpaulo uint32_t ext_cca_narrow_ch160[4]; 3106286441Srpaulo uint32_t last_tx_ch_width_indx; 3107286441Srpaulo uint32_t rx_detected_per_ch_width[4]; 3108286441Srpaulo uint32_t success_per_ch_width[4]; 3109286441Srpaulo uint32_t fail_per_ch_width[4]; 3110286441Srpaulo}; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3111286441Srpaulo 3112286441Srpaulostruct iwm_mvm_statistics_tx { 3113286441Srpaulo uint32_t preamble_cnt; 3114286441Srpaulo uint32_t rx_detected_cnt; 3115286441Srpaulo uint32_t bt_prio_defer_cnt; 3116286441Srpaulo uint32_t bt_prio_kill_cnt; 3117286441Srpaulo uint32_t few_bytes_cnt; 3118286441Srpaulo uint32_t cts_timeout; 3119286441Srpaulo uint32_t ack_timeout; 3120286441Srpaulo uint32_t expected_ack_cnt; 3121286441Srpaulo uint32_t actual_ack_cnt; 3122286441Srpaulo uint32_t dump_msdu_cnt; 3123286441Srpaulo uint32_t burst_abort_next_frame_mismatch_cnt; 3124286441Srpaulo uint32_t burst_abort_missing_next_frame_cnt; 3125286441Srpaulo uint32_t cts_timeout_collision; 3126286441Srpaulo uint32_t ack_or_ba_timeout_collision; 3127286441Srpaulo struct iwm_mvm_statistics_tx_non_phy_agg agg; 3128286441Srpaulo struct iwm_mvm_statistics_tx_channel_width channel_width; 3129286441Srpaulo} __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3130286441Srpaulo 3131286441Srpaulo 3132286441Srpaulostruct iwm_mvm_statistics_bt_activity { 3133286441Srpaulo uint32_t hi_priority_tx_req_cnt; 3134286441Srpaulo uint32_t hi_priority_tx_denied_cnt; 3135286441Srpaulo uint32_t lo_priority_tx_req_cnt; 3136286441Srpaulo uint32_t lo_priority_tx_denied_cnt; 3137286441Srpaulo uint32_t hi_priority_rx_req_cnt; 3138286441Srpaulo uint32_t hi_priority_rx_denied_cnt; 3139286441Srpaulo uint32_t lo_priority_rx_req_cnt; 3140286441Srpaulo uint32_t lo_priority_rx_denied_cnt; 3141286441Srpaulo} __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3142286441Srpaulo 3143286441Srpaulostruct iwm_mvm_statistics_general { 3144286441Srpaulo struct iwm_mvm_statistics_general_common common; 3145286441Srpaulo uint32_t beacon_filtered; 3146286441Srpaulo uint32_t missed_beacons; 3147286441Srpaulo int8_t beacon_filter_average_energy; 3148286441Srpaulo int8_t beacon_filter_reason; 3149286441Srpaulo int8_t beacon_filter_current_energy; 3150286441Srpaulo int8_t beacon_filter_reserved; 3151286441Srpaulo uint32_t beacon_filter_delta_time; 3152286441Srpaulo struct iwm_mvm_statistics_bt_activity bt_activity; 3153286441Srpaulo} __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3154286441Srpaulo 3155286441Srpaulostruct iwm_mvm_statistics_rx { 3156286441Srpaulo struct iwm_mvm_statistics_rx_phy ofdm; 3157286441Srpaulo struct iwm_mvm_statistics_rx_phy cck; 3158286441Srpaulo struct iwm_mvm_statistics_rx_non_phy general; 3159286441Srpaulo struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3160286441Srpaulo} __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3161286441Srpaulo 3162286441Srpaulo/* 3163286441Srpaulo * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3164286441Srpaulo * 3165286441Srpaulo * By default, uCode issues this notification after receiving a beacon 3166286441Srpaulo * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3167286441Srpaulo * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3168286441Srpaulo * 3169286441Srpaulo * Statistics counters continue to increment beacon after beacon, but are 3170286441Srpaulo * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3171286441Srpaulo * 0x9c with CLEAR_STATS bit set (see above). 3172286441Srpaulo * 3173286441Srpaulo * uCode also issues this notification during scans. uCode clears statistics 3174286441Srpaulo * appropriately so that each notification contains statistics for only the 3175286441Srpaulo * one channel that has just been scanned. 3176286441Srpaulo */ 3177286441Srpaulo 3178286441Srpaulostruct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3179286441Srpaulo uint32_t flag; 3180286441Srpaulo struct iwm_mvm_statistics_rx rx; 3181286441Srpaulo struct iwm_mvm_statistics_tx tx; 3182286441Srpaulo struct iwm_mvm_statistics_general general; 3183286441Srpaulo} __packed; 3184286441Srpaulo 3185286441Srpaulo/*********************************** 3186286441Srpaulo * Smart Fifo API 3187286441Srpaulo ***********************************/ 3188286441Srpaulo/* Smart Fifo state */ 3189286441Srpauloenum iwm_sf_state { 3190286441Srpaulo IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3191286441Srpaulo IWM_SF_FULL_ON, 3192286441Srpaulo IWM_SF_UNINIT, 3193286441Srpaulo IWM_SF_INIT_OFF, 3194286441Srpaulo IWM_SF_HW_NUM_STATES 3195286441Srpaulo}; 3196286441Srpaulo 3197286441Srpaulo/* Smart Fifo possible scenario */ 3198286441Srpauloenum iwm_sf_scenario { 3199286441Srpaulo IWM_SF_SCENARIO_SINGLE_UNICAST, 3200286441Srpaulo IWM_SF_SCENARIO_AGG_UNICAST, 3201286441Srpaulo IWM_SF_SCENARIO_MULTICAST, 3202286441Srpaulo IWM_SF_SCENARIO_BA_RESP, 3203286441Srpaulo IWM_SF_SCENARIO_TX_RESP, 3204286441Srpaulo IWM_SF_NUM_SCENARIO 3205286441Srpaulo}; 3206286441Srpaulo 3207286441Srpaulo#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3208286441Srpaulo#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3209286441Srpaulo 3210286441Srpaulo/* smart FIFO default values */ 3211286441Srpaulo#define IWM_SF_W_MARK_SISO 4096 3212286441Srpaulo#define IWM_SF_W_MARK_MIMO2 8192 3213286441Srpaulo#define IWM_SF_W_MARK_MIMO3 6144 3214286441Srpaulo#define IWM_SF_W_MARK_LEGACY 4096 3215286441Srpaulo#define IWM_SF_W_MARK_SCAN 4096 3216286441Srpaulo 3217303628Ssbruno/* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3218303628Ssbruno#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3219303628Ssbruno#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3220303628Ssbruno#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3221303628Ssbruno#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3222303628Ssbruno#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3223303628Ssbruno#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3224303628Ssbruno#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3225303628Ssbruno#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3226303628Ssbruno#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3227303628Ssbruno#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3228303628Ssbruno 3229286441Srpaulo/* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3230286441Srpaulo#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3231286441Srpaulo#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3232286441Srpaulo#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3233286441Srpaulo#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3234286441Srpaulo#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3235286441Srpaulo#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3236286441Srpaulo#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3237286441Srpaulo#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3238286441Srpaulo#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3239286441Srpaulo#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3240286441Srpaulo 3241286441Srpaulo#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3242286441Srpaulo 3243303628Ssbruno#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3244303628Ssbruno 3245286441Srpaulo/** 3246286441Srpaulo * Smart Fifo configuration command. 3247286441Srpaulo * @state: smart fifo state, types listed in iwm_sf_sate. 3248298955Spfg * @watermark: Minimum allowed available free space in RXF for transient state. 3249286441Srpaulo * @long_delay_timeouts: aging and idle timer values for each scenario 3250286441Srpaulo * in long delay state. 3251286441Srpaulo * @full_on_timeouts: timer values for each scenario in full on state. 3252286441Srpaulo */ 3253286441Srpaulostruct iwm_sf_cfg_cmd { 3254286441Srpaulo enum iwm_sf_state state; 3255286441Srpaulo uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3256286441Srpaulo uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3257286441Srpaulo uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3258286441Srpaulo} __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3259286441Srpaulo 3260286441Srpaulo/* 3261286441Srpaulo * END mvm/fw-api.h 3262286441Srpaulo */ 3263286441Srpaulo 3264286441Srpaulo/* 3265286441Srpaulo * BEGIN mvm/fw-api-mac.h 3266286441Srpaulo */ 3267286441Srpaulo 3268286441Srpaulo/* 3269286441Srpaulo * The first MAC indices (starting from 0) 3270286441Srpaulo * are available to the driver, AUX follows 3271286441Srpaulo */ 3272286441Srpaulo#define IWM_MAC_INDEX_AUX 4 3273286441Srpaulo#define IWM_MAC_INDEX_MIN_DRIVER 0 3274286441Srpaulo#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3275286441Srpaulo 3276286441Srpauloenum iwm_ac { 3277286441Srpaulo IWM_AC_BK, 3278286441Srpaulo IWM_AC_BE, 3279286441Srpaulo IWM_AC_VI, 3280286441Srpaulo IWM_AC_VO, 3281286441Srpaulo IWM_AC_NUM, 3282286441Srpaulo}; 3283286441Srpaulo 3284286441Srpaulo/** 3285286441Srpaulo * enum iwm_mac_protection_flags - MAC context flags 3286286441Srpaulo * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3287286441Srpaulo * this will require CCK RTS/CTS2self. 3288286441Srpaulo * RTS/CTS will protect full burst time. 3289286441Srpaulo * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3290286441Srpaulo * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3291286441Srpaulo * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3292286441Srpaulo */ 3293286441Srpauloenum iwm_mac_protection_flags { 3294286441Srpaulo IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3295286441Srpaulo IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3296286441Srpaulo IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3297286441Srpaulo IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3298286441Srpaulo}; 3299286441Srpaulo 3300286441Srpaulo#define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3301286441Srpaulo#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3302286441Srpaulo 3303286441Srpaulo/** 3304286441Srpaulo * enum iwm_mac_types - Supported MAC types 3305286441Srpaulo * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3306286441Srpaulo * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3307286441Srpaulo * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3308286441Srpaulo * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3309286441Srpaulo * @IWM_FW_MAC_TYPE_IBSS: IBSS 3310286441Srpaulo * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3311286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3312286441Srpaulo * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3313286441Srpaulo * @IWM_FW_MAC_TYPE_GO: P2P GO 3314286441Srpaulo * @IWM_FW_MAC_TYPE_TEST: ? 3315286441Srpaulo * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3316286441Srpaulo */ 3317286441Srpauloenum iwm_mac_types { 3318286441Srpaulo IWM_FW_MAC_TYPE_FIRST = 1, 3319286441Srpaulo IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3320286441Srpaulo IWM_FW_MAC_TYPE_LISTENER, 3321286441Srpaulo IWM_FW_MAC_TYPE_PIBSS, 3322286441Srpaulo IWM_FW_MAC_TYPE_IBSS, 3323286441Srpaulo IWM_FW_MAC_TYPE_BSS_STA, 3324286441Srpaulo IWM_FW_MAC_TYPE_P2P_DEVICE, 3325286441Srpaulo IWM_FW_MAC_TYPE_P2P_STA, 3326286441Srpaulo IWM_FW_MAC_TYPE_GO, 3327286441Srpaulo IWM_FW_MAC_TYPE_TEST, 3328286441Srpaulo IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3329286441Srpaulo}; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3330286441Srpaulo 3331286441Srpaulo/** 3332286441Srpaulo * enum iwm_tsf_id - TSF hw timer ID 3333286441Srpaulo * @IWM_TSF_ID_A: use TSF A 3334286441Srpaulo * @IWM_TSF_ID_B: use TSF B 3335286441Srpaulo * @IWM_TSF_ID_C: use TSF C 3336286441Srpaulo * @IWM_TSF_ID_D: use TSF D 3337286441Srpaulo * @IWM_NUM_TSF_IDS: number of TSF timers available 3338286441Srpaulo */ 3339286441Srpauloenum iwm_tsf_id { 3340286441Srpaulo IWM_TSF_ID_A = 0, 3341286441Srpaulo IWM_TSF_ID_B = 1, 3342286441Srpaulo IWM_TSF_ID_C = 2, 3343286441Srpaulo IWM_TSF_ID_D = 3, 3344286441Srpaulo IWM_NUM_TSF_IDS = 4, 3345286441Srpaulo}; /* IWM_TSF_ID_API_E_VER_1 */ 3346286441Srpaulo 3347286441Srpaulo/** 3348286441Srpaulo * struct iwm_mac_data_ap - configuration data for AP MAC context 3349286441Srpaulo * @beacon_time: beacon transmit time in system time 3350286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 3351286441Srpaulo * @bi: beacon interval in TU 3352286441Srpaulo * @bi_reciprocal: 2^32 / bi 3353286441Srpaulo * @dtim_interval: dtim transmit time in TU 3354286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval 3355286441Srpaulo * @mcast_qid: queue ID for multicast traffic 3356286441Srpaulo * @beacon_template: beacon template ID 3357286441Srpaulo */ 3358286441Srpaulostruct iwm_mac_data_ap { 3359286441Srpaulo uint32_t beacon_time; 3360286441Srpaulo uint64_t beacon_tsf; 3361286441Srpaulo uint32_t bi; 3362286441Srpaulo uint32_t bi_reciprocal; 3363286441Srpaulo uint32_t dtim_interval; 3364286441Srpaulo uint32_t dtim_reciprocal; 3365286441Srpaulo uint32_t mcast_qid; 3366286441Srpaulo uint32_t beacon_template; 3367286441Srpaulo} __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3368286441Srpaulo 3369286441Srpaulo/** 3370286441Srpaulo * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3371286441Srpaulo * @beacon_time: beacon transmit time in system time 3372286441Srpaulo * @beacon_tsf: beacon transmit time in TSF 3373286441Srpaulo * @bi: beacon interval in TU 3374286441Srpaulo * @bi_reciprocal: 2^32 / bi 3375286441Srpaulo * @beacon_template: beacon template ID 3376286441Srpaulo */ 3377286441Srpaulostruct iwm_mac_data_ibss { 3378286441Srpaulo uint32_t beacon_time; 3379286441Srpaulo uint64_t beacon_tsf; 3380286441Srpaulo uint32_t bi; 3381286441Srpaulo uint32_t bi_reciprocal; 3382286441Srpaulo uint32_t beacon_template; 3383286441Srpaulo} __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3384286441Srpaulo 3385286441Srpaulo/** 3386286441Srpaulo * struct iwm_mac_data_sta - configuration data for station MAC context 3387286441Srpaulo * @is_assoc: 1 for associated state, 0 otherwise 3388286441Srpaulo * @dtim_time: DTIM arrival time in system time 3389286441Srpaulo * @dtim_tsf: DTIM arrival time in TSF 3390286441Srpaulo * @bi: beacon interval in TU, applicable only when associated 3391286441Srpaulo * @bi_reciprocal: 2^32 / bi , applicable only when associated 3392286441Srpaulo * @dtim_interval: DTIM interval in TU, applicable only when associated 3393286441Srpaulo * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3394286441Srpaulo * @listen_interval: in beacon intervals, applicable only when associated 3395286441Srpaulo * @assoc_id: unique ID assigned by the AP during association 3396286441Srpaulo */ 3397286441Srpaulostruct iwm_mac_data_sta { 3398286441Srpaulo uint32_t is_assoc; 3399286441Srpaulo uint32_t dtim_time; 3400286441Srpaulo uint64_t dtim_tsf; 3401286441Srpaulo uint32_t bi; 3402286441Srpaulo uint32_t bi_reciprocal; 3403286441Srpaulo uint32_t dtim_interval; 3404286441Srpaulo uint32_t dtim_reciprocal; 3405286441Srpaulo uint32_t listen_interval; 3406286441Srpaulo uint32_t assoc_id; 3407286441Srpaulo uint32_t assoc_beacon_arrive_time; 3408286441Srpaulo} __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3409286441Srpaulo 3410286441Srpaulo/** 3411286441Srpaulo * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3412286441Srpaulo * @ap: iwm_mac_data_ap struct with most config data 3413286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3414286441Srpaulo * 0 indicates that there is no CT window. 3415286441Srpaulo * @opp_ps_enabled: indicate that opportunistic PS allowed 3416286441Srpaulo */ 3417286441Srpaulostruct iwm_mac_data_go { 3418286441Srpaulo struct iwm_mac_data_ap ap; 3419286441Srpaulo uint32_t ctwin; 3420286441Srpaulo uint32_t opp_ps_enabled; 3421286441Srpaulo} __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3422286441Srpaulo 3423286441Srpaulo/** 3424286441Srpaulo * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3425286441Srpaulo * @sta: iwm_mac_data_sta struct with most config data 3426286441Srpaulo * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3427286441Srpaulo * 0 indicates that there is no CT window. 3428286441Srpaulo */ 3429286441Srpaulostruct iwm_mac_data_p2p_sta { 3430286441Srpaulo struct iwm_mac_data_sta sta; 3431286441Srpaulo uint32_t ctwin; 3432286441Srpaulo} __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3433286441Srpaulo 3434286441Srpaulo/** 3435286441Srpaulo * struct iwm_mac_data_pibss - Pseudo IBSS config data 3436286441Srpaulo * @stats_interval: interval in TU between statistics notifications to host. 3437286441Srpaulo */ 3438286441Srpaulostruct iwm_mac_data_pibss { 3439286441Srpaulo uint32_t stats_interval; 3440286441Srpaulo} __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3441286441Srpaulo 3442286441Srpaulo/* 3443286441Srpaulo * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3444286441Srpaulo * context. 3445286441Srpaulo * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3446286441Srpaulo * other channels as well. This should be to true only in case that the 3447286441Srpaulo * device is discoverable and there is an active GO. Note that setting this 3448286441Srpaulo * field when not needed, will increase the number of interrupts and have 3449286441Srpaulo * effect on the platform power, as this setting opens the Rx filters on 3450286441Srpaulo * all macs. 3451286441Srpaulo */ 3452286441Srpaulostruct iwm_mac_data_p2p_dev { 3453286441Srpaulo uint32_t is_disc_extended; 3454286441Srpaulo} __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3455286441Srpaulo 3456286441Srpaulo/** 3457286441Srpaulo * enum iwm_mac_filter_flags - MAC context filter flags 3458286441Srpaulo * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3459286441Srpaulo * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3460286441Srpaulo * control frames to the host 3461286441Srpaulo * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3462286441Srpaulo * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3463286441Srpaulo * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3464286441Srpaulo * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3465286441Srpaulo * (in station mode when associated) 3466286441Srpaulo * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3467286441Srpaulo * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3468286441Srpaulo * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3469286441Srpaulo */ 3470286441Srpauloenum iwm_mac_filter_flags { 3471286441Srpaulo IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3472286441Srpaulo IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3473286441Srpaulo IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3474286441Srpaulo IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3475286441Srpaulo IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3476286441Srpaulo IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3477286441Srpaulo IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3478286441Srpaulo IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3479286441Srpaulo IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3480286441Srpaulo}; 3481286441Srpaulo 3482286441Srpaulo/** 3483286441Srpaulo * enum iwm_mac_qos_flags - QoS flags 3484286441Srpaulo * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3485286441Srpaulo * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3486286441Srpaulo * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3487286441Srpaulo * 3488286441Srpaulo */ 3489286441Srpauloenum iwm_mac_qos_flags { 3490286441Srpaulo IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3491286441Srpaulo IWM_MAC_QOS_FLG_TGN = (1 << 1), 3492286441Srpaulo IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3493286441Srpaulo}; 3494286441Srpaulo 3495286441Srpaulo/** 3496286441Srpaulo * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3497286441Srpaulo * @cw_min: Contention window, start value in numbers of slots. 3498286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x0f. 3499286441Srpaulo * @cw_max: Contention window, max value in numbers of slots. 3500286441Srpaulo * Should be a power-of-2, minus 1. Device's default is 0x3f. 3501286441Srpaulo * @aifsn: Number of slots in Arbitration Interframe Space (before 3502286441Srpaulo * performing random backoff timing prior to Tx). Device default 1. 3503286441Srpaulo * @fifos_mask: FIFOs used by this MAC for this AC 3504286441Srpaulo * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3505286441Srpaulo * 3506286441Srpaulo * One instance of this config struct for each of 4 EDCA access categories 3507286441Srpaulo * in struct iwm_qosparam_cmd. 3508286441Srpaulo * 3509286441Srpaulo * Device will automatically increase contention window by (2*CW) + 1 for each 3510286441Srpaulo * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3511286441Srpaulo * value, to cap the CW value. 3512286441Srpaulo */ 3513286441Srpaulostruct iwm_ac_qos { 3514286441Srpaulo uint16_t cw_min; 3515286441Srpaulo uint16_t cw_max; 3516286441Srpaulo uint8_t aifsn; 3517286441Srpaulo uint8_t fifos_mask; 3518286441Srpaulo uint16_t edca_txop; 3519286441Srpaulo} __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3520286441Srpaulo 3521286441Srpaulo/** 3522286441Srpaulo * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3523286441Srpaulo * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3524286441Srpaulo * @id_and_color: ID and color of the MAC 3525286441Srpaulo * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3526286441Srpaulo * @mac_type: one of IWM_FW_MAC_TYPE_* 3527286441Srpaulo * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3528286441Srpaulo * @node_addr: MAC address 3529286441Srpaulo * @bssid_addr: BSSID 3530286441Srpaulo * @cck_rates: basic rates available for CCK 3531286441Srpaulo * @ofdm_rates: basic rates available for OFDM 3532286441Srpaulo * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3533286441Srpaulo * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3534286441Srpaulo * @short_slot: 0x10 for enabling short slots, 0 otherwise 3535286441Srpaulo * @filter_flags: combination of IWM_MAC_FILTER_* 3536286441Srpaulo * @qos_flags: from IWM_MAC_QOS_FLG_* 3537286441Srpaulo * @ac: one iwm_mac_qos configuration for each AC 3538286441Srpaulo * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3539286441Srpaulo */ 3540286441Srpaulostruct iwm_mac_ctx_cmd { 3541286441Srpaulo /* COMMON_INDEX_HDR_API_S_VER_1 */ 3542286441Srpaulo uint32_t id_and_color; 3543286441Srpaulo uint32_t action; 3544286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3545286441Srpaulo uint32_t mac_type; 3546286441Srpaulo uint32_t tsf_id; 3547286441Srpaulo uint8_t node_addr[6]; 3548286441Srpaulo uint16_t reserved_for_node_addr; 3549286441Srpaulo uint8_t bssid_addr[6]; 3550286441Srpaulo uint16_t reserved_for_bssid_addr; 3551286441Srpaulo uint32_t cck_rates; 3552286441Srpaulo uint32_t ofdm_rates; 3553286441Srpaulo uint32_t protection_flags; 3554286441Srpaulo uint32_t cck_short_preamble; 3555286441Srpaulo uint32_t short_slot; 3556286441Srpaulo uint32_t filter_flags; 3557286441Srpaulo /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3558286441Srpaulo uint32_t qos_flags; 3559286441Srpaulo struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3560286441Srpaulo /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3561286441Srpaulo union { 3562286441Srpaulo struct iwm_mac_data_ap ap; 3563286441Srpaulo struct iwm_mac_data_go go; 3564286441Srpaulo struct iwm_mac_data_sta sta; 3565286441Srpaulo struct iwm_mac_data_p2p_sta p2p_sta; 3566286441Srpaulo struct iwm_mac_data_p2p_dev p2p_dev; 3567286441Srpaulo struct iwm_mac_data_pibss pibss; 3568286441Srpaulo struct iwm_mac_data_ibss ibss; 3569286441Srpaulo }; 3570286441Srpaulo} __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3571286441Srpaulo 3572286441Srpaulostatic inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3573286441Srpaulo{ 3574286441Srpaulo if (!v) 3575286441Srpaulo return 0; 3576286441Srpaulo return 0xFFFFFFFF / v; 3577286441Srpaulo} 3578286441Srpaulo 3579286441Srpaulo#define IWM_NONQOS_SEQ_GET 0x1 3580286441Srpaulo#define IWM_NONQOS_SEQ_SET 0x2 3581286441Srpaulostruct iwm_nonqos_seq_query_cmd { 3582286441Srpaulo uint32_t get_set_flag; 3583286441Srpaulo uint32_t mac_id_n_color; 3584286441Srpaulo uint16_t value; 3585286441Srpaulo uint16_t reserved; 3586286441Srpaulo} __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3587286441Srpaulo 3588286441Srpaulo/* 3589286441Srpaulo * END mvm/fw-api-mac.h 3590286441Srpaulo */ 3591286441Srpaulo 3592286441Srpaulo/* 3593286441Srpaulo * BEGIN mvm/fw-api-power.h 3594286441Srpaulo */ 3595286441Srpaulo 3596286441Srpaulo/* Power Management Commands, Responses, Notifications */ 3597286441Srpaulo 3598286441Srpaulo/* Radio LP RX Energy Threshold measured in dBm */ 3599286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3600286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3601286441Srpaulo#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3602286441Srpaulo 3603286441Srpaulo/** 3604286441Srpaulo * enum iwm_scan_flags - masks for power table command flags 3605286441Srpaulo * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3606286441Srpaulo * receiver and transmitter. '0' - does not allow. 3607286441Srpaulo * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3608286441Srpaulo * '1' Driver enables PM (use rest of parameters) 3609286441Srpaulo * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3610286441Srpaulo * '1' PM could sleep over DTIM till listen Interval. 3611286441Srpaulo * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3612286441Srpaulo * access categories are both delivery and trigger enabled. 3613286441Srpaulo * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3614286441Srpaulo * PBW Snoozing enabled 3615286441Srpaulo * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3616286441Srpaulo * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3617286441Srpaulo * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3618286441Srpaulo * detection enablement 3619286441Srpaulo*/ 3620286441Srpauloenum iwm_power_flags { 3621286441Srpaulo IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3622286441Srpaulo IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3623286441Srpaulo IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3624286441Srpaulo IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3625286441Srpaulo IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3626286441Srpaulo IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3627286441Srpaulo IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3628286441Srpaulo IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3629286441Srpaulo}; 3630286441Srpaulo 3631286441Srpaulo#define IWM_POWER_VEC_SIZE 5 3632286441Srpaulo 3633286441Srpaulo/** 3634286441Srpaulo * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3635286441Srpaulo * is used also with a new power API for device wide power settings. 3636286441Srpaulo * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3637286441Srpaulo * 3638286441Srpaulo * @flags: Power table command flags from IWM_POWER_FLAGS_* 3639286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3640286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3641286441Srpaulo * set regardless of power scheme or current power state. 3642286441Srpaulo * FW use this value also when PM is disabled. 3643286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3644286441Srpaulo * PSM transition - legacy PM 3645286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3646286441Srpaulo * PSM transition - legacy PM 3647286441Srpaulo * @sleep_interval: not in use 3648286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3649286441Srpaulo * is set. For example, if it is required to skip over 3650286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3651286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3652286441Srpaulo * Default: 80dbm 3653286441Srpaulo */ 3654286441Srpaulostruct iwm_powertable_cmd { 3655286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3656286441Srpaulo uint16_t flags; 3657286441Srpaulo uint8_t keep_alive_seconds; 3658286441Srpaulo uint8_t debug_flags; 3659286441Srpaulo uint32_t rx_data_timeout; 3660286441Srpaulo uint32_t tx_data_timeout; 3661286441Srpaulo uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3662286441Srpaulo uint32_t skip_dtim_periods; 3663286441Srpaulo uint32_t lprx_rssi_threshold; 3664286441Srpaulo} __packed; 3665286441Srpaulo 3666286441Srpaulo/** 3667286441Srpaulo * enum iwm_device_power_flags - masks for device power command flags 3668286441Srpaulo * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3669286441Srpaulo * receiver and transmitter. '0' - does not allow. This flag should be 3670286441Srpaulo * always set to '1' unless one need to disable actual power down for debug 3671286441Srpaulo * purposes. 3672286441Srpaulo * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3673286441Srpaulo * that power management is disabled. '0' Power management is enabled, one 3674286441Srpaulo * of power schemes is applied. 3675286441Srpaulo*/ 3676286441Srpauloenum iwm_device_power_flags { 3677286441Srpaulo IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3678286441Srpaulo IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3679286441Srpaulo}; 3680286441Srpaulo 3681286441Srpaulo/** 3682286441Srpaulo * struct iwm_device_power_cmd - device wide power command. 3683286441Srpaulo * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3684286441Srpaulo * 3685286441Srpaulo * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3686286441Srpaulo */ 3687286441Srpaulostruct iwm_device_power_cmd { 3688286441Srpaulo /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3689286441Srpaulo uint16_t flags; 3690286441Srpaulo uint16_t reserved; 3691286441Srpaulo} __packed; 3692286441Srpaulo 3693286441Srpaulo/** 3694286441Srpaulo * struct iwm_mac_power_cmd - New power command containing uAPSD support 3695286441Srpaulo * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3696286441Srpaulo * @id_and_color: MAC contex identifier 3697286441Srpaulo * @flags: Power table command flags from POWER_FLAGS_* 3698286441Srpaulo * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3699286441Srpaulo * Minimum allowed:- 3 * DTIM. Keep alive period must be 3700286441Srpaulo * set regardless of power scheme or current power state. 3701286441Srpaulo * FW use this value also when PM is disabled. 3702286441Srpaulo * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3703286441Srpaulo * PSM transition - legacy PM 3704286441Srpaulo * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3705286441Srpaulo * PSM transition - legacy PM 3706286441Srpaulo * @sleep_interval: not in use 3707286441Srpaulo * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3708286441Srpaulo * is set. For example, if it is required to skip over 3709286441Srpaulo * one DTIM, this value need to be set to 2 (DTIM periods). 3710286441Srpaulo * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3711286441Srpaulo * PSM transition - uAPSD 3712286441Srpaulo * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3713286441Srpaulo * PSM transition - uAPSD 3714286441Srpaulo * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3715286441Srpaulo * Default: 80dbm 3716286441Srpaulo * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3717286441Srpaulo * @snooze_interval: Maximum time between attempts to retrieve buffered data 3718286441Srpaulo * from the AP [msec] 3719286441Srpaulo * @snooze_window: A window of time in which PBW snoozing insures that all 3720286441Srpaulo * packets received. It is also the minimum time from last 3721286441Srpaulo * received unicast RX packet, before client stops snoozing 3722286441Srpaulo * for data. [msec] 3723286441Srpaulo * @snooze_step: TBD 3724286441Srpaulo * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3725286441Srpaulo * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3726286441Srpaulo * each corresponding AC. 3727286441Srpaulo * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3728286441Srpaulo * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3729286441Srpaulo * values. 3730286441Srpaulo * @heavy_tx_thld_packets: TX threshold measured in number of packets 3731286441Srpaulo * @heavy_rx_thld_packets: RX threshold measured in number of packets 3732286441Srpaulo * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3733286441Srpaulo * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3734286441Srpaulo * @limited_ps_threshold: 3735286441Srpaulo*/ 3736286441Srpaulostruct iwm_mac_power_cmd { 3737286441Srpaulo /* CONTEXT_DESC_API_T_VER_1 */ 3738286441Srpaulo uint32_t id_and_color; 3739286441Srpaulo 3740286441Srpaulo /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3741286441Srpaulo uint16_t flags; 3742286441Srpaulo uint16_t keep_alive_seconds; 3743286441Srpaulo uint32_t rx_data_timeout; 3744286441Srpaulo uint32_t tx_data_timeout; 3745286441Srpaulo uint32_t rx_data_timeout_uapsd; 3746286441Srpaulo uint32_t tx_data_timeout_uapsd; 3747286441Srpaulo uint8_t lprx_rssi_threshold; 3748286441Srpaulo uint8_t skip_dtim_periods; 3749286441Srpaulo uint16_t snooze_interval; 3750286441Srpaulo uint16_t snooze_window; 3751286441Srpaulo uint8_t snooze_step; 3752286441Srpaulo uint8_t qndp_tid; 3753286441Srpaulo uint8_t uapsd_ac_flags; 3754286441Srpaulo uint8_t uapsd_max_sp; 3755286441Srpaulo uint8_t heavy_tx_thld_packets; 3756286441Srpaulo uint8_t heavy_rx_thld_packets; 3757286441Srpaulo uint8_t heavy_tx_thld_percentage; 3758286441Srpaulo uint8_t heavy_rx_thld_percentage; 3759286441Srpaulo uint8_t limited_ps_threshold; 3760286441Srpaulo uint8_t reserved; 3761286441Srpaulo} __packed; 3762286441Srpaulo 3763286441Srpaulo/* 3764286441Srpaulo * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3765286441Srpaulo * associated AP is identified as improperly implementing uAPSD protocol. 3766286441Srpaulo * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3767286441Srpaulo * @sta_id: index of station in uCode's station table - associated AP ID in 3768286441Srpaulo * this context. 3769286441Srpaulo */ 3770286441Srpaulostruct iwm_uapsd_misbehaving_ap_notif { 3771286441Srpaulo uint32_t sta_id; 3772286441Srpaulo uint8_t mac_id; 3773286441Srpaulo uint8_t reserved[3]; 3774286441Srpaulo} __packed; 3775286441Srpaulo 3776286441Srpaulo/** 3777286441Srpaulo * struct iwm_beacon_filter_cmd 3778286441Srpaulo * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3779286441Srpaulo * @id_and_color: MAC contex identifier 3780286441Srpaulo * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3781286441Srpaulo * to driver if delta in Energy values calculated for this and last 3782286441Srpaulo * passed beacon is greater than this threshold. Zero value means that 3783286441Srpaulo * the Energy change is ignored for beacon filtering, and beacon will 3784286441Srpaulo * not be forced to be sent to driver regardless of this delta. Typical 3785286441Srpaulo * energy delta 5dB. 3786286441Srpaulo * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3787286441Srpaulo * Send beacon to driver if delta in Energy values calculated for this 3788286441Srpaulo * and last passed beacon is greater than this threshold. Zero value 3789286441Srpaulo * means that the Energy change is ignored for beacon filtering while in 3790286441Srpaulo * Roaming state, typical energy delta 1dB. 3791286441Srpaulo * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3792286441Srpaulo * calculated for current beacon is less than the threshold, use 3793286441Srpaulo * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3794286441Srpaulo * Threshold. Typical energy threshold is -72dBm. 3795286441Srpaulo * @bf_temp_threshold: This threshold determines the type of temperature 3796286441Srpaulo * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3797286441Srpaulo * If the current temperature is above this threshold - Fast filter 3798286441Srpaulo * will be used, If the current temperature is below this threshold - 3799286441Srpaulo * Slow filter will be used. 3800286441Srpaulo * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3801286441Srpaulo * calculated for this and the last passed beacon is greater than this 3802286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3803286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3804298955Spfg * regardless of whether its temperature has been changed. 3805286441Srpaulo * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3806286441Srpaulo * calculated for this and the last passed beacon is greater than this 3807286441Srpaulo * threshold. Zero value means that the temperature change is ignored for 3808286441Srpaulo * beacon filtering; beacons will not be forced to be sent to driver 3809298955Spfg * regardless of whether its temperature has been changed. 3810286441Srpaulo * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3811286441Srpaulo * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3812286441Srpaulo * for a specific period of time. Units: Beacons. 3813286441Srpaulo * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3814286441Srpaulo * for a longer period of time then this escape-timeout. Units: Beacons. 3815286441Srpaulo * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3816286441Srpaulo */ 3817286441Srpaulostruct iwm_beacon_filter_cmd { 3818286441Srpaulo uint32_t bf_energy_delta; 3819286441Srpaulo uint32_t bf_roaming_energy_delta; 3820286441Srpaulo uint32_t bf_roaming_state; 3821286441Srpaulo uint32_t bf_temp_threshold; 3822286441Srpaulo uint32_t bf_temp_fast_filter; 3823286441Srpaulo uint32_t bf_temp_slow_filter; 3824286441Srpaulo uint32_t bf_enable_beacon_filter; 3825286441Srpaulo uint32_t bf_debug_flag; 3826286441Srpaulo uint32_t bf_escape_timer; 3827286441Srpaulo uint32_t ba_escape_timer; 3828286441Srpaulo uint32_t ba_enable_beacon_abort; 3829286441Srpaulo} __packed; 3830286441Srpaulo 3831286441Srpaulo/* Beacon filtering and beacon abort */ 3832286441Srpaulo#define IWM_BF_ENERGY_DELTA_DEFAULT 5 3833286441Srpaulo#define IWM_BF_ENERGY_DELTA_MAX 255 3834286441Srpaulo#define IWM_BF_ENERGY_DELTA_MIN 0 3835286441Srpaulo 3836286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3837286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3838286441Srpaulo#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3839286441Srpaulo 3840286441Srpaulo#define IWM_BF_ROAMING_STATE_DEFAULT 72 3841286441Srpaulo#define IWM_BF_ROAMING_STATE_MAX 255 3842286441Srpaulo#define IWM_BF_ROAMING_STATE_MIN 0 3843286441Srpaulo 3844286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3845286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MAX 255 3846286441Srpaulo#define IWM_BF_TEMP_THRESHOLD_MIN 0 3847286441Srpaulo 3848286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3849286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MAX 255 3850286441Srpaulo#define IWM_BF_TEMP_FAST_FILTER_MIN 0 3851286441Srpaulo 3852286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3853286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3854286441Srpaulo#define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3855286441Srpaulo 3856286441Srpaulo#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3857286441Srpaulo 3858286441Srpaulo#define IWM_BF_DEBUG_FLAG_DEFAULT 0 3859286441Srpaulo 3860286441Srpaulo#define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3861286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MAX 1024 3862286441Srpaulo#define IWM_BF_ESCAPE_TIMER_MIN 0 3863286441Srpaulo 3864286441Srpaulo#define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3865286441Srpaulo#define IWM_BA_ESCAPE_TIMER_D3 9 3866286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MAX 1024 3867286441Srpaulo#define IWM_BA_ESCAPE_TIMER_MIN 0 3868286441Srpaulo 3869286441Srpaulo#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3870286441Srpaulo 3871286441Srpaulo#define IWM_BF_CMD_CONFIG_DEFAULTS \ 3872286441Srpaulo .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3873286441Srpaulo .bf_roaming_energy_delta = \ 3874286441Srpaulo htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3875286441Srpaulo .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3876286441Srpaulo .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3877286441Srpaulo .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3878286441Srpaulo .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3879286441Srpaulo .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3880286441Srpaulo .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3881286441Srpaulo .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3882286441Srpaulo 3883286441Srpaulo/* 3884286441Srpaulo * END mvm/fw-api-power.h 3885286441Srpaulo */ 3886286441Srpaulo 3887286441Srpaulo/* 3888286441Srpaulo * BEGIN mvm/fw-api-rs.h 3889286441Srpaulo */ 3890286441Srpaulo 3891286441Srpaulo/* 3892286441Srpaulo * These serve as indexes into 3893286441Srpaulo * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3894286441Srpaulo * TODO: avoid overlap between legacy and HT rates 3895286441Srpaulo */ 3896286441Srpauloenum { 3897286441Srpaulo IWM_RATE_1M_INDEX = 0, 3898286441Srpaulo IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3899286441Srpaulo IWM_RATE_2M_INDEX, 3900286441Srpaulo IWM_RATE_5M_INDEX, 3901286441Srpaulo IWM_RATE_11M_INDEX, 3902286441Srpaulo IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3903286441Srpaulo IWM_RATE_6M_INDEX, 3904286441Srpaulo IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3905286441Srpaulo IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3906286441Srpaulo IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3907286441Srpaulo IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3908286441Srpaulo IWM_RATE_9M_INDEX, 3909286441Srpaulo IWM_RATE_12M_INDEX, 3910286441Srpaulo IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3911286441Srpaulo IWM_RATE_18M_INDEX, 3912286441Srpaulo IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3913286441Srpaulo IWM_RATE_24M_INDEX, 3914286441Srpaulo IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3915286441Srpaulo IWM_RATE_36M_INDEX, 3916286441Srpaulo IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3917286441Srpaulo IWM_RATE_48M_INDEX, 3918286441Srpaulo IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3919286441Srpaulo IWM_RATE_54M_INDEX, 3920286441Srpaulo IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3921286441Srpaulo IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3922286441Srpaulo IWM_RATE_60M_INDEX, 3923286441Srpaulo IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3924286441Srpaulo IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3925286441Srpaulo IWM_RATE_MCS_8_INDEX, 3926286441Srpaulo IWM_RATE_MCS_9_INDEX, 3927286441Srpaulo IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3928286441Srpaulo IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3929286441Srpaulo IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3930286441Srpaulo}; 3931286441Srpaulo 3932286441Srpaulo#define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3933286441Srpaulo 3934286441Srpaulo/* fw API values for legacy bit rates, both OFDM and CCK */ 3935286441Srpauloenum { 3936286441Srpaulo IWM_RATE_6M_PLCP = 13, 3937286441Srpaulo IWM_RATE_9M_PLCP = 15, 3938286441Srpaulo IWM_RATE_12M_PLCP = 5, 3939286441Srpaulo IWM_RATE_18M_PLCP = 7, 3940286441Srpaulo IWM_RATE_24M_PLCP = 9, 3941286441Srpaulo IWM_RATE_36M_PLCP = 11, 3942286441Srpaulo IWM_RATE_48M_PLCP = 1, 3943286441Srpaulo IWM_RATE_54M_PLCP = 3, 3944286441Srpaulo IWM_RATE_1M_PLCP = 10, 3945286441Srpaulo IWM_RATE_2M_PLCP = 20, 3946286441Srpaulo IWM_RATE_5M_PLCP = 55, 3947286441Srpaulo IWM_RATE_11M_PLCP = 110, 3948286441Srpaulo IWM_RATE_INVM_PLCP = -1, 3949286441Srpaulo}; 3950286441Srpaulo 3951286441Srpaulo/* 3952286441Srpaulo * rate_n_flags bit fields 3953286441Srpaulo * 3954286441Srpaulo * The 32-bit value has different layouts in the low 8 bites depending on the 3955286441Srpaulo * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3956286441Srpaulo * for CCK and OFDM). 3957286441Srpaulo * 3958286441Srpaulo * High-throughput (HT) rate format 3959286441Srpaulo * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3960286441Srpaulo * Very High-throughput (VHT) rate format 3961286441Srpaulo * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3962286441Srpaulo * Legacy OFDM rate format for bits 7:0 3963286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3964286441Srpaulo * Legacy CCK rate format for bits 7:0: 3965286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3966286441Srpaulo */ 3967286441Srpaulo 3968286441Srpaulo/* Bit 8: (1) HT format, (0) legacy or VHT format */ 3969286441Srpaulo#define IWM_RATE_MCS_HT_POS 8 3970286441Srpaulo#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3971286441Srpaulo 3972286441Srpaulo/* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3973286441Srpaulo#define IWM_RATE_MCS_CCK_POS 9 3974286441Srpaulo#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3975286441Srpaulo 3976286441Srpaulo/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3977286441Srpaulo#define IWM_RATE_MCS_VHT_POS 26 3978286441Srpaulo#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3979286441Srpaulo 3980286441Srpaulo 3981286441Srpaulo/* 3982286441Srpaulo * High-throughput (HT) rate format for bits 7:0 3983286441Srpaulo * 3984286441Srpaulo * 2-0: MCS rate base 3985286441Srpaulo * 0) 6 Mbps 3986286441Srpaulo * 1) 12 Mbps 3987286441Srpaulo * 2) 18 Mbps 3988286441Srpaulo * 3) 24 Mbps 3989286441Srpaulo * 4) 36 Mbps 3990286441Srpaulo * 5) 48 Mbps 3991286441Srpaulo * 6) 54 Mbps 3992286441Srpaulo * 7) 60 Mbps 3993286441Srpaulo * 4-3: 0) Single stream (SISO) 3994286441Srpaulo * 1) Dual stream (MIMO) 3995286441Srpaulo * 2) Triple stream (MIMO) 3996286441Srpaulo * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3997286441Srpaulo * (bits 7-6 are zero) 3998286441Srpaulo * 3999286441Srpaulo * Together the low 5 bits work out to the MCS index because we don't 4000286441Srpaulo * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4001286441Srpaulo * streams and 16-23 have three streams. We could also support MCS 32 4002286441Srpaulo * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4003286441Srpaulo */ 4004286441Srpaulo#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 4005286441Srpaulo#define IWM_RATE_HT_MCS_NSS_POS 3 4006286441Srpaulo#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 4007286441Srpaulo 4008286441Srpaulo/* Bit 10: (1) Use Green Field preamble */ 4009286441Srpaulo#define IWM_RATE_HT_MCS_GF_POS 10 4010286441Srpaulo#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 4011286441Srpaulo 4012286441Srpaulo#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 4013286441Srpaulo 4014286441Srpaulo/* 4015286441Srpaulo * Very High-throughput (VHT) rate format for bits 7:0 4016286441Srpaulo * 4017286441Srpaulo * 3-0: VHT MCS (0-9) 4018286441Srpaulo * 5-4: number of streams - 1: 4019286441Srpaulo * 0) Single stream (SISO) 4020286441Srpaulo * 1) Dual stream (MIMO) 4021286441Srpaulo * 2) Triple stream (MIMO) 4022286441Srpaulo */ 4023286441Srpaulo 4024286441Srpaulo/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4025286441Srpaulo#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4026286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_POS 4 4027286441Srpaulo#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 4028286441Srpaulo 4029286441Srpaulo/* 4030286441Srpaulo * Legacy OFDM rate format for bits 7:0 4031286441Srpaulo * 4032286441Srpaulo * 3-0: 0xD) 6 Mbps 4033286441Srpaulo * 0xF) 9 Mbps 4034286441Srpaulo * 0x5) 12 Mbps 4035286441Srpaulo * 0x7) 18 Mbps 4036286441Srpaulo * 0x9) 24 Mbps 4037286441Srpaulo * 0xB) 36 Mbps 4038286441Srpaulo * 0x1) 48 Mbps 4039286441Srpaulo * 0x3) 54 Mbps 4040286441Srpaulo * (bits 7-4 are 0) 4041286441Srpaulo * 4042286441Srpaulo * Legacy CCK rate format for bits 7:0: 4043286441Srpaulo * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4044286441Srpaulo * 4045286441Srpaulo * 6-0: 10) 1 Mbps 4046286441Srpaulo * 20) 2 Mbps 4047286441Srpaulo * 55) 5.5 Mbps 4048286441Srpaulo * 110) 11 Mbps 4049286441Srpaulo * (bit 7 is 0) 4050286441Srpaulo */ 4051286441Srpaulo#define IWM_RATE_LEGACY_RATE_MSK 0xff 4052286441Srpaulo 4053286441Srpaulo 4054286441Srpaulo/* 4055286441Srpaulo * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4056286441Srpaulo * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4057286441Srpaulo */ 4058286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4059286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4060286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4061286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4062286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4063286441Srpaulo#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4064286441Srpaulo 4065286441Srpaulo/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4066286441Srpaulo#define IWM_RATE_MCS_SGI_POS 13 4067286441Srpaulo#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4068286441Srpaulo 4069286441Srpaulo/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4070286441Srpaulo#define IWM_RATE_MCS_ANT_POS 14 4071286441Srpaulo#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4072286441Srpaulo#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4073286441Srpaulo#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4074286441Srpaulo#define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4075286441Srpaulo IWM_RATE_MCS_ANT_B_MSK) 4076286441Srpaulo#define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4077286441Srpaulo IWM_RATE_MCS_ANT_C_MSK) 4078286441Srpaulo#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4079286441Srpaulo#define IWM_RATE_MCS_ANT_NUM 3 4080286441Srpaulo 4081286441Srpaulo/* Bit 17-18: (0) SS, (1) SS*2 */ 4082286441Srpaulo#define IWM_RATE_MCS_STBC_POS 17 4083286441Srpaulo#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4084286441Srpaulo 4085286441Srpaulo/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4086286441Srpaulo#define IWM_RATE_MCS_BF_POS 19 4087286441Srpaulo#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4088286441Srpaulo 4089286441Srpaulo/* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4090286441Srpaulo#define IWM_RATE_MCS_ZLF_POS 20 4091286441Srpaulo#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4092286441Srpaulo 4093286441Srpaulo/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4094286441Srpaulo#define IWM_RATE_MCS_DUP_POS 24 4095286441Srpaulo#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4096286441Srpaulo 4097286441Srpaulo/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4098286441Srpaulo#define IWM_RATE_MCS_LDPC_POS 27 4099286441Srpaulo#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4100286441Srpaulo 4101286441Srpaulo 4102286441Srpaulo/* Link Quality definitions */ 4103286441Srpaulo 4104286441Srpaulo/* # entries in rate scale table to support Tx retries */ 4105286441Srpaulo#define IWM_LQ_MAX_RETRY_NUM 16 4106286441Srpaulo 4107286441Srpaulo/* Link quality command flags bit fields */ 4108286441Srpaulo 4109286441Srpaulo/* Bit 0: (0) Don't use RTS (1) Use RTS */ 4110286441Srpaulo#define IWM_LQ_FLAG_USE_RTS_POS 0 4111286441Srpaulo#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4112286441Srpaulo 4113286441Srpaulo/* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4114286441Srpaulo#define IWM_LQ_FLAG_COLOR_POS 1 4115286441Srpaulo#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4116286441Srpaulo 4117286441Srpaulo/* Bit 4-5: Tx RTS BW Signalling 4118286441Srpaulo * (0) No RTS BW signalling 4119286441Srpaulo * (1) Static BW signalling 4120286441Srpaulo * (2) Dynamic BW signalling 4121286441Srpaulo */ 4122286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4123286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4124286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4125286441Srpaulo#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4126286441Srpaulo 4127286441Srpaulo/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4128286441Srpaulo * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4129286441Srpaulo */ 4130286441Srpaulo#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4131286441Srpaulo#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4132286441Srpaulo 4133286441Srpaulo/** 4134286441Srpaulo * struct iwm_lq_cmd - link quality command 4135286441Srpaulo * @sta_id: station to update 4136286441Srpaulo * @control: not used 4137286441Srpaulo * @flags: combination of IWM_LQ_FLAG_* 4138286441Srpaulo * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4139286441Srpaulo * and SISO rates 4140286441Srpaulo * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4141286441Srpaulo * Should be ANT_[ABC] 4142286441Srpaulo * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4143286441Srpaulo * @initial_rate_index: first index from rs_table per AC category 4144286441Srpaulo * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4145286441Srpaulo * value of 100 is one usec. Range is 100 to 8000 4146286441Srpaulo * @agg_disable_start_th: try-count threshold for starting aggregation. 4147286441Srpaulo * If a frame has higher try-count, it should not be selected for 4148286441Srpaulo * starting an aggregation sequence. 4149286441Srpaulo * @agg_frame_cnt_limit: max frame count in an aggregation. 4150286441Srpaulo * 0: no limit 4151286441Srpaulo * 1: no aggregation (one frame per aggregation) 4152286441Srpaulo * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4153286441Srpaulo * @rs_table: array of rates for each TX try, each is rate_n_flags, 4154286441Srpaulo * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4155286441Srpaulo * @bf_params: beam forming params, currently not used 4156286441Srpaulo */ 4157286441Srpaulostruct iwm_lq_cmd { 4158286441Srpaulo uint8_t sta_id; 4159286441Srpaulo uint8_t reserved1; 4160286441Srpaulo uint16_t control; 4161286441Srpaulo /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4162286441Srpaulo uint8_t flags; 4163286441Srpaulo uint8_t mimo_delim; 4164286441Srpaulo uint8_t single_stream_ant_msk; 4165286441Srpaulo uint8_t dual_stream_ant_msk; 4166286441Srpaulo uint8_t initial_rate_index[IWM_AC_NUM]; 4167286441Srpaulo /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4168286441Srpaulo uint16_t agg_time_limit; 4169286441Srpaulo uint8_t agg_disable_start_th; 4170286441Srpaulo uint8_t agg_frame_cnt_limit; 4171286441Srpaulo uint32_t reserved2; 4172286441Srpaulo uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4173286441Srpaulo uint32_t bf_params; 4174286441Srpaulo}; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4175286441Srpaulo 4176286441Srpaulo/* 4177286441Srpaulo * END mvm/fw-api-rs.h 4178286441Srpaulo */ 4179286441Srpaulo 4180286441Srpaulo/* 4181286441Srpaulo * BEGIN mvm/fw-api-tx.h 4182286441Srpaulo */ 4183286441Srpaulo 4184286441Srpaulo/** 4185286441Srpaulo * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4186286441Srpaulo * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4187286441Srpaulo * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4188286441Srpaulo * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4189286441Srpaulo * Otherwise, use rate_n_flags from the TX command 4190286441Srpaulo * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4191286441Srpaulo * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4192286441Srpaulo * Must set IWM_TX_CMD_FLG_ACK with this flag. 4193286441Srpaulo * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4194286441Srpaulo * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4195286441Srpaulo * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4196286441Srpaulo * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4197286441Srpaulo * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4198286441Srpaulo * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4199286441Srpaulo * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4200286441Srpaulo * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4201286441Srpaulo * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4202286441Srpaulo * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4203286441Srpaulo * Should be set for beacons and probe responses 4204286441Srpaulo * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4205286441Srpaulo * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4206286441Srpaulo * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4207286441Srpaulo * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4208286441Srpaulo * Should be set for 26/30 length MAC headers 4209286441Srpaulo * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4210286441Srpaulo * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4211286441Srpaulo * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4212286441Srpaulo * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4213286441Srpaulo * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4214286441Srpaulo * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4215286441Srpaulo * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4216286441Srpaulo * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4217286441Srpaulo */ 4218286441Srpauloenum iwm_tx_flags { 4219286441Srpaulo IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4220286441Srpaulo IWM_TX_CMD_FLG_ACK = (1 << 3), 4221286441Srpaulo IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4222286441Srpaulo IWM_TX_CMD_FLG_BA = (1 << 5), 4223286441Srpaulo IWM_TX_CMD_FLG_BAR = (1 << 6), 4224286441Srpaulo IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4225286441Srpaulo IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4226286441Srpaulo IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4227286441Srpaulo IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4228286441Srpaulo IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4229286441Srpaulo IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4230286441Srpaulo IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4231286441Srpaulo IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4232286441Srpaulo IWM_TX_CMD_FLG_TSF = (1 << 16), 4233286441Srpaulo IWM_TX_CMD_FLG_CALIB = (1 << 17), 4234286441Srpaulo IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4235286441Srpaulo IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4236286441Srpaulo IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4237286441Srpaulo IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4238286441Srpaulo IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4239286441Srpaulo IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4240286441Srpaulo IWM_TX_CMD_FLG_DUR = (1 << 25), 4241286441Srpaulo IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4242286441Srpaulo IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4243286441Srpaulo IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4244286441Srpaulo IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4245286441Srpaulo}; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4246286441Srpaulo 4247303628Ssbruno/** 4248303628Ssbruno * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4249303628Ssbruno * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4250303628Ssbruno * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4251303628Ssbruno * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4252303628Ssbruno */ 4253303628Ssbrunoenum iwm_tx_pm_timeouts { 4254303628Ssbruno IWM_PM_FRAME_NONE = 0, 4255303628Ssbruno IWM_PM_FRAME_MGMT = 2, 4256303628Ssbruno IWM_PM_FRAME_ASSOC = 3, 4257303628Ssbruno}; 4258303628Ssbruno 4259286441Srpaulo/* 4260286441Srpaulo * TX command security control 4261286441Srpaulo */ 4262286441Srpaulo#define IWM_TX_CMD_SEC_WEP 0x01 4263286441Srpaulo#define IWM_TX_CMD_SEC_CCM 0x02 4264286441Srpaulo#define IWM_TX_CMD_SEC_TKIP 0x03 4265286441Srpaulo#define IWM_TX_CMD_SEC_EXT 0x04 4266286441Srpaulo#define IWM_TX_CMD_SEC_MSK 0x07 4267286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4268286441Srpaulo#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4269286441Srpaulo#define IWM_TX_CMD_SEC_KEY128 0x08 4270286441Srpaulo 4271286441Srpaulo/* TODO: how does these values are OK with only 16 bit variable??? */ 4272286441Srpaulo/* 4273286441Srpaulo * TX command next frame info 4274286441Srpaulo * 4275286441Srpaulo * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4276286441Srpaulo * bit 3 - immediate ACK required 4277286441Srpaulo * bit 4 - rate is taken from STA table 4278286441Srpaulo * bit 5 - frame belongs to BA stream 4279286441Srpaulo * bit 6 - immediate BA response expected 4280286441Srpaulo * bit 7 - unused 4281286441Srpaulo * bits 8:15 - Station ID 4282286441Srpaulo * bits 16:31 - rate 4283286441Srpaulo */ 4284286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4285286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4286286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4287286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4288286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4289286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4290286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4291286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4292286441Srpaulo#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4293286441Srpaulo 4294286441Srpaulo/* 4295286441Srpaulo * TX command Frame life time in us - to be written in pm_frame_timeout 4296286441Srpaulo */ 4297286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4298286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4299286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4300286441Srpaulo#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4301286441Srpaulo 4302286441Srpaulo/* 4303286441Srpaulo * TID for non QoS frames - to be written in tid_tspec 4304286441Srpaulo */ 4305286441Srpaulo#define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4306286441Srpaulo 4307286441Srpaulo/* 4308286441Srpaulo * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4309286441Srpaulo */ 4310286441Srpaulo#define IWM_DEFAULT_TX_RETRY 15 4311286441Srpaulo#define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4312286441Srpaulo#define IWM_RTS_DFAULT_RETRY_LIMIT 60 4313286441Srpaulo#define IWM_BAR_DFAULT_RETRY_LIMIT 60 4314286441Srpaulo#define IWM_LOW_RETRY_LIMIT 7 4315286441Srpaulo 4316286441Srpaulo/* TODO: complete documentation for try_cnt and btkill_cnt */ 4317286441Srpaulo/** 4318286441Srpaulo * struct iwm_tx_cmd - TX command struct to FW 4319286441Srpaulo * ( IWM_TX_CMD = 0x1c ) 4320286441Srpaulo * @len: in bytes of the payload, see below for details 4321286441Srpaulo * @next_frame_len: same as len, but for next frame (0 if not applicable) 4322286441Srpaulo * Used for fragmentation and bursting, but not in 11n aggregation. 4323286441Srpaulo * @tx_flags: combination of IWM_TX_CMD_FLG_* 4324286441Srpaulo * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4325286441Srpaulo * cleared. Combination of IWM_RATE_MCS_* 4326286441Srpaulo * @sta_id: index of destination station in FW station table 4327286441Srpaulo * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4328300050Seadler * @initial_rate_index: index into the rate table for initial TX attempt. 4329286441Srpaulo * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4330286441Srpaulo * @key: security key 4331286441Srpaulo * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4332286441Srpaulo * @life_time: frame life time (usecs??) 4333286441Srpaulo * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4334286441Srpaulo * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4335286441Srpaulo * @dram_msb_ptr: upper bits of the scratch physical address 4336286441Srpaulo * @rts_retry_limit: max attempts for RTS 4337286441Srpaulo * @data_retry_limit: max attempts to send the data packet 4338286441Srpaulo * @tid_spec: TID/tspec 4339286441Srpaulo * @pm_frame_timeout: PM TX frame timeout 4340286441Srpaulo * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4341286441Srpaulo * specified by HCCA protocol 4342286441Srpaulo * 4343286441Srpaulo * The byte count (both len and next_frame_len) includes MAC header 4344286441Srpaulo * (24/26/30/32 bytes) 4345286441Srpaulo * + 2 bytes pad if 26/30 header size 4346286441Srpaulo * + 8 byte IV for CCM or TKIP (not used for WEP) 4347286441Srpaulo * + Data payload 4348286441Srpaulo * + 8-byte MIC (not used for CCM/WEP) 4349286441Srpaulo * It does not include post-MAC padding, i.e., 4350286441Srpaulo * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4351286441Srpaulo * Range of len: 14-2342 bytes. 4352286441Srpaulo * 4353286441Srpaulo * After the struct fields the MAC header is placed, plus any padding, 4354286441Srpaulo * and then the actial payload. 4355286441Srpaulo */ 4356286441Srpaulostruct iwm_tx_cmd { 4357286441Srpaulo uint16_t len; 4358286441Srpaulo uint16_t next_frame_len; 4359286441Srpaulo uint32_t tx_flags; 4360286441Srpaulo struct { 4361286441Srpaulo uint8_t try_cnt; 4362286441Srpaulo uint8_t btkill_cnt; 4363286441Srpaulo uint16_t reserved; 4364286441Srpaulo } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4365286441Srpaulo uint32_t rate_n_flags; 4366286441Srpaulo uint8_t sta_id; 4367286441Srpaulo uint8_t sec_ctl; 4368286441Srpaulo uint8_t initial_rate_index; 4369286441Srpaulo uint8_t reserved2; 4370286441Srpaulo uint8_t key[16]; 4371286441Srpaulo uint16_t next_frame_flags; 4372286441Srpaulo uint16_t reserved3; 4373286441Srpaulo uint32_t life_time; 4374286441Srpaulo uint32_t dram_lsb_ptr; 4375286441Srpaulo uint8_t dram_msb_ptr; 4376286441Srpaulo uint8_t rts_retry_limit; 4377286441Srpaulo uint8_t data_retry_limit; 4378286441Srpaulo uint8_t tid_tspec; 4379286441Srpaulo uint16_t pm_frame_timeout; 4380286441Srpaulo uint16_t driver_txop; 4381286441Srpaulo uint8_t payload[0]; 4382286441Srpaulo struct ieee80211_frame hdr[0]; 4383286441Srpaulo} __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4384286441Srpaulo 4385286441Srpaulo/* 4386286441Srpaulo * TX response related data 4387286441Srpaulo */ 4388286441Srpaulo 4389286441Srpaulo/* 4390286441Srpaulo * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4391286441Srpaulo * @IWM_TX_STATUS_SUCCESS: 4392286441Srpaulo * @IWM_TX_STATUS_DIRECT_DONE: 4393286441Srpaulo * @IWM_TX_STATUS_POSTPONE_DELAY: 4394286441Srpaulo * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4395286441Srpaulo * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4396286441Srpaulo * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4397286441Srpaulo * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4398286441Srpaulo * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4399286441Srpaulo * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4400286441Srpaulo * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4401286441Srpaulo * @IWM_TX_STATUS_FAIL_UNDERRUN: 4402286441Srpaulo * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4403286441Srpaulo * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4404286441Srpaulo * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4405286441Srpaulo * @IWM_TX_STATUS_FAIL_DEST_PS: 4406286441Srpaulo * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4407286441Srpaulo * @IWM_TX_STATUS_FAIL_BT_RETRY: 4408286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_INVALID: 4409286441Srpaulo * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4410286441Srpaulo * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4411286441Srpaulo * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4412286441Srpaulo * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4413286441Srpaulo * @IWM_TX_STATUS_FAIL_FW_DROP: 4414286441Srpaulo * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4415286441Srpaulo * STA table 4416286441Srpaulo * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4417286441Srpaulo * @IWM_TX_MODE_MSK: 4418286441Srpaulo * @IWM_TX_MODE_NO_BURST: 4419286441Srpaulo * @IWM_TX_MODE_IN_BURST_SEQ: 4420286441Srpaulo * @IWM_TX_MODE_FIRST_IN_BURST: 4421286441Srpaulo * @IWM_TX_QUEUE_NUM_MSK: 4422286441Srpaulo * 4423286441Srpaulo * Valid only if frame_count =1 4424286441Srpaulo * TODO: complete documentation 4425286441Srpaulo */ 4426286441Srpauloenum iwm_tx_status { 4427286441Srpaulo IWM_TX_STATUS_MSK = 0x000000ff, 4428286441Srpaulo IWM_TX_STATUS_SUCCESS = 0x01, 4429286441Srpaulo IWM_TX_STATUS_DIRECT_DONE = 0x02, 4430286441Srpaulo /* postpone TX */ 4431286441Srpaulo IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4432286441Srpaulo IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4433286441Srpaulo IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4434286441Srpaulo IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4435286441Srpaulo IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4436286441Srpaulo /* abort TX */ 4437286441Srpaulo IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4438286441Srpaulo IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4439286441Srpaulo IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4440286441Srpaulo IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4441286441Srpaulo IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4442286441Srpaulo IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4443286441Srpaulo IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4444286441Srpaulo IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4445286441Srpaulo IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4446286441Srpaulo IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4447286441Srpaulo IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4448286441Srpaulo IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4449286441Srpaulo IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4450286441Srpaulo IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4451286441Srpaulo IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4452286441Srpaulo IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4453286441Srpaulo IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4454286441Srpaulo IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4455286441Srpaulo IWM_TX_MODE_MSK = 0x00000f00, 4456286441Srpaulo IWM_TX_MODE_NO_BURST = 0x00000000, 4457286441Srpaulo IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4458286441Srpaulo IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4459286441Srpaulo IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4460286441Srpaulo IWM_TX_NARROW_BW_MSK = 0x00060000, 4461286441Srpaulo IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4462286441Srpaulo IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4463286441Srpaulo IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4464286441Srpaulo}; 4465286441Srpaulo 4466286441Srpaulo/* 4467286441Srpaulo * enum iwm_tx_agg_status - TX aggregation status 4468286441Srpaulo * @IWM_AGG_TX_STATE_STATUS_MSK: 4469286441Srpaulo * @IWM_AGG_TX_STATE_TRANSMITTED: 4470286441Srpaulo * @IWM_AGG_TX_STATE_UNDERRUN: 4471286441Srpaulo * @IWM_AGG_TX_STATE_BT_PRIO: 4472286441Srpaulo * @IWM_AGG_TX_STATE_FEW_BYTES: 4473286441Srpaulo * @IWM_AGG_TX_STATE_ABORT: 4474286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4475286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4476286441Srpaulo * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4477286441Srpaulo * @IWM_AGG_TX_STATE_SCD_QUERY: 4478286441Srpaulo * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4479286441Srpaulo * @IWM_AGG_TX_STATE_RESPONSE: 4480286441Srpaulo * @IWM_AGG_TX_STATE_DUMP_TX: 4481286441Srpaulo * @IWM_AGG_TX_STATE_DELAY_TX: 4482286441Srpaulo * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4483286441Srpaulo * occur if tx failed for this frame when it was a member of a previous 4484286441Srpaulo * aggregation block). If rate scaling is used, retry count indicates the 4485286441Srpaulo * rate table entry used for all frames in the new agg. 4486286441Srpaulo *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4487286441Srpaulo * this frame 4488286441Srpaulo * 4489286441Srpaulo * TODO: complete documentation 4490286441Srpaulo */ 4491286441Srpauloenum iwm_tx_agg_status { 4492286441Srpaulo IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4493286441Srpaulo IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4494286441Srpaulo IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4495286441Srpaulo IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4496286441Srpaulo IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4497286441Srpaulo IWM_AGG_TX_STATE_ABORT = 0x008, 4498286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4499286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4500286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4501286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4502286441Srpaulo IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4503286441Srpaulo IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4504286441Srpaulo IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4505286441Srpaulo IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4506286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4507286441Srpaulo IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4508286441Srpaulo}; 4509286441Srpaulo 4510286441Srpaulo#define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4511286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4512286441Srpaulo IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4513286441Srpaulo 4514286441Srpaulo/* 4515286441Srpaulo * The mask below describes a status where we are absolutely sure that the MPDU 4516286441Srpaulo * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4517286441Srpaulo * written the bytes to the TXE, but we know nothing about what the DSP did. 4518286441Srpaulo */ 4519286441Srpaulo#define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4520286441Srpaulo IWM_AGG_TX_STATE_ABORT | \ 4521286441Srpaulo IWM_AGG_TX_STATE_SCD_QUERY) 4522286441Srpaulo 4523286441Srpaulo/* 4524286441Srpaulo * IWM_REPLY_TX = 0x1c (response) 4525286441Srpaulo * 4526286441Srpaulo * This response may be in one of two slightly different formats, indicated 4527286441Srpaulo * by the frame_count field: 4528286441Srpaulo * 4529286441Srpaulo * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4530286441Srpaulo * frame. Multiple attempts, at various bit rates, may have been made for 4531286441Srpaulo * this frame. 4532286441Srpaulo * 4533286441Srpaulo * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4534286441Srpaulo * frames that used block-acknowledge. All frames were transmitted at 4535286441Srpaulo * same rate. Rate scaling may have been used if first frame in this new 4536286441Srpaulo * agg block failed in previous agg block(s). 4537286441Srpaulo * 4538286441Srpaulo * Note that, for aggregation, ACK (block-ack) status is not delivered 4539286441Srpaulo * here; block-ack has not been received by the time the device records 4540286441Srpaulo * this status. 4541286441Srpaulo * This status relates to reasons the tx might have been blocked or aborted 4542286441Srpaulo * within the device, rather than whether it was received successfully by 4543286441Srpaulo * the destination station. 4544286441Srpaulo */ 4545286441Srpaulo 4546286441Srpaulo/** 4547286441Srpaulo * struct iwm_agg_tx_status - per packet TX aggregation status 4548286441Srpaulo * @status: enum iwm_tx_agg_status 4549286441Srpaulo * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4550286441Srpaulo */ 4551286441Srpaulostruct iwm_agg_tx_status { 4552286441Srpaulo uint16_t status; 4553286441Srpaulo uint16_t sequence; 4554286441Srpaulo} __packed; 4555286441Srpaulo 4556286441Srpaulo/* 4557286441Srpaulo * definitions for initial rate index field 4558286441Srpaulo * bits [3:0] initial rate index 4559286441Srpaulo * bits [6:4] rate table color, used for the initial rate 4560286441Srpaulo * bit-7 invalid rate indication 4561286441Srpaulo */ 4562286441Srpaulo#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4563286441Srpaulo#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4564286441Srpaulo#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4565286441Srpaulo 4566286441Srpaulo#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4567286441Srpaulo#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4568286441Srpaulo 4569286441Srpaulo/** 4570286441Srpaulo * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4571286441Srpaulo * ( IWM_REPLY_TX = 0x1c ) 4572286441Srpaulo * @frame_count: 1 no aggregation, >1 aggregation 4573286441Srpaulo * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4574286441Srpaulo * @failure_rts: num of failures due to unsuccessful RTS 4575286441Srpaulo * @failure_frame: num failures due to no ACK (unused for agg) 4576286441Srpaulo * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4577286441Srpaulo * Tx of all the batch. IWM_RATE_MCS_* 4578286441Srpaulo * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4579286441Srpaulo * for agg: RTS + CTS + aggregation tx time + block-ack time. 4580286441Srpaulo * in usec. 4581286441Srpaulo * @pa_status: tx power info 4582286441Srpaulo * @pa_integ_res_a: tx power info 4583286441Srpaulo * @pa_integ_res_b: tx power info 4584286441Srpaulo * @pa_integ_res_c: tx power info 4585286441Srpaulo * @measurement_req_id: tx power info 4586286441Srpaulo * @tfd_info: TFD information set by the FH 4587286441Srpaulo * @seq_ctl: sequence control from the Tx cmd 4588286441Srpaulo * @byte_cnt: byte count from the Tx cmd 4589286441Srpaulo * @tlc_info: TLC rate info 4590286441Srpaulo * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4591286441Srpaulo * @frame_ctrl: frame control 4592286441Srpaulo * @status: for non-agg: frame status IWM_TX_STATUS_* 4593286441Srpaulo * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4594286441Srpaulo * follow this one, up to frame_count. 4595286441Srpaulo * 4596286441Srpaulo * After the array of statuses comes the SSN of the SCD. Look at 4597286441Srpaulo * %iwm_mvm_get_scd_ssn for more details. 4598286441Srpaulo */ 4599286441Srpaulostruct iwm_mvm_tx_resp { 4600286441Srpaulo uint8_t frame_count; 4601286441Srpaulo uint8_t bt_kill_count; 4602286441Srpaulo uint8_t failure_rts; 4603286441Srpaulo uint8_t failure_frame; 4604286441Srpaulo uint32_t initial_rate; 4605286441Srpaulo uint16_t wireless_media_time; 4606286441Srpaulo 4607286441Srpaulo uint8_t pa_status; 4608286441Srpaulo uint8_t pa_integ_res_a[3]; 4609286441Srpaulo uint8_t pa_integ_res_b[3]; 4610286441Srpaulo uint8_t pa_integ_res_c[3]; 4611286441Srpaulo uint16_t measurement_req_id; 4612286441Srpaulo uint16_t reserved; 4613286441Srpaulo 4614286441Srpaulo uint32_t tfd_info; 4615286441Srpaulo uint16_t seq_ctl; 4616286441Srpaulo uint16_t byte_cnt; 4617286441Srpaulo uint8_t tlc_info; 4618286441Srpaulo uint8_t ra_tid; 4619286441Srpaulo uint16_t frame_ctrl; 4620286441Srpaulo 4621286441Srpaulo struct iwm_agg_tx_status status; 4622286441Srpaulo} __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4623286441Srpaulo 4624286441Srpaulo/** 4625286441Srpaulo * struct iwm_mvm_ba_notif - notifies about reception of BA 4626286441Srpaulo * ( IWM_BA_NOTIF = 0xc5 ) 4627286441Srpaulo * @sta_addr_lo32: lower 32 bits of the MAC address 4628286441Srpaulo * @sta_addr_hi16: upper 16 bits of the MAC address 4629286441Srpaulo * @sta_id: Index of recipient (BA-sending) station in fw's station table 4630286441Srpaulo * @tid: tid of the session 4631286441Srpaulo * @seq_ctl: 4632286441Srpaulo * @bitmap: the bitmap of the BA notification as seen in the air 4633286441Srpaulo * @scd_flow: the tx queue this BA relates to 4634286441Srpaulo * @scd_ssn: the index of the last contiguously sent packet 4635286441Srpaulo * @txed: number of Txed frames in this batch 4636286441Srpaulo * @txed_2_done: number of Acked frames in this batch 4637286441Srpaulo */ 4638286441Srpaulostruct iwm_mvm_ba_notif { 4639286441Srpaulo uint32_t sta_addr_lo32; 4640286441Srpaulo uint16_t sta_addr_hi16; 4641286441Srpaulo uint16_t reserved; 4642286441Srpaulo 4643286441Srpaulo uint8_t sta_id; 4644286441Srpaulo uint8_t tid; 4645286441Srpaulo uint16_t seq_ctl; 4646286441Srpaulo uint64_t bitmap; 4647286441Srpaulo uint16_t scd_flow; 4648286441Srpaulo uint16_t scd_ssn; 4649286441Srpaulo uint8_t txed; 4650286441Srpaulo uint8_t txed_2_done; 4651286441Srpaulo uint16_t reserved1; 4652286441Srpaulo} __packed; 4653286441Srpaulo 4654286441Srpaulo/* 4655286441Srpaulo * struct iwm_mac_beacon_cmd - beacon template command 4656286441Srpaulo * @tx: the tx commands associated with the beacon frame 4657286441Srpaulo * @template_id: currently equal to the mac context id of the coresponding 4658286441Srpaulo * mac. 4659286441Srpaulo * @tim_idx: the offset of the tim IE in the beacon 4660286441Srpaulo * @tim_size: the length of the tim IE 4661286441Srpaulo * @frame: the template of the beacon frame 4662286441Srpaulo */ 4663286441Srpaulostruct iwm_mac_beacon_cmd { 4664286441Srpaulo struct iwm_tx_cmd tx; 4665286441Srpaulo uint32_t template_id; 4666286441Srpaulo uint32_t tim_idx; 4667286441Srpaulo uint32_t tim_size; 4668286441Srpaulo struct ieee80211_frame frame[0]; 4669286441Srpaulo} __packed; 4670286441Srpaulo 4671286441Srpaulostruct iwm_beacon_notif { 4672286441Srpaulo struct iwm_mvm_tx_resp beacon_notify_hdr; 4673286441Srpaulo uint64_t tsf; 4674286441Srpaulo uint32_t ibss_mgr_status; 4675286441Srpaulo} __packed; 4676286441Srpaulo 4677286441Srpaulo/** 4678286441Srpaulo * enum iwm_dump_control - dump (flush) control flags 4679300050Seadler * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4680286441Srpaulo * and the TFD queues are empty. 4681286441Srpaulo */ 4682286441Srpauloenum iwm_dump_control { 4683286441Srpaulo IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4684286441Srpaulo}; 4685286441Srpaulo 4686286441Srpaulo/** 4687286441Srpaulo * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4688286441Srpaulo * @queues_ctl: bitmap of queues to flush 4689286441Srpaulo * @flush_ctl: control flags 4690286441Srpaulo * @reserved: reserved 4691286441Srpaulo */ 4692286441Srpaulostruct iwm_tx_path_flush_cmd { 4693286441Srpaulo uint32_t queues_ctl; 4694286441Srpaulo uint16_t flush_ctl; 4695286441Srpaulo uint16_t reserved; 4696286441Srpaulo} __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4697286441Srpaulo 4698286441Srpaulo/** 4699286441Srpaulo * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4700286441Srpaulo * @tx_resp: the Tx response from the fw (agg or non-agg) 4701286441Srpaulo * 4702286441Srpaulo * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4703286441Srpaulo * it can't know that everything will go well until the end of the AMPDU, it 4704286441Srpaulo * can't know in advance the number of MPDUs that will be sent in the current 4705286441Srpaulo * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4706286441Srpaulo * Hence, it can't know in advance what the SSN of the SCD will be at the end 4707286441Srpaulo * of the batch. This is why the SSN of the SCD is written at the end of the 4708286441Srpaulo * whole struct at a variable offset. This function knows how to cope with the 4709286441Srpaulo * variable offset and returns the SSN of the SCD. 4710286441Srpaulo */ 4711286441Srpaulostatic inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4712286441Srpaulo{ 4713286441Srpaulo return le32_to_cpup((uint32_t *)&tx_resp->status + 4714286441Srpaulo tx_resp->frame_count) & 0xfff; 4715286441Srpaulo} 4716286441Srpaulo 4717286441Srpaulo/* 4718286441Srpaulo * END mvm/fw-api-tx.h 4719286441Srpaulo */ 4720286441Srpaulo 4721286441Srpaulo/* 4722286441Srpaulo * BEGIN mvm/fw-api-scan.h 4723286441Srpaulo */ 4724286441Srpaulo 4725303628Ssbruno/** 4726303628Ssbruno * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4727303628Ssbruno * @token: 4728303628Ssbruno * @sta_id: station id 4729303628Ssbruno * @tid: 4730303628Ssbruno * @scd_queue: scheduler queue to confiug 4731303628Ssbruno * @enable: 1 queue enable, 0 queue disable 4732303628Ssbruno * @aggregate: 1 aggregated queue, 0 otherwise 4733303628Ssbruno * @tx_fifo: %enum iwm_mvm_tx_fifo 4734303628Ssbruno * @window: BA window size 4735303628Ssbruno * @ssn: SSN for the BA agreement 4736303628Ssbruno */ 4737303628Ssbrunostruct iwm_scd_txq_cfg_cmd { 4738303628Ssbruno uint8_t token; 4739303628Ssbruno uint8_t sta_id; 4740303628Ssbruno uint8_t tid; 4741303628Ssbruno uint8_t scd_queue; 4742303628Ssbruno uint8_t enable; 4743303628Ssbruno uint8_t aggregate; 4744303628Ssbruno uint8_t tx_fifo; 4745303628Ssbruno uint8_t window; 4746303628Ssbruno uint16_t ssn; 4747303628Ssbruno uint16_t reserved; 4748303628Ssbruno} __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4749303628Ssbruno 4750303628Ssbruno/** 4751303628Ssbruno * struct iwm_scd_txq_cfg_rsp 4752303628Ssbruno * @token: taken from the command 4753303628Ssbruno * @sta_id: station id from the command 4754303628Ssbruno * @tid: tid from the command 4755303628Ssbruno * @scd_queue: scd_queue from the command 4756303628Ssbruno */ 4757303628Ssbrunostruct iwm_scd_txq_cfg_rsp { 4758303628Ssbruno uint8_t token; 4759303628Ssbruno uint8_t sta_id; 4760303628Ssbruno uint8_t tid; 4761303628Ssbruno uint8_t scd_queue; 4762303628Ssbruno} __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4763303628Ssbruno 4764303628Ssbruno 4765286441Srpaulo/* Scan Commands, Responses, Notifications */ 4766286441Srpaulo 4767286441Srpaulo/* Masks for iwm_scan_channel.type flags */ 4768286441Srpaulo#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0) 4769286441Srpaulo#define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22) 4770286441Srpaulo 4771286441Srpaulo/* Max number of IEs for direct SSID scans in a command */ 4772286441Srpaulo#define IWM_PROBE_OPTION_MAX 20 4773286441Srpaulo 4774286441Srpaulo/** 4775286441Srpaulo * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table 4776286441Srpaulo * @channel: band is selected by iwm_scan_cmd "flags" field 4777286441Srpaulo * @tx_gain: gain for analog radio 4778286441Srpaulo * @dsp_atten: gain for DSP 4779286441Srpaulo * @active_dwell: dwell time for active scan in TU, typically 5-50 4780286441Srpaulo * @passive_dwell: dwell time for passive scan in TU, typically 20-500 4781286441Srpaulo * @type: type is broken down to these bits: 4782286441Srpaulo * bit 0: 0 = passive, 1 = active 4783286441Srpaulo * bits 1-20: SSID direct bit map. If any of these bits is set then 4784286441Srpaulo * the corresponding SSID IE is transmitted in probe request 4785286441Srpaulo * (bit i adds IE in position i to the probe request) 4786286441Srpaulo * bit 22: channel width, 0 = regular, 1 = TGj narrow channel 4787286441Srpaulo * 4788286441Srpaulo * @iteration_count: 4789286441Srpaulo * @iteration_interval: 4790286441Srpaulo * This struct is used once for each channel in the scan list. 4791286441Srpaulo * Each channel can independently select: 4792286441Srpaulo * 1) SSID for directed active scans 4793286441Srpaulo * 2) Txpower setting (for rate specified within Tx command) 4794286441Srpaulo * 3) How long to stay on-channel (behavior may be modified by quiet_time, 4795286441Srpaulo * quiet_plcp_th, good_CRC_th) 4796286441Srpaulo * 4797286441Srpaulo * To avoid uCode errors, make sure the following are true (see comments 4798286441Srpaulo * under struct iwm_scan_cmd about max_out_time and quiet_time): 4799286441Srpaulo * 1) If using passive_dwell (i.e. passive_dwell != 0): 4800286441Srpaulo * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0) 4801286441Srpaulo * 2) quiet_time <= active_dwell 4802286441Srpaulo * 3) If restricting off-channel time (i.e. max_out_time !=0): 4803286441Srpaulo * passive_dwell < max_out_time 4804286441Srpaulo * active_dwell < max_out_time 4805286441Srpaulo */ 4806286441Srpaulostruct iwm_scan_channel { 4807286441Srpaulo uint32_t type; 4808286441Srpaulo uint16_t channel; 4809286441Srpaulo uint16_t iteration_count; 4810286441Srpaulo uint32_t iteration_interval; 4811286441Srpaulo uint16_t active_dwell; 4812286441Srpaulo uint16_t passive_dwell; 4813286441Srpaulo} __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */ 4814286441Srpaulo 4815286441Srpaulo/** 4816286441Srpaulo * struct iwm_ssid_ie - directed scan network information element 4817286441Srpaulo * 4818286441Srpaulo * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4819286441Srpaulo * selected by "type" bit field in struct iwm_scan_channel; 4820286441Srpaulo * each channel may select different ssids from among the 20 entries. 4821286441Srpaulo * SSID IEs get transmitted in reverse order of entry. 4822286441Srpaulo */ 4823286441Srpaulostruct iwm_ssid_ie { 4824286441Srpaulo uint8_t id; 4825286441Srpaulo uint8_t len; 4826286441Srpaulo uint8_t ssid[IEEE80211_NWID_LEN]; 4827286441Srpaulo} __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4828286441Srpaulo 4829303628Ssbruno/* scan offload */ 4830303628Ssbruno#define IWM_MAX_SCAN_CHANNELS 40 4831303628Ssbruno#define IWM_SCAN_MAX_BLACKLIST_LEN 64 4832303628Ssbruno#define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4833303628Ssbruno#define IWM_SCAN_MAX_PROFILES 11 4834303628Ssbruno#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4835303628Ssbruno 4836303628Ssbruno/* Default watchdog (in MS) for scheduled scan iteration */ 4837303628Ssbruno#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4838303628Ssbruno 4839303628Ssbruno#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4840303628Ssbruno#define IWM_CAN_ABORT_STATUS 1 4841303628Ssbruno 4842303628Ssbruno#define IWM_FULL_SCAN_MULTIPLIER 5 4843303628Ssbruno#define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4844303628Ssbruno#define IWM_MAX_SCHED_SCAN_PLANS 2 4845303628Ssbruno 4846286441Srpaulo/** 4847286441Srpaulo * iwm_scan_flags - masks for scan command flags 4848286441Srpaulo *@IWM_SCAN_FLAGS_PERIODIC_SCAN: 4849286441Srpaulo *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX: 4850286441Srpaulo *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND: 4851286441Srpaulo *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND: 4852286441Srpaulo *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN: 4853286441Srpaulo *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active 4854286441Srpaulo * in the past hour, even if they are marked as passive. 4855286441Srpaulo */ 4856286441Srpauloenum iwm_scan_flags { 4857286441Srpaulo IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0), 4858286441Srpaulo IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1), 4859286441Srpaulo IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2), 4860286441Srpaulo IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3), 4861286441Srpaulo IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4), 4862286441Srpaulo IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5), 4863286441Srpaulo}; 4864286441Srpaulo 4865286441Srpaulo/** 4866286441Srpaulo * enum iwm_scan_type - Scan types for scan command 4867286441Srpaulo * @IWM_SCAN_TYPE_FORCED: 4868286441Srpaulo * @IWM_SCAN_TYPE_BACKGROUND: 4869286441Srpaulo * @IWM_SCAN_TYPE_OS: 4870286441Srpaulo * @IWM_SCAN_TYPE_ROAMING: 4871286441Srpaulo * @IWM_SCAN_TYPE_ACTION: 4872286441Srpaulo * @IWM_SCAN_TYPE_DISCOVERY: 4873286441Srpaulo * @IWM_SCAN_TYPE_DISCOVERY_FORCED: 4874286441Srpaulo */ 4875286441Srpauloenum iwm_scan_type { 4876286441Srpaulo IWM_SCAN_TYPE_FORCED = 0, 4877286441Srpaulo IWM_SCAN_TYPE_BACKGROUND = 1, 4878286441Srpaulo IWM_SCAN_TYPE_OS = 2, 4879286441Srpaulo IWM_SCAN_TYPE_ROAMING = 3, 4880286441Srpaulo IWM_SCAN_TYPE_ACTION = 4, 4881286441Srpaulo IWM_SCAN_TYPE_DISCOVERY = 5, 4882286441Srpaulo IWM_SCAN_TYPE_DISCOVERY_FORCED = 6, 4883286441Srpaulo}; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */ 4884286441Srpaulo 4885286441Srpaulo/* Maximal number of channels to scan */ 4886286441Srpaulo#define IWM_MAX_NUM_SCAN_CHANNELS 0x24 4887286441Srpaulo 4888286441Srpaulo/** 4889303628Ssbruno * iwm_scan_schedule_lmac - schedule of scan offload 4890303628Ssbruno * @delay: delay between iterations, in seconds. 4891303628Ssbruno * @iterations: num of scan iterations 4892303628Ssbruno * @full_scan_mul: number of partial scans before each full scan 4893286441Srpaulo */ 4894303628Ssbrunostruct iwm_scan_schedule_lmac { 4895303628Ssbruno uint16_t delay; 4896303628Ssbruno uint8_t iterations; 4897303628Ssbruno uint8_t full_scan_mul; 4898303628Ssbruno} __packed; /* SCAN_SCHEDULE_API_S */ 4899303628Ssbruno 4900303628Ssbruno/** 4901303628Ssbruno * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4902303628Ssbruno * @tx_flags: combination of TX_CMD_FLG_* 4903303628Ssbruno * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4904303628Ssbruno * cleared. Combination of RATE_MCS_* 4905303628Ssbruno * @sta_id: index of destination station in FW station table 4906303628Ssbruno * @reserved: for alignment and future use 4907303628Ssbruno */ 4908303628Ssbrunostruct iwm_scan_req_tx_cmd { 4909303628Ssbruno uint32_t tx_flags; 4910303628Ssbruno uint32_t rate_n_flags; 4911303628Ssbruno uint8_t sta_id; 4912303628Ssbruno uint8_t reserved[3]; 4913303628Ssbruno} __packed; 4914303628Ssbruno 4915303628Ssbrunoenum iwm_scan_channel_flags_lmac { 4916303628Ssbruno IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4917303628Ssbruno IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4918303628Ssbruno}; 4919303628Ssbruno 4920303628Ssbruno/** 4921303628Ssbruno * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4922303628Ssbruno * @flags: bits 1-20: directed scan to i'th ssid 4923303628Ssbruno * other bits &enum iwm_scan_channel_flags_lmac 4924303628Ssbruno * @channel_number: channel number 1-13 etc 4925303628Ssbruno * @iter_count: scan iteration on this channel 4926303628Ssbruno * @iter_interval: interval in seconds between iterations on one channel 4927303628Ssbruno */ 4928303628Ssbrunostruct iwm_scan_channel_cfg_lmac { 4929303628Ssbruno uint32_t flags; 4930303628Ssbruno uint16_t channel_num; 4931303628Ssbruno uint16_t iter_count; 4932303628Ssbruno uint32_t iter_interval; 4933303628Ssbruno} __packed; 4934303628Ssbruno 4935303628Ssbruno/* 4936303628Ssbruno * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4937303628Ssbruno * @offset: offset in the data block 4938303628Ssbruno * @len: length of the segment 4939303628Ssbruno */ 4940303628Ssbrunostruct iwm_scan_probe_segment { 4941303628Ssbruno uint16_t offset; 4942286441Srpaulo uint16_t len; 4943303628Ssbruno} __packed; 4944303628Ssbruno 4945303628Ssbruno/* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4946303628Ssbruno * @mac_header: first (and common) part of the probe 4947303628Ssbruno * @band_data: band specific data 4948303628Ssbruno * @common_data: last (and common) part of the probe 4949303628Ssbruno * @buf: raw data block 4950303628Ssbruno */ 4951303628Ssbrunostruct iwm_scan_probe_req { 4952303628Ssbruno struct iwm_scan_probe_segment mac_header; 4953303628Ssbruno struct iwm_scan_probe_segment band_data[2]; 4954303628Ssbruno struct iwm_scan_probe_segment common_data; 4955303628Ssbruno uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4956303628Ssbruno} __packed; 4957303628Ssbruno 4958303628Ssbrunoenum iwm_scan_channel_flags { 4959303628Ssbruno IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4960303628Ssbruno IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4961303628Ssbruno IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4962303628Ssbruno}; 4963303628Ssbruno 4964303628Ssbruno/* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4965303628Ssbruno * @flags: enum iwm_scan_channel_flags 4966303628Ssbruno * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4967303628Ssbruno * involved. 4968303628Ssbruno * 1 - EBS is disabled. 4969303628Ssbruno * 2 - every second scan will be full scan(and so on). 4970303628Ssbruno */ 4971303628Ssbrunostruct iwm_scan_channel_opt { 4972303628Ssbruno uint16_t flags; 4973303628Ssbruno uint16_t non_ebs_ratio; 4974303628Ssbruno} __packed; 4975303628Ssbruno 4976303628Ssbruno/** 4977303628Ssbruno * iwm_mvm_lmac_scan_flags 4978303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4979303628Ssbruno * without filtering. 4980303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4981303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4982303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4983303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4984303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4985303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4986303628Ssbruno * and DS parameter set IEs into probe requests. 4987303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4988303628Ssbruno * 1, 6 and 11. 4989303628Ssbruno * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4990303628Ssbruno */ 4991303628Ssbrunoenum iwm_mvm_lmac_scan_flags { 4992303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4993303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4994303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4995303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4996303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4997303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4998303628Ssbruno IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4999303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 5000303628Ssbruno IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 5001303628Ssbruno}; 5002303628Ssbruno 5003303628Ssbrunoenum iwm_scan_priority { 5004303628Ssbruno IWM_SCAN_PRIORITY_LOW, 5005303628Ssbruno IWM_SCAN_PRIORITY_MEDIUM, 5006303628Ssbruno IWM_SCAN_PRIORITY_HIGH, 5007303628Ssbruno}; 5008303628Ssbruno 5009303628Ssbruno/** 5010303628Ssbruno * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 5011303628Ssbruno * @reserved1: for alignment and future use 5012303628Ssbruno * @channel_num: num of channels to scan 5013303628Ssbruno * @active-dwell: dwell time for active channels 5014303628Ssbruno * @passive-dwell: dwell time for passive channels 5015303628Ssbruno * @fragmented-dwell: dwell time for fragmented passive scan 5016303628Ssbruno * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 5017303628Ssbruno * @reserved2: for alignment and future use 5018303628Ssbruno * @rx_chain_selct: PHY_RX_CHAIN_* flags 5019303628Ssbruno * @scan_flags: &enum iwm_mvm_lmac_scan_flags 5020303628Ssbruno * @max_out_time: max time (in TU) to be out of associated channel 5021303628Ssbruno * @suspend_time: pause scan this long (TUs) when returning to service channel 5022303628Ssbruno * @flags: RXON flags 5023303628Ssbruno * @filter_flags: RXON filter 5024303628Ssbruno * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 5025303628Ssbruno * @direct_scan: list of SSIDs for directed active scan 5026303628Ssbruno * @scan_prio: enum iwm_scan_priority 5027303628Ssbruno * @iter_num: number of scan iterations 5028303628Ssbruno * @delay: delay in seconds before first iteration 5029303628Ssbruno * @schedule: two scheduling plans. The first one is finite, the second one can 5030303628Ssbruno * be infinite. 5031303628Ssbruno * @channel_opt: channel optimization options, for full and partial scan 5032303628Ssbruno * @data: channel configuration and probe request packet. 5033303628Ssbruno */ 5034303628Ssbrunostruct iwm_scan_req_lmac { 5035303628Ssbruno /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 5036303628Ssbruno uint32_t reserved1; 5037303628Ssbruno uint8_t n_channels; 5038303628Ssbruno uint8_t active_dwell; 5039303628Ssbruno uint8_t passive_dwell; 5040303628Ssbruno uint8_t fragmented_dwell; 5041303628Ssbruno uint8_t extended_dwell; 5042303628Ssbruno uint8_t reserved2; 5043303628Ssbruno uint16_t rx_chain_select; 5044303628Ssbruno uint32_t scan_flags; 5045286441Srpaulo uint32_t max_out_time; 5046286441Srpaulo uint32_t suspend_time; 5047303628Ssbruno /* RX_ON_FLAGS_API_S_VER_1 */ 5048303628Ssbruno uint32_t flags; 5049286441Srpaulo uint32_t filter_flags; 5050303628Ssbruno struct iwm_scan_req_tx_cmd tx_cmd[2]; 5051286441Srpaulo struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5052303628Ssbruno uint32_t scan_prio; 5053303628Ssbruno /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 5054303628Ssbruno uint32_t iter_num; 5055303628Ssbruno uint32_t delay; 5056303628Ssbruno struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5057303628Ssbruno struct iwm_scan_channel_opt channel_opt[2]; 5058303628Ssbruno uint8_t data[]; 5059303628Ssbruno} __packed; 5060286441Srpaulo 5061303628Ssbruno/** 5062303628Ssbruno * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5063303628Ssbruno * @last_schedule_line: last schedule line executed (fast or regular) 5064303628Ssbruno * @last_schedule_iteration: last scan iteration executed before scan abort 5065303628Ssbruno * @status: enum iwm_scan_offload_complete_status 5066303628Ssbruno * @ebs_status: EBS success status &enum iwm_scan_ebs_status 5067303628Ssbruno * @time_after_last_iter; time in seconds elapsed after last iteration 5068303628Ssbruno */ 5069303628Ssbrunostruct iwm_periodic_scan_complete { 5070303628Ssbruno uint8_t last_schedule_line; 5071303628Ssbruno uint8_t last_schedule_iteration; 5072303628Ssbruno uint8_t status; 5073303628Ssbruno uint8_t ebs_status; 5074303628Ssbruno uint32_t time_after_last_iter; 5075303628Ssbruno uint32_t reserved; 5076303628Ssbruno} __packed; 5077286441Srpaulo 5078286441Srpaulo/* Response to scan request contains only status with one of these values */ 5079286441Srpaulo#define IWM_SCAN_RESPONSE_OK 0x1 5080286441Srpaulo#define IWM_SCAN_RESPONSE_ERROR 0x2 5081286441Srpaulo 5082286441Srpaulo/* 5083286441Srpaulo * IWM_SCAN_ABORT_CMD = 0x81 5084286441Srpaulo * When scan abort is requested, the command has no fields except the common 5085286441Srpaulo * header. The response contains only a status with one of these values. 5086286441Srpaulo */ 5087286441Srpaulo#define IWM_SCAN_ABORT_POSSIBLE 0x1 5088286441Srpaulo#define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */ 5089286441Srpaulo 5090286441Srpaulo/* TODO: complete documentation */ 5091286441Srpaulo#define IWM_SCAN_OWNER_STATUS 0x1 5092286441Srpaulo#define IWM_MEASURE_OWNER_STATUS 0x2 5093286441Srpaulo 5094286441Srpaulo/** 5095286441Srpaulo * struct iwm_scan_start_notif - notifies start of scan in the device 5096286441Srpaulo * ( IWM_SCAN_START_NOTIFICATION = 0x82 ) 5097286441Srpaulo * @tsf_low: TSF timer (lower half) in usecs 5098286441Srpaulo * @tsf_high: TSF timer (higher half) in usecs 5099286441Srpaulo * @beacon_timer: structured as follows: 5100286441Srpaulo * bits 0:19 - beacon interval in usecs 5101286441Srpaulo * bits 20:23 - reserved (0) 5102286441Srpaulo * bits 24:31 - number of beacons 5103286441Srpaulo * @channel: which channel is scanned 5104286441Srpaulo * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5105286441Srpaulo * @status: one of *_OWNER_STATUS 5106286441Srpaulo */ 5107286441Srpaulostruct iwm_scan_start_notif { 5108286441Srpaulo uint32_t tsf_low; 5109286441Srpaulo uint32_t tsf_high; 5110286441Srpaulo uint32_t beacon_timer; 5111286441Srpaulo uint8_t channel; 5112286441Srpaulo uint8_t band; 5113286441Srpaulo uint8_t reserved[2]; 5114286441Srpaulo uint32_t status; 5115286441Srpaulo} __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */ 5116286441Srpaulo 5117286441Srpaulo/* scan results probe_status first bit indicates success */ 5118286441Srpaulo#define IWM_SCAN_PROBE_STATUS_OK 0 5119286441Srpaulo#define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0) 5120286441Srpaulo/* error statuses combined with TX_FAILED */ 5121286441Srpaulo#define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1) 5122286441Srpaulo#define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2) 5123286441Srpaulo 5124286441Srpaulo/* How many statistics are gathered for each channel */ 5125286441Srpaulo#define IWM_SCAN_RESULTS_STATISTICS 1 5126286441Srpaulo 5127286441Srpaulo/** 5128286441Srpaulo * enum iwm_scan_complete_status - status codes for scan complete notifications 5129286441Srpaulo * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 5130286441Srpaulo * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 5131286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 5132286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 5133286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 5134286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 5135286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 5136286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 5137286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 5138286441Srpaulo * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 5139286441Srpaulo * (not an error!) 5140286441Srpaulo * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 5141286441Srpaulo * asked for 5142286441Srpaulo * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 5143286441Srpaulo*/ 5144286441Srpauloenum iwm_scan_complete_status { 5145286441Srpaulo IWM_SCAN_COMP_STATUS_OK = 0x1, 5146286441Srpaulo IWM_SCAN_COMP_STATUS_ABORT = 0x2, 5147286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 5148286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 5149286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 5150286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 5151286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 5152286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 5153286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 5154286441Srpaulo IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 5155286441Srpaulo IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 5156286441Srpaulo IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 5157286441Srpaulo}; 5158286441Srpaulo 5159286441Srpaulo/** 5160286441Srpaulo * struct iwm_scan_results_notif - scan results for one channel 5161286441Srpaulo * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 5162286441Srpaulo * @channel: which channel the results are from 5163286441Srpaulo * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5164286441Srpaulo * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 5165286441Srpaulo * @num_probe_not_sent: # of request that weren't sent due to not enough time 5166286441Srpaulo * @duration: duration spent in channel, in usecs 5167286441Srpaulo * @statistics: statistics gathered for this channel 5168286441Srpaulo */ 5169286441Srpaulostruct iwm_scan_results_notif { 5170286441Srpaulo uint8_t channel; 5171286441Srpaulo uint8_t band; 5172286441Srpaulo uint8_t probe_status; 5173286441Srpaulo uint8_t num_probe_not_sent; 5174286441Srpaulo uint32_t duration; 5175286441Srpaulo uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 5176286441Srpaulo} __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 5177286441Srpaulo 5178286441Srpaulo/** 5179286441Srpaulo * struct iwm_scan_complete_notif - notifies end of scanning (all channels) 5180286441Srpaulo * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 ) 5181286441Srpaulo * @scanned_channels: number of channels scanned (and number of valid results) 5182286441Srpaulo * @status: one of IWM_SCAN_COMP_STATUS_* 5183286441Srpaulo * @bt_status: BT on/off status 5184286441Srpaulo * @last_channel: last channel that was scanned 5185286441Srpaulo * @tsf_low: TSF timer (lower half) in usecs 5186286441Srpaulo * @tsf_high: TSF timer (higher half) in usecs 5187286441Srpaulo * @results: all scan results, only "scanned_channels" of them are valid 5188286441Srpaulo */ 5189286441Srpaulostruct iwm_scan_complete_notif { 5190286441Srpaulo uint8_t scanned_channels; 5191286441Srpaulo uint8_t status; 5192286441Srpaulo uint8_t bt_status; 5193286441Srpaulo uint8_t last_channel; 5194286441Srpaulo uint32_t tsf_low; 5195286441Srpaulo uint32_t tsf_high; 5196286441Srpaulo struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS]; 5197286441Srpaulo} __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */ 5198286441Srpaulo 5199286441Srpauloenum iwm_scan_framework_client { 5200286441Srpaulo IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 5201286441Srpaulo IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 5202286441Srpaulo IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 5203286441Srpaulo}; 5204286441Srpaulo 5205286441Srpaulo/** 5206286441Srpaulo * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6 5207286441Srpaulo * @scan_flags: see enum iwm_scan_flags 5208286441Srpaulo * @channel_count: channels in channel list 5209286441Srpaulo * @quiet_time: dwell time, in milisiconds, on quiet channel 5210286441Srpaulo * @quiet_plcp_th: quiet channel num of packets threshold 5211286441Srpaulo * @good_CRC_th: passive to active promotion threshold 5212286441Srpaulo * @rx_chain: RXON rx chain. 5213286441Srpaulo * @max_out_time: max uSec to be out of assoceated channel 5214286441Srpaulo * @suspend_time: pause scan this long when returning to service channel 5215286441Srpaulo * @flags: RXON flags 5216286441Srpaulo * @filter_flags: RXONfilter 5217286441Srpaulo * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz. 5218286441Srpaulo * @direct_scan: list of SSIDs for directed active scan 5219286441Srpaulo * @scan_type: see enum iwm_scan_type. 5220286441Srpaulo * @rep_count: repetition count for each scheduled scan iteration. 5221286441Srpaulo */ 5222286441Srpaulostruct iwm_scan_offload_cmd { 5223286441Srpaulo uint16_t len; 5224286441Srpaulo uint8_t scan_flags; 5225286441Srpaulo uint8_t channel_count; 5226286441Srpaulo uint16_t quiet_time; 5227286441Srpaulo uint16_t quiet_plcp_th; 5228286441Srpaulo uint16_t good_CRC_th; 5229286441Srpaulo uint16_t rx_chain; 5230286441Srpaulo uint32_t max_out_time; 5231286441Srpaulo uint32_t suspend_time; 5232286441Srpaulo /* IWM_RX_ON_FLAGS_API_S_VER_1 */ 5233286441Srpaulo uint32_t flags; 5234286441Srpaulo uint32_t filter_flags; 5235286441Srpaulo struct iwm_tx_cmd tx_cmd[2]; 5236286441Srpaulo /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5237286441Srpaulo struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5238286441Srpaulo uint32_t scan_type; 5239286441Srpaulo uint32_t rep_count; 5240286441Srpaulo} __packed; 5241286441Srpaulo 5242286441Srpauloenum iwm_scan_offload_channel_flags { 5243286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0), 5244286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22), 5245286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24), 5246286441Srpaulo IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25), 5247286441Srpaulo}; 5248286441Srpaulo 5249286441Srpaulo/** 5250286441Srpaulo * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S 5251286441Srpaulo * @type: bitmap - see enum iwm_scan_offload_channel_flags. 5252286441Srpaulo * 0: passive (0) or active (1) scan. 5253286441Srpaulo * 1-20: directed scan to i'th ssid. 5254286441Srpaulo * 22: channel width configuation - 1 for narrow. 5255286441Srpaulo * 24: full scan. 5256286441Srpaulo * 25: partial scan. 5257286441Srpaulo * @channel_number: channel number 1-13 etc. 5258286441Srpaulo * @iter_count: repetition count for the channel. 5259286441Srpaulo * @iter_interval: interval between two innteration on one channel. 5260286441Srpaulo * @dwell_time: entry 0 - active scan, entry 1 - passive scan. 5261286441Srpaulo */ 5262286441Srpaulostruct iwm_scan_channel_cfg { 5263286441Srpaulo uint32_t type[IWM_MAX_SCAN_CHANNELS]; 5264286441Srpaulo uint16_t channel_number[IWM_MAX_SCAN_CHANNELS]; 5265286441Srpaulo uint16_t iter_count[IWM_MAX_SCAN_CHANNELS]; 5266286441Srpaulo uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS]; 5267286441Srpaulo uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2]; 5268286441Srpaulo} __packed; 5269286441Srpaulo 5270286441Srpaulo/** 5271286441Srpaulo * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S 5272286441Srpaulo * @scan_cmd: scan command fixed part 5273286441Srpaulo * @channel_cfg: scan channel configuration 5274286441Srpaulo * @data: probe request frames (one per band) 5275286441Srpaulo */ 5276286441Srpaulostruct iwm_scan_offload_cfg { 5277286441Srpaulo struct iwm_scan_offload_cmd scan_cmd; 5278286441Srpaulo struct iwm_scan_channel_cfg channel_cfg; 5279286441Srpaulo uint8_t data[0]; 5280286441Srpaulo} __packed; 5281286441Srpaulo 5282286441Srpaulo/** 5283286441Srpaulo * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 5284286441Srpaulo * @ssid: MAC address to filter out 5285286441Srpaulo * @reported_rssi: AP rssi reported to the host 5286286441Srpaulo * @client_bitmap: clients ignore this entry - enum scan_framework_client 5287286441Srpaulo */ 5288286441Srpaulostruct iwm_scan_offload_blacklist { 5289286441Srpaulo uint8_t ssid[IEEE80211_ADDR_LEN]; 5290286441Srpaulo uint8_t reported_rssi; 5291286441Srpaulo uint8_t client_bitmap; 5292286441Srpaulo} __packed; 5293286441Srpaulo 5294286441Srpauloenum iwm_scan_offload_network_type { 5295286441Srpaulo IWM_NETWORK_TYPE_BSS = 1, 5296286441Srpaulo IWM_NETWORK_TYPE_IBSS = 2, 5297286441Srpaulo IWM_NETWORK_TYPE_ANY = 3, 5298286441Srpaulo}; 5299286441Srpaulo 5300286441Srpauloenum iwm_scan_offload_band_selection { 5301286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5302286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5303286441Srpaulo IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5304286441Srpaulo}; 5305286441Srpaulo 5306286441Srpaulo/** 5307286441Srpaulo * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5308286441Srpaulo * @ssid_index: index to ssid list in fixed part 5309286441Srpaulo * @unicast_cipher: encryption olgorithm to match - bitmap 5310286441Srpaulo * @aut_alg: authentication olgorithm to match - bitmap 5311286441Srpaulo * @network_type: enum iwm_scan_offload_network_type 5312286441Srpaulo * @band_selection: enum iwm_scan_offload_band_selection 5313286441Srpaulo * @client_bitmap: clients waiting for match - enum scan_framework_client 5314286441Srpaulo */ 5315286441Srpaulostruct iwm_scan_offload_profile { 5316286441Srpaulo uint8_t ssid_index; 5317286441Srpaulo uint8_t unicast_cipher; 5318286441Srpaulo uint8_t auth_alg; 5319286441Srpaulo uint8_t network_type; 5320286441Srpaulo uint8_t band_selection; 5321286441Srpaulo uint8_t client_bitmap; 5322286441Srpaulo uint8_t reserved[2]; 5323286441Srpaulo} __packed; 5324286441Srpaulo 5325286441Srpaulo/** 5326286441Srpaulo * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5327286441Srpaulo * @blaclist: AP list to filter off from scan results 5328286441Srpaulo * @profiles: profiles to search for match 5329286441Srpaulo * @blacklist_len: length of blacklist 5330286441Srpaulo * @num_profiles: num of profiles in the list 5331286441Srpaulo * @match_notify: clients waiting for match found notification 5332286441Srpaulo * @pass_match: clients waiting for the results 5333286441Srpaulo * @active_clients: active clients bitmap - enum scan_framework_client 5334286441Srpaulo * @any_beacon_notify: clients waiting for match notification without match 5335286441Srpaulo */ 5336286441Srpaulostruct iwm_scan_offload_profile_cfg { 5337286441Srpaulo struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5338286441Srpaulo uint8_t blacklist_len; 5339286441Srpaulo uint8_t num_profiles; 5340286441Srpaulo uint8_t match_notify; 5341286441Srpaulo uint8_t pass_match; 5342286441Srpaulo uint8_t active_clients; 5343286441Srpaulo uint8_t any_beacon_notify; 5344286441Srpaulo uint8_t reserved[2]; 5345286441Srpaulo} __packed; 5346286441Srpaulo 5347286441Srpaulo/** 5348286441Srpaulo * iwm_scan_offload_schedule - schedule of scan offload 5349286441Srpaulo * @delay: delay between iterations, in seconds. 5350286441Srpaulo * @iterations: num of scan iterations 5351286441Srpaulo * @full_scan_mul: number of partial scans before each full scan 5352286441Srpaulo */ 5353286441Srpaulostruct iwm_scan_offload_schedule { 5354286441Srpaulo uint16_t delay; 5355286441Srpaulo uint8_t iterations; 5356286441Srpaulo uint8_t full_scan_mul; 5357286441Srpaulo} __packed; 5358286441Srpaulo 5359286441Srpaulo/* 5360286441Srpaulo * iwm_scan_offload_flags 5361286441Srpaulo * 5362286441Srpaulo * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering. 5363286441Srpaulo * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan. 5364286441Srpaulo * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan 5365286441Srpaulo * on A band. 5366286441Srpaulo */ 5367286441Srpauloenum iwm_scan_offload_flags { 5368286441Srpaulo IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0), 5369286441Srpaulo IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2), 5370286441Srpaulo IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3), 5371286441Srpaulo}; 5372286441Srpaulo 5373286441Srpaulo/** 5374286441Srpaulo * iwm_scan_offload_req - scan offload request command 5375286441Srpaulo * @flags: bitmap - enum iwm_scan_offload_flags. 5376286441Srpaulo * @watchdog: maximum scan duration in TU. 5377286441Srpaulo * @delay: delay in seconds before first iteration. 5378286441Srpaulo * @schedule_line: scan offload schedule, for fast and regular scan. 5379286441Srpaulo */ 5380286441Srpaulostruct iwm_scan_offload_req { 5381286441Srpaulo uint16_t flags; 5382286441Srpaulo uint16_t watchdog; 5383286441Srpaulo uint16_t delay; 5384286441Srpaulo uint16_t reserved; 5385286441Srpaulo struct iwm_scan_offload_schedule schedule_line[2]; 5386286441Srpaulo} __packed; 5387286441Srpaulo 5388286441Srpauloenum iwm_scan_offload_compleate_status { 5389286441Srpaulo IWM_SCAN_OFFLOAD_COMPLETED = 1, 5390286441Srpaulo IWM_SCAN_OFFLOAD_ABORTED = 2, 5391286441Srpaulo}; 5392286441Srpaulo 5393286441Srpaulo/** 5394303628Ssbruno * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5395303628Ssbruno * SCAN_COMPLETE_NTF_API_S_VER_3 5396303628Ssbruno * @scanned_channels: number of channels scanned (and number of valid results) 5397303628Ssbruno * @status: one of SCAN_COMP_STATUS_* 5398303628Ssbruno * @bt_status: BT on/off status 5399303628Ssbruno * @last_channel: last channel that was scanned 5400303628Ssbruno * @tsf_low: TSF timer (lower half) in usecs 5401303628Ssbruno * @tsf_high: TSF timer (higher half) in usecs 5402303628Ssbruno * @results: an array of scan results, only "scanned_channels" of them are valid 5403303628Ssbruno */ 5404303628Ssbrunostruct iwm_lmac_scan_complete_notif { 5405303628Ssbruno uint8_t scanned_channels; 5406303628Ssbruno uint8_t status; 5407303628Ssbruno uint8_t bt_status; 5408303628Ssbruno uint8_t last_channel; 5409303628Ssbruno uint32_t tsf_low; 5410303628Ssbruno uint32_t tsf_high; 5411303628Ssbruno struct iwm_scan_results_notif results[]; 5412303628Ssbruno} __packed; 5413303628Ssbruno 5414303628Ssbruno 5415303628Ssbruno/** 5416286441Srpaulo * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1 5417286441Srpaulo * @last_schedule_line: last schedule line executed (fast or regular) 5418286441Srpaulo * @last_schedule_iteration: last scan iteration executed before scan abort 5419286441Srpaulo * @status: enum iwm_scan_offload_compleate_status 5420286441Srpaulo */ 5421286441Srpaulostruct iwm_scan_offload_complete { 5422286441Srpaulo uint8_t last_schedule_line; 5423286441Srpaulo uint8_t last_schedule_iteration; 5424286441Srpaulo uint8_t status; 5425286441Srpaulo uint8_t reserved; 5426286441Srpaulo} __packed; 5427286441Srpaulo 5428286441Srpaulo/** 5429286441Srpaulo * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1 5430286441Srpaulo * @ssid_bitmap: SSIDs indexes found in this iteration 5431286441Srpaulo * @client_bitmap: clients that are active and wait for this notification 5432286441Srpaulo */ 5433286441Srpaulostruct iwm_sched_scan_results { 5434286441Srpaulo uint16_t ssid_bitmap; 5435286441Srpaulo uint8_t client_bitmap; 5436286441Srpaulo uint8_t reserved; 5437286441Srpaulo}; 5438286441Srpaulo 5439286441Srpaulo/* 5440286441Srpaulo * END mvm/fw-api-scan.h 5441286441Srpaulo */ 5442286441Srpaulo 5443286441Srpaulo/* 5444286441Srpaulo * BEGIN mvm/fw-api-sta.h 5445286441Srpaulo */ 5446286441Srpaulo 5447303628Ssbruno/* UMAC Scan API */ 5448303628Ssbruno 5449303628Ssbruno/* The maximum of either of these cannot exceed 8, because we use an 5450303628Ssbruno * 8-bit mask (see IWM_MVM_SCAN_MASK). 5451303628Ssbruno */ 5452303628Ssbruno#define IWM_MVM_MAX_UMAC_SCANS 8 5453303628Ssbruno#define IWM_MVM_MAX_LMAC_SCANS 1 5454303628Ssbruno 5455303628Ssbrunoenum iwm_scan_config_flags { 5456303628Ssbruno IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5457303628Ssbruno IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5458303628Ssbruno IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5459303628Ssbruno IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5460303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5461303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5462303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5463303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5464303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5465303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5466303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5467303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5468303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5469303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5470303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5471303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5472303628Ssbruno IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5473303628Ssbruno IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5474303628Ssbruno 5475303628Ssbruno /* Bits 26-31 are for num of channels in channel_array */ 5476303628Ssbruno#define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5477303628Ssbruno}; 5478303628Ssbruno 5479303628Ssbrunoenum iwm_scan_config_rates { 5480303628Ssbruno /* OFDM basic rates */ 5481303628Ssbruno IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5482303628Ssbruno IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5483303628Ssbruno IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5484303628Ssbruno IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5485303628Ssbruno IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5486303628Ssbruno IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5487303628Ssbruno IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5488303628Ssbruno IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5489303628Ssbruno /* CCK basic rates */ 5490303628Ssbruno IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5491303628Ssbruno IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5492303628Ssbruno IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5493303628Ssbruno IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5494303628Ssbruno 5495303628Ssbruno /* Bits 16-27 are for supported rates */ 5496303628Ssbruno#define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5497303628Ssbruno}; 5498303628Ssbruno 5499303628Ssbrunoenum iwm_channel_flags { 5500303628Ssbruno IWM_CHANNEL_FLAG_EBS = (1 << 0), 5501303628Ssbruno IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5502303628Ssbruno IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5503303628Ssbruno IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5504303628Ssbruno}; 5505303628Ssbruno 5506286441Srpaulo/** 5507303628Ssbruno * struct iwm_scan_config 5508303628Ssbruno * @flags: enum scan_config_flags 5509303628Ssbruno * @tx_chains: valid_tx antenna - ANT_* definitions 5510303628Ssbruno * @rx_chains: valid_rx antenna - ANT_* definitions 5511303628Ssbruno * @legacy_rates: default legacy rates - enum scan_config_rates 5512303628Ssbruno * @out_of_channel_time: default max out of serving channel time 5513303628Ssbruno * @suspend_time: default max suspend time 5514303628Ssbruno * @dwell_active: default dwell time for active scan 5515303628Ssbruno * @dwell_passive: default dwell time for passive scan 5516303628Ssbruno * @dwell_fragmented: default dwell time for fragmented scan 5517303628Ssbruno * @dwell_extended: default dwell time for channels 1, 6 and 11 5518303628Ssbruno * @mac_addr: default mac address to be used in probes 5519303628Ssbruno * @bcast_sta_id: the index of the station in the fw 5520303628Ssbruno * @channel_flags: default channel flags - enum iwm_channel_flags 5521303628Ssbruno * scan_config_channel_flag 5522303628Ssbruno * @channel_array: default supported channels 5523303628Ssbruno */ 5524303628Ssbrunostruct iwm_scan_config { 5525303628Ssbruno uint32_t flags; 5526303628Ssbruno uint32_t tx_chains; 5527303628Ssbruno uint32_t rx_chains; 5528303628Ssbruno uint32_t legacy_rates; 5529303628Ssbruno uint32_t out_of_channel_time; 5530303628Ssbruno uint32_t suspend_time; 5531303628Ssbruno uint8_t dwell_active; 5532303628Ssbruno uint8_t dwell_passive; 5533303628Ssbruno uint8_t dwell_fragmented; 5534303628Ssbruno uint8_t dwell_extended; 5535303628Ssbruno uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5536303628Ssbruno uint8_t bcast_sta_id; 5537303628Ssbruno uint8_t channel_flags; 5538303628Ssbruno uint8_t channel_array[]; 5539303628Ssbruno} __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5540303628Ssbruno 5541303628Ssbruno/** 5542303628Ssbruno * iwm_umac_scan_flags 5543303628Ssbruno *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5544303628Ssbruno * can be preempted by other scan requests with higher priority. 5545303628Ssbruno * The low priority scan will be resumed when the higher proirity scan is 5546303628Ssbruno * completed. 5547303628Ssbruno *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5548303628Ssbruno * when scan starts. 5549303628Ssbruno */ 5550303628Ssbrunoenum iwm_umac_scan_flags { 5551303628Ssbruno IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5552303628Ssbruno IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5553303628Ssbruno}; 5554303628Ssbruno 5555303628Ssbrunoenum iwm_umac_scan_uid_offsets { 5556303628Ssbruno IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5557303628Ssbruno IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5558303628Ssbruno}; 5559303628Ssbruno 5560303628Ssbrunoenum iwm_umac_scan_general_flags { 5561303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5562303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5563303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5564303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5565303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5566303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5567303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5568303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5569303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5570303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5571303628Ssbruno IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5572303628Ssbruno}; 5573303628Ssbruno 5574303628Ssbruno/** 5575303628Ssbruno * struct iwm_scan_channel_cfg_umac 5576303628Ssbruno * @flags: bitmap - 0-19: directed scan to i'th ssid. 5577303628Ssbruno * @channel_num: channel number 1-13 etc. 5578303628Ssbruno * @iter_count: repetition count for the channel. 5579303628Ssbruno * @iter_interval: interval between two scan iterations on one channel. 5580303628Ssbruno */ 5581303628Ssbrunostruct iwm_scan_channel_cfg_umac { 5582303628Ssbruno uint32_t flags; 5583303628Ssbruno uint8_t channel_num; 5584303628Ssbruno uint8_t iter_count; 5585303628Ssbruno uint16_t iter_interval; 5586303628Ssbruno} __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5587303628Ssbruno 5588303628Ssbruno/** 5589303628Ssbruno * struct iwm_scan_umac_schedule 5590303628Ssbruno * @interval: interval in seconds between scan iterations 5591303628Ssbruno * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5592303628Ssbruno * @reserved: for alignment and future use 5593303628Ssbruno */ 5594303628Ssbrunostruct iwm_scan_umac_schedule { 5595303628Ssbruno uint16_t interval; 5596303628Ssbruno uint8_t iter_count; 5597303628Ssbruno uint8_t reserved; 5598303628Ssbruno} __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5599303628Ssbruno 5600303628Ssbruno/** 5601303628Ssbruno * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5602303628Ssbruno * parameters following channels configuration array. 5603303628Ssbruno * @schedule: two scheduling plans. 5604303628Ssbruno * @delay: delay in TUs before starting the first scan iteration 5605303628Ssbruno * @reserved: for future use and alignment 5606303628Ssbruno * @preq: probe request with IEs blocks 5607303628Ssbruno * @direct_scan: list of SSIDs for directed active scan 5608303628Ssbruno */ 5609303628Ssbrunostruct iwm_scan_req_umac_tail { 5610303628Ssbruno /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5611303628Ssbruno struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5612303628Ssbruno uint16_t delay; 5613303628Ssbruno uint16_t reserved; 5614303628Ssbruno /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5615303628Ssbruno struct iwm_scan_probe_req preq; 5616303628Ssbruno struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5617303628Ssbruno} __packed; 5618303628Ssbruno 5619303628Ssbruno/** 5620303628Ssbruno * struct iwm_scan_req_umac 5621303628Ssbruno * @flags: &enum iwm_umac_scan_flags 5622303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5623303628Ssbruno * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5624303628Ssbruno * @general_flags: &enum iwm_umac_scan_general_flags 5625303628Ssbruno * @extended_dwell: dwell time for channels 1, 6 and 11 5626303628Ssbruno * @active_dwell: dwell time for active scan 5627303628Ssbruno * @passive_dwell: dwell time for passive scan 5628303628Ssbruno * @fragmented_dwell: dwell time for fragmented passive scan 5629303628Ssbruno * @max_out_time: max out of serving channel time 5630303628Ssbruno * @suspend_time: max suspend time 5631303628Ssbruno * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5632303628Ssbruno * @channel_flags: &enum iwm_scan_channel_flags 5633303628Ssbruno * @n_channels: num of channels in scan request 5634303628Ssbruno * @reserved: for future use and alignment 5635303628Ssbruno * @data: &struct iwm_scan_channel_cfg_umac and 5636303628Ssbruno * &struct iwm_scan_req_umac_tail 5637303628Ssbruno */ 5638303628Ssbrunostruct iwm_scan_req_umac { 5639303628Ssbruno uint32_t flags; 5640303628Ssbruno uint32_t uid; 5641303628Ssbruno uint32_t ooc_priority; 5642303628Ssbruno /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5643303628Ssbruno uint32_t general_flags; 5644303628Ssbruno uint8_t extended_dwell; 5645303628Ssbruno uint8_t active_dwell; 5646303628Ssbruno uint8_t passive_dwell; 5647303628Ssbruno uint8_t fragmented_dwell; 5648303628Ssbruno uint32_t max_out_time; 5649303628Ssbruno uint32_t suspend_time; 5650303628Ssbruno uint32_t scan_priority; 5651303628Ssbruno /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5652303628Ssbruno uint8_t channel_flags; 5653303628Ssbruno uint8_t n_channels; 5654303628Ssbruno uint16_t reserved; 5655303628Ssbruno uint8_t data[]; 5656303628Ssbruno} __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5657303628Ssbruno 5658303628Ssbruno/** 5659303628Ssbruno * struct iwm_umac_scan_abort 5660303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5661303628Ssbruno * @flags: reserved 5662303628Ssbruno */ 5663303628Ssbrunostruct iwm_umac_scan_abort { 5664303628Ssbruno uint32_t uid; 5665303628Ssbruno uint32_t flags; 5666303628Ssbruno} __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5667303628Ssbruno 5668303628Ssbruno/** 5669303628Ssbruno * struct iwm_umac_scan_complete 5670303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5671303628Ssbruno * @last_schedule: last scheduling line 5672303628Ssbruno * @last_iter: last scan iteration number 5673303628Ssbruno * @scan status: &enum iwm_scan_offload_complete_status 5674303628Ssbruno * @ebs_status: &enum iwm_scan_ebs_status 5675303628Ssbruno * @time_from_last_iter: time elapsed from last iteration 5676303628Ssbruno * @reserved: for future use 5677303628Ssbruno */ 5678303628Ssbrunostruct iwm_umac_scan_complete { 5679303628Ssbruno uint32_t uid; 5680303628Ssbruno uint8_t last_schedule; 5681303628Ssbruno uint8_t last_iter; 5682303628Ssbruno uint8_t status; 5683303628Ssbruno uint8_t ebs_status; 5684303628Ssbruno uint32_t time_from_last_iter; 5685303628Ssbruno uint32_t reserved; 5686303628Ssbruno} __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5687303628Ssbruno 5688303628Ssbruno#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5689303628Ssbruno/** 5690303628Ssbruno * struct iwm_scan_offload_profile_match - match information 5691303628Ssbruno * @bssid: matched bssid 5692303628Ssbruno * @channel: channel where the match occurred 5693303628Ssbruno * @energy: 5694303628Ssbruno * @matching_feature: 5695303628Ssbruno * @matching_channels: bitmap of channels that matched, referencing 5696303628Ssbruno * the channels passed in tue scan offload request 5697303628Ssbruno */ 5698303628Ssbrunostruct iwm_scan_offload_profile_match { 5699303628Ssbruno uint8_t bssid[IEEE80211_ADDR_LEN]; 5700303628Ssbruno uint16_t reserved; 5701303628Ssbruno uint8_t channel; 5702303628Ssbruno uint8_t energy; 5703303628Ssbruno uint8_t matching_feature; 5704303628Ssbruno uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5705303628Ssbruno} __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5706303628Ssbruno 5707303628Ssbruno/** 5708303628Ssbruno * struct iwm_scan_offload_profiles_query - match results query response 5709303628Ssbruno * @matched_profiles: bitmap of matched profiles, referencing the 5710303628Ssbruno * matches passed in the scan offload request 5711303628Ssbruno * @last_scan_age: age of the last offloaded scan 5712303628Ssbruno * @n_scans_done: number of offloaded scans done 5713303628Ssbruno * @gp2_d0u: GP2 when D0U occurred 5714303628Ssbruno * @gp2_invoked: GP2 when scan offload was invoked 5715303628Ssbruno * @resume_while_scanning: not used 5716303628Ssbruno * @self_recovery: obsolete 5717303628Ssbruno * @reserved: reserved 5718303628Ssbruno * @matches: array of match information, one for each match 5719303628Ssbruno */ 5720303628Ssbrunostruct iwm_scan_offload_profiles_query { 5721303628Ssbruno uint32_t matched_profiles; 5722303628Ssbruno uint32_t last_scan_age; 5723303628Ssbruno uint32_t n_scans_done; 5724303628Ssbruno uint32_t gp2_d0u; 5725303628Ssbruno uint32_t gp2_invoked; 5726303628Ssbruno uint8_t resume_while_scanning; 5727303628Ssbruno uint8_t self_recovery; 5728303628Ssbruno uint16_t reserved; 5729303628Ssbruno struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5730303628Ssbruno} __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5731303628Ssbruno 5732303628Ssbruno/** 5733303628Ssbruno * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5734303628Ssbruno * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5735303628Ssbruno * @scanned_channels: number of channels scanned and number of valid elements in 5736303628Ssbruno * results array 5737303628Ssbruno * @status: one of SCAN_COMP_STATUS_* 5738303628Ssbruno * @bt_status: BT on/off status 5739303628Ssbruno * @last_channel: last channel that was scanned 5740303628Ssbruno * @tsf_low: TSF timer (lower half) in usecs 5741303628Ssbruno * @tsf_high: TSF timer (higher half) in usecs 5742303628Ssbruno * @results: array of scan results, only "scanned_channels" of them are valid 5743303628Ssbruno */ 5744303628Ssbrunostruct iwm_umac_scan_iter_complete_notif { 5745303628Ssbruno uint32_t uid; 5746303628Ssbruno uint8_t scanned_channels; 5747303628Ssbruno uint8_t status; 5748303628Ssbruno uint8_t bt_status; 5749303628Ssbruno uint8_t last_channel; 5750303628Ssbruno uint32_t tsf_low; 5751303628Ssbruno uint32_t tsf_high; 5752303628Ssbruno struct iwm_scan_results_notif results[]; 5753303628Ssbruno} __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5754303628Ssbruno 5755303628Ssbruno/* Please keep this enum *SORTED* by hex value. 5756303628Ssbruno * Needed for binary search, otherwise a warning will be triggered. 5757303628Ssbruno */ 5758303628Ssbrunoenum iwm_scan_subcmd_ids { 5759303628Ssbruno IWM_GSCAN_START_CMD = 0x0, 5760303628Ssbruno IWM_GSCAN_STOP_CMD = 0x1, 5761303628Ssbruno IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5762303628Ssbruno IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5763303628Ssbruno IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5764303628Ssbruno IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5765303628Ssbruno IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5766303628Ssbruno IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5767303628Ssbruno IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5768303628Ssbruno}; 5769303628Ssbruno 5770303628Ssbruno/* STA API */ 5771303628Ssbruno 5772303628Ssbruno/** 5773286441Srpaulo * enum iwm_sta_flags - flags for the ADD_STA host command 5774286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5775286441Srpaulo * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5776303628Ssbruno * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5777286441Srpaulo * @IWM_STA_FLG_PS: set if STA is in Power Save 5778286441Srpaulo * @IWM_STA_FLG_INVALID: set if STA is invalid 5779286441Srpaulo * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5780286441Srpaulo * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5781286441Srpaulo * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5782286441Srpaulo * @IWM_STA_FLG_PAN: STA is for PAN interface 5783286441Srpaulo * @IWM_STA_FLG_CLASS_AUTH: 5784286441Srpaulo * @IWM_STA_FLG_CLASS_ASSOC: 5785286441Srpaulo * @IWM_STA_FLG_CLASS_MIMO_PROT: 5786286441Srpaulo * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5787286441Srpaulo * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5788286441Srpaulo * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5789286441Srpaulo * initialised by driver and can be updated by fw upon reception of 5790286441Srpaulo * action frames that can change the channel width. When cleared the fw 5791286441Srpaulo * will send all the frames in 20MHz even when FAT channel is requested. 5792286441Srpaulo * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5793286441Srpaulo * driver and can be updated by fw upon reception of action frames. 5794286441Srpaulo * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5795286441Srpaulo */ 5796286441Srpauloenum iwm_sta_flags { 5797286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5798286441Srpaulo IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5799286441Srpaulo 5800303628Ssbruno IWM_STA_FLG_DISABLE_TX = (1 << 4), 5801286441Srpaulo 5802286441Srpaulo IWM_STA_FLG_PS = (1 << 8), 5803286441Srpaulo IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5804286441Srpaulo IWM_STA_FLG_PAN = (1 << 13), 5805286441Srpaulo IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5806286441Srpaulo IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5807286441Srpaulo IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5808286441Srpaulo 5809286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5810286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5811286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5812286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5813286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5814286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5815286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5816286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5817286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5818286441Srpaulo IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5819286441Srpaulo 5820286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5821286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5822286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5823286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5824286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5825286441Srpaulo IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5826286441Srpaulo 5827286441Srpaulo IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5828286441Srpaulo IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5829286441Srpaulo IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5830286441Srpaulo IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5831286441Srpaulo IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5832286441Srpaulo 5833286441Srpaulo IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5834286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5835286441Srpaulo IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5836286441Srpaulo IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5837286441Srpaulo}; 5838286441Srpaulo 5839286441Srpaulo/** 5840286441Srpaulo * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5841286441Srpaulo * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5842286441Srpaulo * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5843286441Srpaulo * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5844286441Srpaulo * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5845286441Srpaulo * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5846286441Srpaulo * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5847286441Srpaulo * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5848286441Srpaulo * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5849286441Srpaulo * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5850286441Srpaulo * station info array (1 - n 1X mode) 5851286441Srpaulo * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5852286441Srpaulo * @IWM_STA_KEY_NOT_VALID: key is invalid 5853286441Srpaulo * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5854286441Srpaulo * @IWM_STA_KEY_MULTICAST: set for multical key 5855286441Srpaulo * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5856286441Srpaulo */ 5857286441Srpauloenum iwm_sta_key_flag { 5858286441Srpaulo IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5859286441Srpaulo IWM_STA_KEY_FLG_WEP = (1 << 0), 5860286441Srpaulo IWM_STA_KEY_FLG_CCM = (2 << 0), 5861286441Srpaulo IWM_STA_KEY_FLG_TKIP = (3 << 0), 5862286441Srpaulo IWM_STA_KEY_FLG_EXT = (4 << 0), 5863286441Srpaulo IWM_STA_KEY_FLG_CMAC = (6 << 0), 5864286441Srpaulo IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5865286441Srpaulo IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5866286441Srpaulo 5867286441Srpaulo IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5868286441Srpaulo IWM_STA_KEY_FLG_KEYID_POS = 8, 5869286441Srpaulo IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5870286441Srpaulo IWM_STA_KEY_NOT_VALID = (1 << 11), 5871286441Srpaulo IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5872286441Srpaulo IWM_STA_KEY_MULTICAST = (1 << 14), 5873286441Srpaulo IWM_STA_KEY_MFP = (1 << 15), 5874286441Srpaulo}; 5875286441Srpaulo 5876286441Srpaulo/** 5877286441Srpaulo * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5878303628Ssbruno * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5879286441Srpaulo * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5880286441Srpaulo * @IWM_STA_MODIFY_TX_RATE: unused 5881286441Srpaulo * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5882286441Srpaulo * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5883286441Srpaulo * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5884286441Srpaulo * @IWM_STA_MODIFY_PROT_TH: 5885286441Srpaulo * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5886286441Srpaulo */ 5887286441Srpauloenum iwm_sta_modify_flag { 5888303628Ssbruno IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5889286441Srpaulo IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5890286441Srpaulo IWM_STA_MODIFY_TX_RATE = (1 << 2), 5891286441Srpaulo IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5892286441Srpaulo IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5893286441Srpaulo IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5894286441Srpaulo IWM_STA_MODIFY_PROT_TH = (1 << 6), 5895286441Srpaulo IWM_STA_MODIFY_QUEUES = (1 << 7), 5896286441Srpaulo}; 5897286441Srpaulo 5898286441Srpaulo#define IWM_STA_MODE_MODIFY 1 5899286441Srpaulo 5900286441Srpaulo/** 5901286441Srpaulo * enum iwm_sta_sleep_flag - type of sleep of the station 5902286441Srpaulo * @IWM_STA_SLEEP_STATE_AWAKE: 5903286441Srpaulo * @IWM_STA_SLEEP_STATE_PS_POLL: 5904286441Srpaulo * @IWM_STA_SLEEP_STATE_UAPSD: 5905303628Ssbruno * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5906303628Ssbruno * (last) released frame 5907286441Srpaulo */ 5908286441Srpauloenum iwm_sta_sleep_flag { 5909286441Srpaulo IWM_STA_SLEEP_STATE_AWAKE = 0, 5910286441Srpaulo IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5911286441Srpaulo IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5912303628Ssbruno IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5913286441Srpaulo}; 5914286441Srpaulo 5915286441Srpaulo/* STA ID and color bits definitions */ 5916286441Srpaulo#define IWM_STA_ID_SEED (0x0f) 5917286441Srpaulo#define IWM_STA_ID_POS (0) 5918286441Srpaulo#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5919286441Srpaulo 5920286441Srpaulo#define IWM_STA_COLOR_SEED (0x7) 5921286441Srpaulo#define IWM_STA_COLOR_POS (4) 5922286441Srpaulo#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5923286441Srpaulo 5924286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5925286441Srpaulo (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5926286441Srpaulo#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5927286441Srpaulo (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5928286441Srpaulo 5929286441Srpaulo#define IWM_STA_KEY_MAX_NUM (16) 5930286441Srpaulo#define IWM_STA_KEY_IDX_INVALID (0xff) 5931286441Srpaulo#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5932286441Srpaulo#define IWM_MAX_GLOBAL_KEYS (4) 5933286441Srpaulo#define IWM_STA_KEY_LEN_WEP40 (5) 5934286441Srpaulo#define IWM_STA_KEY_LEN_WEP104 (13) 5935286441Srpaulo 5936286441Srpaulo/** 5937286441Srpaulo * struct iwm_mvm_keyinfo - key information 5938286441Srpaulo * @key_flags: type %iwm_sta_key_flag 5939286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5940286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5941286441Srpaulo * @key_offset: key offset in the fw's key table 5942286441Srpaulo * @key: 16-byte unicast decryption key 5943286441Srpaulo * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5944286441Srpaulo * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5945286441Srpaulo * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5946286441Srpaulo */ 5947286441Srpaulostruct iwm_mvm_keyinfo { 5948286441Srpaulo uint16_t key_flags; 5949286441Srpaulo uint8_t tkip_rx_tsc_byte2; 5950286441Srpaulo uint8_t reserved1; 5951286441Srpaulo uint16_t tkip_rx_ttak[5]; 5952286441Srpaulo uint8_t key_offset; 5953286441Srpaulo uint8_t reserved2; 5954286441Srpaulo uint8_t key[16]; 5955286441Srpaulo uint64_t tx_secur_seq_cnt; 5956286441Srpaulo uint64_t hw_tkip_mic_rx_key; 5957286441Srpaulo uint64_t hw_tkip_mic_tx_key; 5958286441Srpaulo} __packed; 5959286441Srpaulo 5960303628Ssbruno#define IWM_ADD_STA_STATUS_MASK 0xFF 5961303628Ssbruno#define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5962303628Ssbruno#define IWM_ADD_STA_BAID_MASK 0x7F00 5963303628Ssbruno#define IWM_ADD_STA_BAID_SHIFT 8 5964303628Ssbruno 5965286441Srpaulo/** 5966303628Ssbruno * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5967303628Ssbruno * ( REPLY_ADD_STA = 0x18 ) 5968286441Srpaulo * @add_modify: 1: modify existing, 0: add new station 5969303628Ssbruno * @awake_acs: 5970303628Ssbruno * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5971303628Ssbruno * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5972286441Srpaulo * @mac_id_n_color: the Mac context this station belongs to 5973286441Srpaulo * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5974286441Srpaulo * @sta_id: index of station in uCode's station table 5975286441Srpaulo * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5976286441Srpaulo * alone. 1 - modify, 0 - don't change. 5977286441Srpaulo * @station_flags: look at %iwm_sta_flags 5978286441Srpaulo * @station_flags_msk: what of %station_flags have changed 5979286441Srpaulo * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5980286441Srpaulo * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5981286441Srpaulo * add_immediate_ba_ssn. 5982286441Srpaulo * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5983286441Srpaulo * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5984286441Srpaulo * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5985286441Srpaulo * add_immediate_ba_tid. 5986286441Srpaulo * @sleep_tx_count: number of packets to transmit to station even though it is 5987286441Srpaulo * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5988286441Srpaulo * keeps track of STA sleep state. 5989286441Srpaulo * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5990286441Srpaulo * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5991286441Srpaulo * mac-addr. 5992286441Srpaulo * @beamform_flags: beam forming controls 5993286441Srpaulo * @tfd_queue_msk: tfd queues used by this station 5994286441Srpaulo * 5995286441Srpaulo * The device contains an internal table of per-station information, with info 5996286441Srpaulo * on security keys, aggregation parameters, and Tx rates for initial Tx 5997286441Srpaulo * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5998286441Srpaulo * 5999286441Srpaulo * ADD_STA sets up the table entry for one station, either creating a new 6000286441Srpaulo * entry, or modifying a pre-existing one. 6001286441Srpaulo */ 6002303628Ssbrunostruct iwm_mvm_add_sta_cmd_v7 { 6003286441Srpaulo uint8_t add_modify; 6004303628Ssbruno uint8_t awake_acs; 6005286441Srpaulo uint16_t tid_disable_tx; 6006286441Srpaulo uint32_t mac_id_n_color; 6007286441Srpaulo uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6008286441Srpaulo uint16_t reserved2; 6009286441Srpaulo uint8_t sta_id; 6010286441Srpaulo uint8_t modify_mask; 6011286441Srpaulo uint16_t reserved3; 6012286441Srpaulo uint32_t station_flags; 6013286441Srpaulo uint32_t station_flags_msk; 6014286441Srpaulo uint8_t add_immediate_ba_tid; 6015286441Srpaulo uint8_t remove_immediate_ba_tid; 6016286441Srpaulo uint16_t add_immediate_ba_ssn; 6017286441Srpaulo uint16_t sleep_tx_count; 6018286441Srpaulo uint16_t sleep_state_flags; 6019286441Srpaulo uint16_t assoc_id; 6020286441Srpaulo uint16_t beamform_flags; 6021286441Srpaulo uint32_t tfd_queue_msk; 6022303628Ssbruno} __packed; /* ADD_STA_CMD_API_S_VER_7 */ 6023286441Srpaulo 6024286441Srpaulo/** 6025286441Srpaulo * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 6026286441Srpaulo * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 6027286441Srpaulo * @sta_id: index of station in uCode's station table 6028286441Srpaulo * @key_offset: key offset in key storage 6029286441Srpaulo * @key_flags: type %iwm_sta_key_flag 6030286441Srpaulo * @key: key material data 6031286441Srpaulo * @key2: key material data 6032286441Srpaulo * @rx_secur_seq_cnt: RX security sequence counter for the key 6033286441Srpaulo * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6034286441Srpaulo * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6035286441Srpaulo */ 6036286441Srpaulostruct iwm_mvm_add_sta_key_cmd { 6037286441Srpaulo uint8_t sta_id; 6038286441Srpaulo uint8_t key_offset; 6039286441Srpaulo uint16_t key_flags; 6040286441Srpaulo uint8_t key[16]; 6041286441Srpaulo uint8_t key2[16]; 6042286441Srpaulo uint8_t rx_secur_seq_cnt[16]; 6043286441Srpaulo uint8_t tkip_rx_tsc_byte2; 6044286441Srpaulo uint8_t reserved; 6045286441Srpaulo uint16_t tkip_rx_ttak[5]; 6046286441Srpaulo} __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6047286441Srpaulo 6048286441Srpaulo/** 6049286441Srpaulo * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 6050286441Srpaulo * @IWM_ADD_STA_SUCCESS: operation was executed successfully 6051286441Srpaulo * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6052286441Srpaulo * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6053286441Srpaulo * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6054286441Srpaulo * that doesn't exist. 6055286441Srpaulo */ 6056286441Srpauloenum iwm_mvm_add_sta_rsp_status { 6057286441Srpaulo IWM_ADD_STA_SUCCESS = 0x1, 6058286441Srpaulo IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 6059286441Srpaulo IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 6060286441Srpaulo IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 6061286441Srpaulo}; 6062286441Srpaulo 6063286441Srpaulo/** 6064286441Srpaulo * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 6065286441Srpaulo * ( IWM_REMOVE_STA = 0x19 ) 6066286441Srpaulo * @sta_id: the station id of the station to be removed 6067286441Srpaulo */ 6068286441Srpaulostruct iwm_mvm_rm_sta_cmd { 6069286441Srpaulo uint8_t sta_id; 6070286441Srpaulo uint8_t reserved[3]; 6071286441Srpaulo} __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 6072286441Srpaulo 6073286441Srpaulo/** 6074286441Srpaulo * struct iwm_mvm_mgmt_mcast_key_cmd 6075286441Srpaulo * ( IWM_MGMT_MCAST_KEY = 0x1f ) 6076286441Srpaulo * @ctrl_flags: %iwm_sta_key_flag 6077286441Srpaulo * @IGTK: 6078286441Srpaulo * @K1: IGTK master key 6079286441Srpaulo * @K2: IGTK sub key 6080286441Srpaulo * @sta_id: station ID that support IGTK 6081286441Srpaulo * @key_id: 6082286441Srpaulo * @receive_seq_cnt: initial RSC/PN needed for replay check 6083286441Srpaulo */ 6084286441Srpaulostruct iwm_mvm_mgmt_mcast_key_cmd { 6085286441Srpaulo uint32_t ctrl_flags; 6086286441Srpaulo uint8_t IGTK[16]; 6087286441Srpaulo uint8_t K1[16]; 6088286441Srpaulo uint8_t K2[16]; 6089286441Srpaulo uint32_t key_id; 6090286441Srpaulo uint32_t sta_id; 6091286441Srpaulo uint64_t receive_seq_cnt; 6092286441Srpaulo} __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6093286441Srpaulo 6094286441Srpaulostruct iwm_mvm_wep_key { 6095286441Srpaulo uint8_t key_index; 6096286441Srpaulo uint8_t key_offset; 6097286441Srpaulo uint16_t reserved1; 6098286441Srpaulo uint8_t key_size; 6099286441Srpaulo uint8_t reserved2[3]; 6100286441Srpaulo uint8_t key[16]; 6101286441Srpaulo} __packed; 6102286441Srpaulo 6103286441Srpaulostruct iwm_mvm_wep_key_cmd { 6104286441Srpaulo uint32_t mac_id_n_color; 6105286441Srpaulo uint8_t num_keys; 6106286441Srpaulo uint8_t decryption_type; 6107286441Srpaulo uint8_t flags; 6108286441Srpaulo uint8_t reserved; 6109286441Srpaulo struct iwm_mvm_wep_key wep_key[0]; 6110286441Srpaulo} __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6111286441Srpaulo 6112286441Srpaulo/* 6113286441Srpaulo * END mvm/fw-api-sta.h 6114286441Srpaulo */ 6115286441Srpaulo 6116286441Srpaulo/* 6117303628Ssbruno * BT coex 6118303628Ssbruno */ 6119303628Ssbruno 6120303628Ssbrunoenum iwm_bt_coex_mode { 6121303628Ssbruno IWM_BT_COEX_DISABLE = 0x0, 6122303628Ssbruno IWM_BT_COEX_NW = 0x1, 6123303628Ssbruno IWM_BT_COEX_BT = 0x2, 6124303628Ssbruno IWM_BT_COEX_WIFI = 0x3, 6125303628Ssbruno}; /* BT_COEX_MODES_E */ 6126303628Ssbruno 6127303628Ssbrunoenum iwm_bt_coex_enabled_modules { 6128303628Ssbruno IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 6129303628Ssbruno IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 6130303628Ssbruno IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 6131303628Ssbruno IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 6132303628Ssbruno IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 6133303628Ssbruno}; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6134303628Ssbruno 6135303628Ssbruno/** 6136303628Ssbruno * struct iwm_bt_coex_cmd - bt coex configuration command 6137303628Ssbruno * @mode: enum %iwm_bt_coex_mode 6138303628Ssbruno * @enabled_modules: enum %iwm_bt_coex_enabled_modules 6139303628Ssbruno * 6140303628Ssbruno * The structure is used for the BT_COEX command. 6141303628Ssbruno */ 6142303628Ssbrunostruct iwm_bt_coex_cmd { 6143303628Ssbruno uint32_t mode; 6144303628Ssbruno uint32_t enabled_modules; 6145303628Ssbruno} __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6146303628Ssbruno 6147303628Ssbruno 6148303628Ssbruno/* 6149303628Ssbruno * Location Aware Regulatory (LAR) API - MCC updates 6150303628Ssbruno */ 6151303628Ssbruno 6152303628Ssbruno/** 6153303628Ssbruno * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 6154303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 6155303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6156303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6157303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 6158303628Ssbruno * @mcc: given mobile country code 6159303628Ssbruno * @source_id: the source from where we got the MCC, see iwm_mcc_source 6160303628Ssbruno * @reserved: reserved for alignment 6161303628Ssbruno */ 6162303628Ssbrunostruct iwm_mcc_update_cmd_v1 { 6163303628Ssbruno uint16_t mcc; 6164303628Ssbruno uint8_t source_id; 6165303628Ssbruno uint8_t reserved; 6166303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 6167303628Ssbruno 6168303628Ssbruno/** 6169303628Ssbruno * struct iwm_mcc_update_cmd - Request the device to update geographic 6170303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 6171303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6172303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6173303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 6174303628Ssbruno * @mcc: given mobile country code 6175303628Ssbruno * @source_id: the source from where we got the MCC, see iwm_mcc_source 6176303628Ssbruno * @reserved: reserved for alignment 6177303628Ssbruno * @key: integrity key for MCC API OEM testing 6178303628Ssbruno * @reserved2: reserved 6179303628Ssbruno */ 6180303628Ssbrunostruct iwm_mcc_update_cmd { 6181303628Ssbruno uint16_t mcc; 6182303628Ssbruno uint8_t source_id; 6183303628Ssbruno uint8_t reserved; 6184303628Ssbruno uint32_t key; 6185303628Ssbruno uint32_t reserved2[5]; 6186303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6187303628Ssbruno 6188303628Ssbruno/** 6189303628Ssbruno * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 6190303628Ssbruno * Contains the new channel control profile map, if changed, and the new MCC 6191303628Ssbruno * (mobile country code). 6192303628Ssbruno * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6193303628Ssbruno * @status: see &enum iwm_mcc_update_status 6194303628Ssbruno * @mcc: the new applied MCC 6195303628Ssbruno * @cap: capabilities for all channels which matches the MCC 6196303628Ssbruno * @source_id: the MCC source, see iwm_mcc_source 6197303628Ssbruno * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6198303628Ssbruno * channels, depending on platform) 6199303628Ssbruno * @channels: channel control data map, DWORD for each channel. Only the first 6200303628Ssbruno * 16bits are used. 6201303628Ssbruno */ 6202303628Ssbrunostruct iwm_mcc_update_resp_v1 { 6203303628Ssbruno uint32_t status; 6204303628Ssbruno uint16_t mcc; 6205303628Ssbruno uint8_t cap; 6206303628Ssbruno uint8_t source_id; 6207303628Ssbruno uint32_t n_channels; 6208303628Ssbruno uint32_t channels[0]; 6209303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 6210303628Ssbruno 6211303628Ssbruno/** 6212303628Ssbruno * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 6213303628Ssbruno * Contains the new channel control profile map, if changed, and the new MCC 6214303628Ssbruno * (mobile country code). 6215303628Ssbruno * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6216303628Ssbruno * @status: see &enum iwm_mcc_update_status 6217303628Ssbruno * @mcc: the new applied MCC 6218303628Ssbruno * @cap: capabilities for all channels which matches the MCC 6219303628Ssbruno * @source_id: the MCC source, see iwm_mcc_source 6220303628Ssbruno * @time: time elapsed from the MCC test start (in 30 seconds TU) 6221303628Ssbruno * @reserved: reserved. 6222303628Ssbruno * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6223303628Ssbruno * channels, depending on platform) 6224303628Ssbruno * @channels: channel control data map, DWORD for each channel. Only the first 6225303628Ssbruno * 16bits are used. 6226303628Ssbruno */ 6227303628Ssbrunostruct iwm_mcc_update_resp { 6228303628Ssbruno uint32_t status; 6229303628Ssbruno uint16_t mcc; 6230303628Ssbruno uint8_t cap; 6231303628Ssbruno uint8_t source_id; 6232303628Ssbruno uint16_t time; 6233303628Ssbruno uint16_t reserved; 6234303628Ssbruno uint32_t n_channels; 6235303628Ssbruno uint32_t channels[0]; 6236303628Ssbruno} __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 6237303628Ssbruno 6238303628Ssbruno/** 6239303628Ssbruno * struct iwm_mcc_chub_notif - chub notifies of mcc change 6240303628Ssbruno * (MCC_CHUB_UPDATE_CMD = 0xc9) 6241303628Ssbruno * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6242303628Ssbruno * the cellular and connectivity cores that gets updates of the mcc, and 6243303628Ssbruno * notifies the ucode directly of any mcc change. 6244303628Ssbruno * The ucode requests the driver to request the device to update geographic 6245303628Ssbruno * regulatory profile according to the given MCC (Mobile Country Code). 6246303628Ssbruno * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6247303628Ssbruno * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6248303628Ssbruno * MCC in the cmd response will be the relevant MCC in the NVM. 6249303628Ssbruno * @mcc: given mobile country code 6250303628Ssbruno * @source_id: identity of the change originator, see iwm_mcc_source 6251303628Ssbruno * @reserved1: reserved for alignment 6252303628Ssbruno */ 6253303628Ssbrunostruct iwm_mcc_chub_notif { 6254303628Ssbruno uint16_t mcc; 6255303628Ssbruno uint8_t source_id; 6256303628Ssbruno uint8_t reserved1; 6257303628Ssbruno} __packed; /* LAR_MCC_NOTIFY_S */ 6258303628Ssbruno 6259303628Ssbrunoenum iwm_mcc_update_status { 6260303628Ssbruno IWM_MCC_RESP_NEW_CHAN_PROFILE, 6261303628Ssbruno IWM_MCC_RESP_SAME_CHAN_PROFILE, 6262303628Ssbruno IWM_MCC_RESP_INVALID, 6263303628Ssbruno IWM_MCC_RESP_NVM_DISABLED, 6264303628Ssbruno IWM_MCC_RESP_ILLEGAL, 6265303628Ssbruno IWM_MCC_RESP_LOW_PRIORITY, 6266303628Ssbruno IWM_MCC_RESP_TEST_MODE_ACTIVE, 6267303628Ssbruno IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 6268303628Ssbruno IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 6269303628Ssbruno}; 6270303628Ssbruno 6271303628Ssbrunoenum iwm_mcc_source { 6272303628Ssbruno IWM_MCC_SOURCE_OLD_FW = 0, 6273303628Ssbruno IWM_MCC_SOURCE_ME = 1, 6274303628Ssbruno IWM_MCC_SOURCE_BIOS = 2, 6275303628Ssbruno IWM_MCC_SOURCE_3G_LTE_HOST = 3, 6276303628Ssbruno IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 6277303628Ssbruno IWM_MCC_SOURCE_WIFI = 5, 6278303628Ssbruno IWM_MCC_SOURCE_RESERVED = 6, 6279303628Ssbruno IWM_MCC_SOURCE_DEFAULT = 7, 6280303628Ssbruno IWM_MCC_SOURCE_UNINITIALIZED = 8, 6281303628Ssbruno IWM_MCC_SOURCE_MCC_API = 9, 6282303628Ssbruno IWM_MCC_SOURCE_GET_CURRENT = 0x10, 6283303628Ssbruno IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 6284303628Ssbruno}; 6285303628Ssbruno 6286303628Ssbruno/* 6287286441Srpaulo * Some cherry-picked definitions 6288286441Srpaulo */ 6289286441Srpaulo 6290286441Srpaulo#define IWM_FRAME_LIMIT 64 6291286441Srpaulo 6292303628Ssbruno/* 6293303628Ssbruno * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6294303628Ssbruno * As the firmware is slowly running out of command IDs and grouping of 6295303628Ssbruno * commands is desirable anyway, the firmware is extending the command 6296303628Ssbruno * header from 4 bytes to 8 bytes to introduce a group (in place of the 6297303628Ssbruno * former flags field, since that's always 0 on commands and thus can 6298303628Ssbruno * be easily used to distinguish between the two). 6299303628Ssbruno * 6300303628Ssbruno * These functions retrieve specific information from the id field in 6301303628Ssbruno * the iwm_host_cmd struct which contains the command id, the group id, 6302303628Ssbruno * and the version of the command. 6303303628Ssbruno*/ 6304303628Ssbrunostatic inline uint8_t 6305303628Ssbrunoiwm_cmd_opcode(uint32_t cmdid) 6306303628Ssbruno{ 6307303628Ssbruno return cmdid & 0xff; 6308303628Ssbruno} 6309303628Ssbruno 6310303628Ssbrunostatic inline uint8_t 6311303628Ssbrunoiwm_cmd_groupid(uint32_t cmdid) 6312303628Ssbruno{ 6313303628Ssbruno return ((cmdid & 0Xff00) >> 8); 6314303628Ssbruno} 6315303628Ssbruno 6316303628Ssbrunostatic inline uint8_t 6317303628Ssbrunoiwm_cmd_version(uint32_t cmdid) 6318303628Ssbruno{ 6319303628Ssbruno return ((cmdid & 0xff0000) >> 16); 6320303628Ssbruno} 6321303628Ssbruno 6322303628Ssbrunostatic inline uint32_t 6323303628Ssbrunoiwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6324303628Ssbruno{ 6325303628Ssbruno return opcode + (groupid << 8) + (version << 16); 6326303628Ssbruno} 6327303628Ssbruno 6328303628Ssbruno/* make uint16_t wide id out of uint8_t group and opcode */ 6329303628Ssbruno#define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6330303628Ssbruno 6331303628Ssbruno/* due to the conversion, this group is special */ 6332303628Ssbruno#define IWM_ALWAYS_LONG_GROUP 1 6333303628Ssbruno 6334286441Srpaulostruct iwm_cmd_header { 6335286441Srpaulo uint8_t code; 6336286441Srpaulo uint8_t flags; 6337286441Srpaulo uint8_t idx; 6338286441Srpaulo uint8_t qid; 6339286441Srpaulo} __packed; 6340286441Srpaulo 6341303628Ssbrunostruct iwm_cmd_header_wide { 6342303628Ssbruno uint8_t opcode; 6343303628Ssbruno uint8_t group_id; 6344303628Ssbruno uint8_t idx; 6345303628Ssbruno uint8_t qid; 6346303628Ssbruno uint16_t length; 6347303628Ssbruno uint8_t reserved; 6348303628Ssbruno uint8_t version; 6349303628Ssbruno} __packed; 6350303628Ssbruno 6351286441Srpauloenum iwm_power_scheme { 6352286441Srpaulo IWM_POWER_SCHEME_CAM = 1, 6353286441Srpaulo IWM_POWER_SCHEME_BPS, 6354286441Srpaulo IWM_POWER_SCHEME_LP 6355286441Srpaulo}; 6356286441Srpaulo 6357286441Srpaulo#define IWM_DEF_CMD_PAYLOAD_SIZE 320 6358301189Sadrian#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6359286441Srpaulo#define IWM_CMD_FAILED_MSK 0x40 6360286441Srpaulo 6361303628Ssbruno/** 6362303628Ssbruno * struct iwm_device_cmd 6363303628Ssbruno * 6364303628Ssbruno * For allocation of the command and tx queues, this establishes the overall 6365303628Ssbruno * size of the largest command we send to uCode, except for commands that 6366303628Ssbruno * aren't fully copied and use other TFD space. 6367303628Ssbruno */ 6368286441Srpaulostruct iwm_device_cmd { 6369303628Ssbruno union { 6370303628Ssbruno struct { 6371303628Ssbruno struct iwm_cmd_header hdr; 6372303628Ssbruno uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6373303628Ssbruno }; 6374303628Ssbruno struct { 6375303628Ssbruno struct iwm_cmd_header_wide hdr_wide; 6376303628Ssbruno uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6377303628Ssbruno sizeof(struct iwm_cmd_header_wide) + 6378303628Ssbruno sizeof(struct iwm_cmd_header)]; 6379303628Ssbruno }; 6380303628Ssbruno }; 6381286441Srpaulo} __packed; 6382286441Srpaulo 6383286441Srpaulostruct iwm_rx_packet { 6384286441Srpaulo /* 6385286441Srpaulo * The first 4 bytes of the RX frame header contain both the RX frame 6386286441Srpaulo * size and some flags. 6387286441Srpaulo * Bit fields: 6388286441Srpaulo * 31: flag flush RB request 6389286441Srpaulo * 30: flag ignore TC (terminal counter) request 6390286441Srpaulo * 29: flag fast IRQ request 6391286441Srpaulo * 28-14: Reserved 6392286441Srpaulo * 13-00: RX frame size 6393286441Srpaulo */ 6394286441Srpaulo uint32_t len_n_flags; 6395286441Srpaulo struct iwm_cmd_header hdr; 6396286441Srpaulo uint8_t data[]; 6397286441Srpaulo} __packed; 6398286441Srpaulo 6399286441Srpaulo#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6400286441Srpaulo 6401286441Srpaulostatic inline uint32_t 6402286441Srpauloiwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6403286441Srpaulo{ 6404286441Srpaulo 6405286441Srpaulo return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6406286441Srpaulo} 6407286441Srpaulo 6408286441Srpaulostatic inline uint32_t 6409286441Srpauloiwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6410286441Srpaulo{ 6411286441Srpaulo 6412286441Srpaulo return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6413286441Srpaulo} 6414286441Srpaulo 6415286441Srpaulo 6416286441Srpaulo#define IWM_MIN_DBM -100 6417286441Srpaulo#define IWM_MAX_DBM -33 /* realistic guess */ 6418286441Srpaulo 6419286441Srpaulo#define IWM_READ(sc, reg) \ 6420286441Srpaulo bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6421286441Srpaulo 6422286441Srpaulo#define IWM_WRITE(sc, reg, val) \ 6423286441Srpaulo bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6424286441Srpaulo 6425286441Srpaulo#define IWM_WRITE_1(sc, reg, val) \ 6426286441Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6427286441Srpaulo 6428286441Srpaulo#define IWM_SETBITS(sc, reg, mask) \ 6429286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6430286441Srpaulo 6431286441Srpaulo#define IWM_CLRBITS(sc, reg, mask) \ 6432286441Srpaulo IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6433286441Srpaulo 6434286441Srpaulo#define IWM_BARRIER_WRITE(sc) \ 6435286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6436286441Srpaulo BUS_SPACE_BARRIER_WRITE) 6437286441Srpaulo 6438286441Srpaulo#define IWM_BARRIER_READ_WRITE(sc) \ 6439286441Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6440286441Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6441286441Srpaulo 6442286441Srpaulo#endif /* __IF_IWM_REG_H__ */ 6443