1287117Scem/*- 2287117Scem * Copyright (C) 2012 Intel Corporation 3287117Scem * All rights reserved. 4287117Scem * 5287117Scem * Redistribution and use in source and binary forms, with or without 6287117Scem * modification, are permitted provided that the following conditions 7287117Scem * are met: 8287117Scem * 1. Redistributions of source code must retain the above copyright 9287117Scem * notice, this list of conditions and the following disclaimer. 10287117Scem * 2. Redistributions in binary form must reproduce the above copyright 11287117Scem * notice, this list of conditions and the following disclaimer in the 12287117Scem * documentation and/or other materials provided with the distribution. 13287117Scem * 14287117Scem * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15287117Scem * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16287117Scem * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17287117Scem * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18287117Scem * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19287117Scem * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20287117Scem * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21287117Scem * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22287117Scem * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23287117Scem * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24287117Scem * SUCH DAMAGE. 25287117Scem */ 26287117Scem 27287117Scem__FBSDID("$FreeBSD: releng/11.0/sys/dev/ioat/ioat_hw.h 295603 2016-02-13 19:01:56Z cem $"); 28287117Scem 29287117Scem#ifndef __IOAT_HW_H__ 30287117Scem#define __IOAT_HW_H__ 31287117Scem 32287117Scem#define IOAT_MAX_CHANNELS 32 33287117Scem 34287117Scem#define IOAT_CHANCNT_OFFSET 0x00 35287117Scem 36287117Scem#define IOAT_XFERCAP_OFFSET 0x01 37289732Scem/* Only bits [4:0] are valid. */ 38289732Scem#define IOAT_XFERCAP_VALID_MASK 0x1f 39287117Scem 40287117Scem#define IOAT_GENCTRL_OFFSET 0x02 41287117Scem 42287117Scem#define IOAT_INTRCTRL_OFFSET 0x03 43287117Scem#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 44287117Scem 45287117Scem#define IOAT_ATTNSTATUS_OFFSET 0x04 46287117Scem 47287117Scem#define IOAT_CBVER_OFFSET 0x08 48287117Scem 49287117Scem#define IOAT_INTRDELAY_OFFSET 0x0C 50292228Scem#define IOAT_INTRDELAY_SUPPORTED (1 << 15) 51292228Scem/* Reserved. (1 << 14) */ 52292228Scem/* [13:0] is the coalesce period, in microseconds. */ 53292228Scem#define IOAT_INTRDELAY_US_MASK ((1 << 14) - 1) 54287117Scem 55287117Scem#define IOAT_CS_STATUS_OFFSET 0x0E 56287117Scem 57287117Scem#define IOAT_DMACAPABILITY_OFFSET 0x10 58290087Scem#define IOAT_DMACAP_PB (1 << 0) 59295603Scem#define IOAT_DMACAP_CRC (1 << 1) 60295603Scem#define IOAT_DMACAP_MARKER_SKIP (1 << 2) 61295603Scem#define IOAT_DMACAP_OLD_XOR (1 << 3) 62290087Scem#define IOAT_DMACAP_DCA (1 << 4) 63295603Scem#define IOAT_DMACAP_MOVECRC (1 << 5) 64290087Scem#define IOAT_DMACAP_BFILL (1 << 6) 65295603Scem#define IOAT_DMACAP_EXT_APIC (1 << 7) 66290087Scem#define IOAT_DMACAP_XOR (1 << 8) 67290087Scem#define IOAT_DMACAP_PQ (1 << 9) 68290087Scem#define IOAT_DMACAP_DMA_DIF (1 << 10) 69290087Scem#define IOAT_DMACAP_DWBES (1 << 13) 70290087Scem#define IOAT_DMACAP_RAID16SS (1 << 17) 71290087Scem#define IOAT_DMACAP_DMAMC (1 << 18) 72290087Scem#define IOAT_DMACAP_CTOS (1 << 19) 73287117Scem 74290087Scem#define IOAT_DMACAP_STR \ 75290087Scem "\20\24Completion_Timeout_Support\23DMA_with_Multicasting_Support" \ 76290087Scem "\22RAID_Super_descriptors\16Descriptor_Write_Back_Error_Support" \ 77295603Scem "\13DMA_with_DIF\12PQ\11XOR\10Extended_APIC_ID\07Block_Fill\06Move_CRC" \ 78295603Scem "\05DCA\04Old_XOR\03Marker_Skipping\02CRC\01Page_Break" 79290087Scem 80287117Scem/* DMA Channel Registers */ 81287117Scem#define IOAT_CHANCTRL_OFFSET 0x80 82287117Scem#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 83287117Scem#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 84287117Scem#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 85287117Scem#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 86287117Scem#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 87287117Scem#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 88287117Scem#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 89287117Scem#define IOAT_CHANCTRL_INT_REARM 0x0001 90287117Scem#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 91290229Scem IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 92290229Scem IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\ 93290229Scem IOAT_CHANCTRL_ERR_INT_EN) 94287117Scem 95287117Scem#define IOAT_CHANCMD_OFFSET 0x84 96287117Scem#define IOAT_CHANCMD_RESET 0x20 97287117Scem#define IOAT_CHANCMD_SUSPEND 0x04 98287117Scem 99287117Scem#define IOAT_DMACOUNT_OFFSET 0x86 100287117Scem 101287117Scem#define IOAT_CHANSTS_OFFSET_LOW 0x88 102287117Scem#define IOAT_CHANSTS_OFFSET_HIGH 0x8C 103287117Scem#define IOAT_CHANSTS_OFFSET 0x88 104287117Scem 105287117Scem#define IOAT_CHANSTS_STATUS 0x7ULL 106287117Scem#define IOAT_CHANSTS_ACTIVE 0x0 107287117Scem#define IOAT_CHANSTS_IDLE 0x1 108287117Scem#define IOAT_CHANSTS_SUSPENDED 0x2 109287117Scem#define IOAT_CHANSTS_HALTED 0x3 110290229Scem#define IOAT_CHANSTS_ARMED 0x4 111287117Scem 112287117Scem#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL 113287117Scem#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL 114287117Scem 115287117Scem#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) 116287117Scem 117287117Scem#define IOAT_CHAINADDR_OFFSET_LOW 0x90 118287117Scem#define IOAT_CHAINADDR_OFFSET_HIGH 0x94 119287117Scem 120287117Scem#define IOAT_CHANCMP_OFFSET_LOW 0x98 121287117Scem#define IOAT_CHANCMP_OFFSET_HIGH 0x9C 122287117Scem 123287117Scem#define IOAT_CHANERR_OFFSET 0xA8 124287117Scem 125289912Scem#define IOAT_CHANERR_XSADDERR (1 << 0) 126289912Scem#define IOAT_CHANERR_XDADDERR (1 << 1) 127289912Scem#define IOAT_CHANERR_NDADDERR (1 << 2) 128289912Scem#define IOAT_CHANERR_DERR (1 << 3) 129289912Scem#define IOAT_CHANERR_CHADDERR (1 << 4) 130289912Scem#define IOAT_CHANERR_CCMDERR (1 << 5) 131289912Scem#define IOAT_CHANERR_CUNCORERR (1 << 6) 132289912Scem#define IOAT_CHANERR_DUNCORERR (1 << 7) 133289912Scem#define IOAT_CHANERR_RDERR (1 << 8) 134289912Scem#define IOAT_CHANERR_WDERR (1 << 9) 135289912Scem#define IOAT_CHANERR_DCERR (1 << 10) 136289912Scem#define IOAT_CHANERR_DXSERR (1 << 11) 137289912Scem#define IOAT_CHANERR_CMPADDERR (1 << 12) 138289912Scem#define IOAT_CHANERR_INTCFGERR (1 << 13) 139289912Scem#define IOAT_CHANERR_SEDERR (1 << 14) 140289912Scem#define IOAT_CHANERR_UNAFFERR (1 << 15) 141289912Scem#define IOAT_CHANERR_CXPERR (1 << 16) 142289912Scem/* Reserved. (1 << 17) */ 143289912Scem#define IOAT_CHANERR_DCNTERR (1 << 18) 144289912Scem#define IOAT_CHANERR_DIFFERR (1 << 19) 145289912Scem#define IOAT_CHANERR_GTVERR (1 << 20) 146289912Scem#define IOAT_CHANERR_ATVERR (1 << 21) 147289912Scem#define IOAT_CHANERR_RTVERR (1 << 22) 148289912Scem#define IOAT_CHANERR_BBERR (1 << 23) 149289912Scem#define IOAT_CHANERR_RDIFFERR (1 << 24) 150289912Scem#define IOAT_CHANERR_RGTVERR (1 << 25) 151289912Scem#define IOAT_CHANERR_RATVERR (1 << 26) 152289912Scem#define IOAT_CHANERR_RRTVERR (1 << 27) 153289912Scem 154289983Scem#define IOAT_CHANERR_STR \ 155289983Scem "\20\34RRTVERR\33RATVERR\32RGTVERR\31RDIFFERR\30BBERR\27RTVERR\26ATVERR" \ 156289983Scem "\25GTVERR\24DIFFERR\23DCNTERR\21CXPERR\20UNAFFERR\17SEDERR\16INTCFGERR" \ 157289983Scem "\15CMPADDERR\14DXSERR\13DCERR\12WDERR\11RDERR\10DUNCORERR\07CUNCORERR" \ 158289983Scem "\06CCMDERR\05CHADDERR\04DERR\03NDADDERR\02XDADDERR\01XSADDERR" 159289983Scem 160289983Scem 161287117Scem#define IOAT_CFG_CHANERR_INT_OFFSET 0x180 162287117Scem#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184 163287117Scem 164287117Scem#define IOAT_MIN_ORDER 4 165287117Scem#define IOAT_MAX_ORDER 16 166287117Scem 167287117Scem#endif /* __IOAT_HW_H__ */ 168