iir_pci.c revision 158651
1/*- 2 * Copyright (c) 2000-03 ICP vortex GmbH 3 * Copyright (c) 2002-03 Intel Corporation 4 * Copyright (c) 2003 Adaptec Inc. 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#ident "$Id: iir_pci.c 1.2 2003/08/26 12:29:55 achim Exp $" 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/iir/iir_pci.c 158651 2006-05-16 14:37:58Z phk $"); 35 36/* 37 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 38 * 39 * Written by: Achim Leubner <achim.leubner@intel.com> 40 * Written by: Achim Leubner <achim_leubner@adaptec.com> 41 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 42 * 43 * TODO: 44 */ 45 46/* #include "opt_iir.h" */ 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/endian.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/module.h> 55#include <sys/bus.h> 56 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/rman.h> 60 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcivar.h> 63 64#include <cam/scsi/scsi_all.h> 65 66#include <dev/iir/iir.h> 67 68/* Mapping registers for various areas */ 69#define PCI_DPMEM PCIR_BAR(0) 70 71/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 72#define GDT_PCI_PRODUCT_FC 0x200 73 74/* PCI SRAM structure */ 75#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 76#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 77#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 78#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 79#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 80#define GDT_SRAM_SZ 0x40 81 82/* DPRAM PCI controllers */ 83#define GDT_DPR_IF 0x00 /* interface area */ 84#define GDT_6SR (0xff0 - GDT_SRAM_SZ) 85#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 86#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 87#define GDT_EVENT 0xff8 /* u_int8_t, release event */ 88#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 89#define GDT_DPRAM_SZ 0x1000 90 91/* PLX register structure (new PCI controllers) */ 92#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 93#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 94#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 95#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 96#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 97#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 98#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 99#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 100#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 101#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 102#define GDT_PLX_SZ 0x80 103 104/* DPRAM new PCI controllers */ 105#define GDT_IC 0x00 /* interface */ 106#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 107 /* SRAM structure */ 108#define GDT_PCINEW_SZ 0x4000 109 110/* i960 register structure (PCI MPR controllers) */ 111#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 112#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 113#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 114#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 115#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 116#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 117#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 118#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 119#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 120#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 121#define GDT_I960_SZ 0x1000 122 123/* DPRAM PCI MPR controllers */ 124#define GDT_I960R 0x00 /* 4KB i960 registers */ 125#define GDT_MPR_IC GDT_I960_SZ 126 /* i960 register area */ 127#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 128 /* DPRAM struct. */ 129#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 130 131static int iir_pci_probe(device_t dev); 132static int iir_pci_attach(device_t dev); 133 134void gdt_pci_enable_intr(struct gdt_softc *); 135 136void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 137u_int8_t gdt_mpr_get_status(struct gdt_softc *); 138void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 139void gdt_mpr_release_event(struct gdt_softc *); 140void gdt_mpr_set_sema0(struct gdt_softc *); 141int gdt_mpr_test_busy(struct gdt_softc *); 142 143static device_method_t iir_pci_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, iir_pci_probe), 146 DEVMETHOD(device_attach, iir_pci_attach), 147 { 0, 0} 148}; 149 150 151static driver_t iir_pci_driver = 152{ 153 "iir", 154 iir_pci_methods, 155 sizeof(struct gdt_softc) 156}; 157 158static devclass_t iir_devclass; 159 160DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 161 162static int 163iir_pci_probe(device_t dev) 164{ 165 if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 166 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 167 device_set_desc(dev, "Intel Integrated RAID Controller"); 168 return (BUS_PROBE_DEFAULT); 169 } 170 if (pci_get_vendor(dev) == GDT_VENDOR_ID && 171 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 172 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 173 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 174 device_set_desc(dev, "ICP Disk Array Controller"); 175 return (BUS_PROBE_DEFAULT); 176 } 177 return (ENXIO); 178} 179 180 181static int 182iir_pci_attach(device_t dev) 183{ 184 struct gdt_softc *gdt; 185 struct resource *io = NULL, *irq = NULL; 186 int retries, rid, error = 0; 187 void *ih; 188 u_int8_t protocol; 189 190 /* map DPMEM */ 191 rid = PCI_DPMEM; 192 io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 193 if (io == NULL) { 194 device_printf(dev, "can't allocate register resources\n"); 195 error = ENOMEM; 196 goto err; 197 } 198 199 /* get IRQ */ 200 rid = 0; 201 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 202 RF_ACTIVE | RF_SHAREABLE); 203 if (io == NULL) { 204 device_printf(dev, "can't find IRQ value\n"); 205 error = ENOMEM; 206 goto err; 207 } 208 209 gdt = device_get_softc(dev); 210 bzero(gdt, sizeof(struct gdt_softc)); 211 gdt->sc_init_level = 0; 212 gdt->sc_dpmemt = rman_get_bustag(io); 213 gdt->sc_dpmemh = rman_get_bushandle(io); 214 gdt->sc_dpmembase = rman_get_start(io); 215 gdt->sc_hanum = device_get_unit(dev); 216 gdt->sc_bus = pci_get_bus(dev); 217 gdt->sc_slot = pci_get_slot(dev); 218 gdt->sc_vendor = pci_get_vendor(dev); 219 gdt->sc_device = pci_get_device(dev); 220 gdt->sc_subdevice = pci_get_subdevice(dev); 221 gdt->sc_class = GDT_MPR; 222/* no FC ctr. 223 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 224 gdt->sc_class |= GDT_FC; 225*/ 226 227 /* initialize RP controller */ 228 /* check and reset interface area */ 229 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 230 htole32(GDT_MPR_MAGIC)); 231 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 232 htole32(GDT_MPR_MAGIC)) { 233 printf("cannot access DPMEM at 0x%jx (shadowed?)\n", 234 (uintmax_t)gdt->sc_dpmembase); 235 error = ENXIO; 236 goto err; 237 } 238 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 239 GDT_MPR_SZ >> 2); 240 241 /* Disable everything */ 242 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 243 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 244 GDT_EDOOR_EN) | 4); 245 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 246 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 247 0); 248 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 249 0); 250 251 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 252 htole32(gdt->sc_dpmembase)); 253 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 254 0xff); 255 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 256 257 DELAY(20); 258 retries = GDT_RETRIES; 259 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 260 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 261 if (--retries == 0) { 262 printf("DEINIT failed\n"); 263 error = ENXIO; 264 goto err; 265 } 266 DELAY(1); 267 } 268 269 protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 270 GDT_MPR_IC + GDT_S_INFO)); 271 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 272 0); 273 if (protocol != GDT_PROTOCOL_VERSION) { 274 printf("unsupported protocol %d\n", protocol); 275 error = ENXIO; 276 goto err; 277 } 278 279 /* special commnd to controller BIOS */ 280 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 281 htole32(0)); 282 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 283 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 284 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 285 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 286 htole32(1)); 287 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 288 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 289 htole32(0)); 290 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 291 0xfe); 292 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 293 294 DELAY(20); 295 retries = GDT_RETRIES; 296 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 297 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 298 if (--retries == 0) { 299 printf("initialization error\n"); 300 error = ENXIO; 301 goto err; 302 } 303 DELAY(1); 304 } 305 306 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 307 0); 308 309 gdt->sc_ic_all_size = GDT_MPR_SZ; 310 311 gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 312 gdt->sc_get_status = gdt_mpr_get_status; 313 gdt->sc_intr = gdt_mpr_intr; 314 gdt->sc_release_event = gdt_mpr_release_event; 315 gdt->sc_set_sema0 = gdt_mpr_set_sema0; 316 gdt->sc_test_busy = gdt_mpr_test_busy; 317 318 /* Allocate a dmatag representing the capabilities of this attachment */ 319 /* XXX Should be a child of the PCI bus dma tag */ 320 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 321 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 322 /*highaddr*/BUS_SPACE_MAXADDR, 323 /*filter*/NULL, /*filterarg*/NULL, 324 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 325 /*nsegments*/GDT_MAXSG, 326 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 327 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 328 /*lockarg*/&Giant, &gdt->sc_parent_dmat) != 0) { 329 error = ENXIO; 330 goto err; 331 } 332 gdt->sc_init_level++; 333 334 if (iir_init(gdt) != 0) { 335 iir_free(gdt); 336 error = ENXIO; 337 goto err; 338 } 339 340 /* Register with the XPT */ 341 iir_attach(gdt); 342 343 /* associate interrupt handler */ 344 if (bus_setup_intr( dev, irq, INTR_TYPE_CAM, 345 iir_intr, gdt, &ih )) { 346 device_printf(dev, "Unable to register interrupt handler\n"); 347 error = ENXIO; 348 goto err; 349 } 350 351 gdt_pci_enable_intr(gdt); 352 return (0); 353 354err: 355 if (irq) 356 bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 357/* 358 if (io) 359 bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 360*/ 361 return (error); 362} 363 364 365/* Enable interrupts */ 366void 367gdt_pci_enable_intr(struct gdt_softc *gdt) 368{ 369 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 370 371 switch(GDT_CLASS(gdt)) { 372 case GDT_MPR: 373 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 374 GDT_MPR_EDOOR, 0xff); 375 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 376 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 377 GDT_EDOOR_EN) & ~4); 378 break; 379 } 380} 381 382 383/* 384 * MPR PCI controller-specific functions 385 */ 386 387void 388gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb) 389{ 390 u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t)); 391 u_int16_t dp_offset = gdt->sc_cmd_off; 392 u_int16_t cmd_no = gdt->sc_cmd_cnt++; 393 394 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 395 396 gdt->sc_cmd_off += cp_count; 397 398 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 399 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 400 (u_int32_t *)gccb->gc_cmd, cp_count >> 2); 401 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 402 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 403 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 404 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 405 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 406 htole16(gccb->gc_service)); 407} 408 409u_int8_t 410gdt_mpr_get_status(struct gdt_softc *gdt) 411{ 412 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 413 414 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 415} 416 417void 418gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 419{ 420 int i; 421 422 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 423 424 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 425 426 if (ctx->istatus & 0x80) { /* error flag */ 427 ctx->istatus &= ~0x80; 428 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 429 gdt->sc_dpmemh, GDT_MPR_STATUS); 430 } else /* no error */ 431 ctx->cmd_status = GDT_S_OK; 432 433 ctx->info = 434 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 435 ctx->service = 436 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 437 ctx->info2 = 438 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 439 GDT_MPR_INFO + sizeof (u_int32_t)); 440 441 /* event string */ 442 if (ctx->istatus == GDT_ASYNCINDEX) { 443 if (ctx->service != GDT_SCREENSERVICE && 444 (gdt->sc_fw_vers & 0xff) >= 0x1a) { 445 gdt->sc_dvr.severity = 446 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 447 for (i = 0; i < 256; ++i) { 448 gdt->sc_dvr.event_string[i] = 449 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 450 GDT_EVT_BUF + i); 451 if (gdt->sc_dvr.event_string[i] == 0) 452 break; 453 } 454 } 455 } 456 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 457} 458 459void 460gdt_mpr_release_event(struct gdt_softc *gdt) 461{ 462 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 463 464 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 465} 466 467void 468gdt_mpr_set_sema0(struct gdt_softc *gdt) 469{ 470 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 471 472 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 473} 474 475int 476gdt_mpr_test_busy(struct gdt_softc *gdt) 477{ 478 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 479 480 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 481 GDT_MPR_SEMA0) & 1); 482} 483