iir_pci.c revision 114001
1/* $FreeBSD: head/sys/dev/iir/iir_pci.c 114001 2003-04-25 05:37:04Z scottl $ */ 2/* 3 * Copyright (c) 2000-01 Intel Corporation 4 * All Rights Reserved 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32/* 33 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 34 * 35 * Written by: Achim Leubner <achim.leubner@intel.com> 36 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 37 * 38 * TODO: 39 */ 40 41#ident "$Id: iir_pci.c 1.1 2001/05/22 20:14:12 achim Exp $" 42 43/* #include "opt_iir.h" */ 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/endian.h> 48#include <sys/kernel.h> 49#include <sys/module.h> 50#include <sys/bus.h> 51 52#include <machine/bus_memio.h> 53#include <machine/bus_pio.h> 54#include <machine/bus.h> 55#include <machine/resource.h> 56#include <machine/clock.h> 57#include <sys/rman.h> 58 59#include <pci/pcireg.h> 60#include <pci/pcivar.h> 61 62#include <cam/scsi/scsi_all.h> 63 64#include <dev/iir/iir.h> 65 66/* Mapping registers for various areas */ 67#define PCI_DPMEM PCIR_MAPS 68 69/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 70#define GDT_PCI_PRODUCT_FC 0x200 71 72/* PCI SRAM structure */ 73#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 74#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 75#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 76#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 77#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 78#define GDT_SRAM_SZ 0x40 79 80/* DPRAM PCI controllers */ 81#define GDT_DPR_IF 0x00 /* interface area */ 82#define GDT_6SR (0xff0 - GDT_SRAM_SZ) 83#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 84#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 85#define GDT_EVENT 0xff8 /* u_int8_t, release event */ 86#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 87#define GDT_DPRAM_SZ 0x1000 88 89/* PLX register structure (new PCI controllers) */ 90#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 91#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 92#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 93#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 94#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 95#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 96#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 97#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 98#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 99#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 100#define GDT_PLX_SZ 0x80 101 102/* DPRAM new PCI controllers */ 103#define GDT_IC 0x00 /* interface */ 104#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 105 /* SRAM structure */ 106#define GDT_PCINEW_SZ 0x4000 107 108/* i960 register structure (PCI MPR controllers) */ 109#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 110#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 111#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 112#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 113#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 114#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 115#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 116#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 117#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 118#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 119#define GDT_I960_SZ 0x1000 120 121/* DPRAM PCI MPR controllers */ 122#define GDT_I960R 0x00 /* 4KB i960 registers */ 123#define GDT_MPR_IC GDT_I960_SZ 124 /* i960 register area */ 125#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 126 /* DPRAM struct. */ 127#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 128 129static int iir_pci_probe(device_t dev); 130static int iir_pci_attach(device_t dev); 131 132void gdt_pci_enable_intr(struct gdt_softc *); 133 134void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 135u_int8_t gdt_mpr_get_status(struct gdt_softc *); 136void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 137void gdt_mpr_release_event(struct gdt_softc *); 138void gdt_mpr_set_sema0(struct gdt_softc *); 139int gdt_mpr_test_busy(struct gdt_softc *); 140 141static device_method_t iir_pci_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, iir_pci_probe), 144 DEVMETHOD(device_attach, iir_pci_attach), 145 { 0, 0} 146}; 147 148 149static driver_t iir_pci_driver = 150{ 151 "iir", 152 iir_pci_methods, 153 sizeof(struct gdt_softc) 154}; 155 156static devclass_t iir_devclass; 157 158DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 159 160static int 161iir_pci_probe(device_t dev) 162{ 163 if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 164 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 165 device_set_desc(dev, "Intel Integrated RAID Controller"); 166 return (0); 167 } 168 if (pci_get_vendor(dev) == GDT_VENDOR_ID && 169 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 170 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 171 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 172 device_set_desc(dev, "ICP Disk Array Controller"); 173 return (0); 174 } 175 return (ENXIO); 176} 177 178 179static int 180iir_pci_attach(device_t dev) 181{ 182 struct gdt_softc *gdt; 183 struct resource *io = NULL, *irq = NULL; 184 int retries, rid, error = 0; 185 void *ih; 186 u_int8_t protocol; 187 188 /* map DPMEM */ 189 rid = PCI_DPMEM; 190 io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE); 191 if (io == NULL) { 192 device_printf(dev, "can't allocate register resources\n"); 193 error = ENOMEM; 194 goto err; 195 } 196 197 /* get IRQ */ 198 rid = 0; 199 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 200 RF_ACTIVE | RF_SHAREABLE); 201 if (io == NULL) { 202 device_printf(dev, "can't find IRQ value\n"); 203 error = ENOMEM; 204 goto err; 205 } 206 207 gdt = device_get_softc(dev); 208 bzero(gdt, sizeof(struct gdt_softc)); 209 gdt->sc_init_level = 0; 210 gdt->sc_dpmemt = rman_get_bustag(io); 211 gdt->sc_dpmemh = rman_get_bushandle(io); 212 gdt->sc_dpmembase = rman_get_start(io); 213 gdt->sc_hanum = device_get_unit(dev); 214 gdt->sc_bus = pci_get_bus(dev); 215 gdt->sc_slot = pci_get_slot(dev); 216 gdt->sc_vendor = pci_get_vendor(dev); 217 gdt->sc_device = pci_get_device(dev); 218 gdt->sc_subdevice = pci_get_subdevice(dev); 219 gdt->sc_class = GDT_MPR; 220/* no FC ctr. 221 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 222 gdt->sc_class |= GDT_FC; 223*/ 224 225 /* initialize RP controller */ 226 /* check and reset interface area */ 227 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 228 htole32(GDT_MPR_MAGIC)); 229 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 230 htole32(GDT_MPR_MAGIC)) { 231 printf("cannot access DPMEM at 0x%jx (shadowed?)\n", 232 (uintmax_t)gdt->sc_dpmembase); 233 error = ENXIO; 234 goto err; 235 } 236 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 237 GDT_MPR_SZ >> 2); 238 239 /* Disable everything */ 240 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 241 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 242 GDT_EDOOR_EN) | 4); 243 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 244 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 245 0); 246 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 247 0); 248 249 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 250 htole32(gdt->sc_dpmembase)); 251 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 252 0xff); 253 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 254 255 DELAY(20); 256 retries = GDT_RETRIES; 257 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 258 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 259 if (--retries == 0) { 260 printf("DEINIT failed\n"); 261 error = ENXIO; 262 goto err; 263 } 264 DELAY(1); 265 } 266 267 protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 268 GDT_MPR_IC + GDT_S_INFO)); 269 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 270 0); 271 if (protocol != GDT_PROTOCOL_VERSION) { 272 printf("unsupported protocol %d\n", protocol); 273 error = ENXIO; 274 goto err; 275 } 276 277 /* special commnd to controller BIOS */ 278 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 279 htole32(0)); 280 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 281 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 282 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 283 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 284 htole32(1)); 285 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 286 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 287 htole32(0)); 288 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 289 0xfe); 290 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 291 292 DELAY(20); 293 retries = GDT_RETRIES; 294 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 295 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 296 if (--retries == 0) { 297 printf("initialization error\n"); 298 error = ENXIO; 299 goto err; 300 } 301 DELAY(1); 302 } 303 304 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 305 0); 306 307 gdt->sc_ic_all_size = GDT_MPR_SZ; 308 309 gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 310 gdt->sc_get_status = gdt_mpr_get_status; 311 gdt->sc_intr = gdt_mpr_intr; 312 gdt->sc_release_event = gdt_mpr_release_event; 313 gdt->sc_set_sema0 = gdt_mpr_set_sema0; 314 gdt->sc_test_busy = gdt_mpr_test_busy; 315 316 /* Allocate a dmatag representing the capabilities of this attachment */ 317 /* XXX Should be a child of the PCI bus dma tag */ 318 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 319 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 320 /*highaddr*/BUS_SPACE_MAXADDR, 321 /*filter*/NULL, /*filterarg*/NULL, 322 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 323 /*nsegments*/GDT_MAXSG, 324 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 325 /*flags*/0, &gdt->sc_parent_dmat) != 0) { 326 error = ENXIO; 327 goto err; 328 } 329 gdt->sc_init_level++; 330 331 if (iir_init(gdt) != 0) { 332 iir_free(gdt); 333 error = ENXIO; 334 goto err; 335 } 336 337 /* Register with the XPT */ 338 iir_attach(gdt); 339 340 /* associate interrupt handler */ 341 if (bus_setup_intr( dev, irq, INTR_TYPE_CAM, 342 iir_intr, gdt, &ih )) { 343 device_printf(dev, "Unable to register interrupt handler\n"); 344 error = ENXIO; 345 goto err; 346 } 347 348 gdt_pci_enable_intr(gdt); 349 return (0); 350 351err: 352 if (irq) 353 bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 354/* 355 if (io) 356 bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 357*/ 358 return (error); 359} 360 361 362/* Enable interrupts */ 363void 364gdt_pci_enable_intr(struct gdt_softc *gdt) 365{ 366 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 367 368 switch(GDT_CLASS(gdt)) { 369 case GDT_MPR: 370 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 371 GDT_MPR_EDOOR, 0xff); 372 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 373 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 374 GDT_EDOOR_EN) & ~4); 375 break; 376 } 377} 378 379 380/* 381 * MPR PCI controller-specific functions 382 */ 383 384void 385gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb) 386{ 387 u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t)); 388 u_int16_t dp_offset = gdt->sc_cmd_off; 389 u_int16_t cmd_no = gdt->sc_cmd_cnt++; 390 391 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 392 393 gdt->sc_cmd_off += cp_count; 394 395 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 396 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 397 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 398 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 399 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 400 htole16(ccb->gc_service)); 401 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 402 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 403 (u_int32_t *)gdt->sc_cmd, cp_count >> 2); 404} 405 406u_int8_t 407gdt_mpr_get_status(struct gdt_softc *gdt) 408{ 409 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 410 411 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 412} 413 414void 415gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 416{ 417 int i; 418 419 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 420 421 if (ctx->istatus & 0x80) { /* error flag */ 422 ctx->istatus &= ~0x80; 423 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 424 gdt->sc_dpmemh, GDT_MPR_STATUS); 425 } else /* no error */ 426 ctx->cmd_status = GDT_S_OK; 427 428 ctx->info = 429 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 430 ctx->service = 431 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 432 ctx->info2 = 433 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 434 GDT_MPR_INFO + sizeof (u_int32_t)); 435 436 /* event string */ 437 if (ctx->istatus == GDT_ASYNCINDEX) { 438 if (ctx->service != GDT_SCREENSERVICE && 439 (gdt->sc_fw_vers & 0xff) >= 0x1a) { 440 gdt->sc_dvr.severity = 441 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 442 for (i = 0; i < 256; ++i) { 443 gdt->sc_dvr.event_string[i] = 444 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 445 GDT_EVT_BUF + i); 446 if (gdt->sc_dvr.event_string[i] == 0) 447 break; 448 } 449 } 450 } 451 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 452 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 453} 454 455void 456gdt_mpr_release_event(struct gdt_softc *gdt) 457{ 458 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 459 460 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 461} 462 463void 464gdt_mpr_set_sema0(struct gdt_softc *gdt) 465{ 466 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 467 468 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 469} 470 471int 472gdt_mpr_test_busy(struct gdt_softc *gdt) 473{ 474 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 475 476 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 477 GDT_MPR_SEMA0) & 1); 478} 479