ichsmb_pci.c revision 66703
1 2/* 3 * ichsmb_pci.c 4 * 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * 8 * Subject to the following obligations and disclaimer of warranty, use and 9 * redistribution of this software, in source or object code forms, with or 10 * without modifications are expressly permitted by Whistle Communications; 11 * provided, however, that: 12 * 1. Any and all reproductions of the source or object code must include the 13 * copyright notice above and the following disclaimer of warranties; and 14 * 2. No rights are granted, in any manner or form, to use Whistle 15 * Communications, Inc. trademarks, including the mark "WHISTLE 16 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 17 * such appears in the above copyright notice or in the software. 18 * 19 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 20 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 21 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 22 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 24 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 25 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 26 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 27 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 28 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 29 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 30 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 35 * OF SUCH DAMAGE. 36 * 37 * Author: Archie Cobbs <archie@freebsd.org> 38 * 39 * $FreeBSD: head/sys/dev/ichsmb/ichsmb_pci.c 66703 2000-10-06 00:09:46Z archie $ 40 */ 41 42/* 43 * Support for the SMBus controller logical device which is part of the 44 * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips. 45 */ 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/kernel.h> 50#include <sys/errno.h> 51#include <sys/syslog.h> 52#include <sys/bus.h> 53 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57 58#include <pci/pcivar.h> 59#include <pci/pcireg.h> 60 61#include <dev/smbus/smbconf.h> 62 63#include <dev/ichsmb/ichsmb_var.h> 64#include <dev/ichsmb/ichsmb_reg.h> 65 66/* PCI unique identifiers */ 67#define ID_81801AA 0x24138086 68#define ID_81801AB 0x24238086 69#define ID_82801BA 0x24438086 70 71#define PCIS_SERIALBUS_SMBUS_PROGIF 0x00 72 73/* Internal functions */ 74static int ichsmb_pci_probe(device_t dev); 75static int ichsmb_pci_attach(device_t dev); 76 77/* Device methods */ 78static device_method_t ichsmb_pci_methods[] = { 79 /* Device interface */ 80 DEVMETHOD(device_probe, ichsmb_pci_probe), 81 DEVMETHOD(device_attach, ichsmb_pci_attach), 82 83 /* Bus methods */ 84 DEVMETHOD(bus_print_child, bus_generic_print_child), 85 86 /* SMBus methods */ 87 DEVMETHOD(smbus_callback, ichsmb_callback), 88 DEVMETHOD(smbus_quick, ichsmb_quick), 89 DEVMETHOD(smbus_sendb, ichsmb_sendb), 90 DEVMETHOD(smbus_recvb, ichsmb_recvb), 91 DEVMETHOD(smbus_writeb, ichsmb_writeb), 92 DEVMETHOD(smbus_writew, ichsmb_writew), 93 DEVMETHOD(smbus_readb, ichsmb_readb), 94 DEVMETHOD(smbus_readw, ichsmb_readw), 95 DEVMETHOD(smbus_pcall, ichsmb_pcall), 96 DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 97 DEVMETHOD(smbus_bread, ichsmb_bread), 98 { 0, 0 } 99}; 100 101static driver_t ichsmb_pci_driver = { 102 "ichsmb", 103 ichsmb_pci_methods, 104 sizeof(struct ichsmb_softc) 105}; 106 107static devclass_t ichsmb_pci_devclass; 108 109DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0); 110 111static int 112ichsmb_pci_probe(device_t dev) 113{ 114 /* Check PCI identifier */ 115 switch (pci_get_devid(dev)) { 116 case ID_81801AA: 117 device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller"); 118 break; 119 case ID_81801AB: 120 device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller"); 121 break; 122 case ID_82801BA: 123 device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller"); 124 break; 125 default: 126 if (pci_get_class(dev) == PCIC_SERIALBUS 127 && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS 128 && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) { 129 device_set_desc(dev, "SMBus controller"); 130 return (-2); /* XXX */ 131 } 132 return (ENXIO); 133 } 134 135 /* Done */ 136 return (ichsmb_probe(dev)); 137} 138 139static int 140ichsmb_pci_attach(device_t dev) 141{ 142 const sc_p sc = device_get_softc(dev); 143 u_int32_t cmd; 144 int error; 145 146 /* Initialize private state */ 147 bzero(sc, sizeof(*sc)); 148 sc->ich_cmd = -1; 149 sc->dev = dev; 150 151 /* Allocate an I/O range */ 152 sc->io_rid = ICH_SMB_BASE; 153 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 154 &sc->io_rid, 0, ~0, 16, RF_ACTIVE); 155 if (sc->io_res == NULL) { 156 log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev)); 157 error = ENXIO; 158 goto fail; 159 } 160 sc->io_bst = rman_get_bustag(sc->io_res); 161 sc->io_bsh = rman_get_bushandle(sc->io_res); 162 163 /* Allocate interrupt */ 164 sc->irq_rid = 0; 165 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, 166 &sc->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 167 if (sc->irq_res == NULL) { 168 log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev)); 169 error = ENXIO; 170 goto fail; 171 } 172 173 /* Set up interrupt handler */ 174 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 175 ichsmb_device_intr, sc, &sc->irq_handle); 176 if (error != 0) { 177 log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev)); 178 goto fail; 179 } 180 181 /* Enable I/O mapping */ 182 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 183 cmd |= PCIM_CMD_PORTEN; 184 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 185 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 186 if ((cmd & PCIM_CMD_PORTEN) == 0) { 187 log(LOG_ERR, "%s: can't enable memory map\n", 188 device_get_nameunit(dev)); 189 error = ENXIO; 190 goto fail; 191 } 192 193 /* Enable device */ 194 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 195 196 /* Done */ 197 return (ichsmb_attach(dev)); 198 199fail: 200 /* Attach failed, release resources */ 201 ichsmb_release_resources(sc); 202 return (error); 203} 204 205