ichsmb_pci.c revision 131070
1/*- 2 * ichsmb_pci.c 3 * 4 * Author: Archie Cobbs <archie@freebsd.org> 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * Author: Archie Cobbs <archie@freebsd.org> 8 * 9 * Subject to the following obligations and disclaimer of warranty, use and 10 * redistribution of this software, in source or object code forms, with or 11 * without modifications are expressly permitted by Whistle Communications; 12 * provided, however, that: 13 * 1. Any and all reproductions of the source or object code must include the 14 * copyright notice above and the following disclaimer of warranties; and 15 * 2. No rights are granted, in any manner or form, to use Whistle 16 * Communications, Inc. trademarks, including the mark "WHISTLE 17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 18 * such appears in the above copyright notice or in the software. 19 * 20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 36 * OF SUCH DAMAGE. 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: head/sys/dev/ichsmb/ichsmb_pci.c 131070 2004-06-24 18:21:28Z ambrisko $"); 41 42/* 43 * Support for the SMBus controller logical device which is part of the 44 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips. 45 */ 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/errno.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/syslog.h> 55#include <sys/bus.h> 56 57#include <machine/bus.h> 58#include <sys/rman.h> 59#include <machine/resource.h> 60 61#include <dev/pci/pcivar.h> 62#include <dev/pci/pcireg.h> 63 64#include <dev/smbus/smbconf.h> 65 66#include <dev/ichsmb/ichsmb_var.h> 67#include <dev/ichsmb/ichsmb_reg.h> 68 69/* PCI unique identifiers */ 70#define ID_82801AA 0x24138086 71#define ID_82801AB 0x24238086 72#define ID_82801BA 0x24438086 73#define ID_82801CA 0x24838086 74#define ID_82801DC 0x24C38086 75#define ID_82801EB 0x24D38086 76#define ID_6300ESB 0x25a48086 77 78#define PCIS_SERIALBUS_SMBUS_PROGIF 0x00 79 80/* Internal functions */ 81static int ichsmb_pci_probe(device_t dev); 82static int ichsmb_pci_attach(device_t dev); 83 84/* Device methods */ 85static device_method_t ichsmb_pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, ichsmb_pci_probe), 88 DEVMETHOD(device_attach, ichsmb_pci_attach), 89 90 /* Bus methods */ 91 DEVMETHOD(bus_print_child, bus_generic_print_child), 92 93 /* SMBus methods */ 94 DEVMETHOD(smbus_callback, ichsmb_callback), 95 DEVMETHOD(smbus_quick, ichsmb_quick), 96 DEVMETHOD(smbus_sendb, ichsmb_sendb), 97 DEVMETHOD(smbus_recvb, ichsmb_recvb), 98 DEVMETHOD(smbus_writeb, ichsmb_writeb), 99 DEVMETHOD(smbus_writew, ichsmb_writew), 100 DEVMETHOD(smbus_readb, ichsmb_readb), 101 DEVMETHOD(smbus_readw, ichsmb_readw), 102 DEVMETHOD(smbus_pcall, ichsmb_pcall), 103 DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 104 DEVMETHOD(smbus_bread, ichsmb_bread), 105 { 0, 0 } 106}; 107 108static driver_t ichsmb_pci_driver = { 109 "ichsmb", 110 ichsmb_pci_methods, 111 sizeof(struct ichsmb_softc) 112}; 113 114static devclass_t ichsmb_pci_devclass; 115 116DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0); 117 118static int 119ichsmb_pci_probe(device_t dev) 120{ 121 /* Check PCI identifier */ 122 switch (pci_get_devid(dev)) { 123 case ID_82801AA: 124 device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller"); 125 break; 126 case ID_82801AB: 127 device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller"); 128 break; 129 case ID_82801BA: 130 device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller"); 131 break; 132 case ID_82801CA: 133 device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller"); 134 break; 135 case ID_82801DC: 136 device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller"); 137 break; 138 case ID_82801EB: 139 device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller"); 140 break; 141 case ID_6300ESB: 142 device_set_desc(dev, "Intel 6300ESB (ICH) SMBus controller"); 143 break; 144 default: 145 if (pci_get_class(dev) == PCIC_SERIALBUS 146 && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS 147 && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) { 148 device_set_desc(dev, "SMBus controller"); 149 return (-2); /* XXX */ 150 } 151 return (ENXIO); 152 } 153 154 /* Done */ 155 return (ichsmb_probe(dev)); 156} 157 158static int 159ichsmb_pci_attach(device_t dev) 160{ 161 const sc_p sc = device_get_softc(dev); 162 u_int32_t cmd; 163 int error; 164 165 /* Initialize private state */ 166 bzero(sc, sizeof(*sc)); 167 sc->ich_cmd = -1; 168 sc->dev = dev; 169 170 /* Allocate an I/O range */ 171 sc->io_rid = ICH_SMB_BASE; 172 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 173 &sc->io_rid, 0, ~0, 16, RF_ACTIVE); 174 if (sc->io_res == NULL) 175 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 176 &sc->io_rid, 0, ~0, 32, RF_ACTIVE); 177 if (sc->io_res == NULL) { 178 log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev)); 179 error = ENXIO; 180 goto fail; 181 } 182 sc->io_bst = rman_get_bustag(sc->io_res); 183 sc->io_bsh = rman_get_bushandle(sc->io_res); 184 185 /* Allocate interrupt */ 186 sc->irq_rid = 0; 187 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 188 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE); 189 if (sc->irq_res == NULL) { 190 log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev)); 191 error = ENXIO; 192 goto fail; 193 } 194 195 /* Set up interrupt handler */ 196 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 197 ichsmb_device_intr, sc, &sc->irq_handle); 198 if (error != 0) { 199 log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev)); 200 goto fail; 201 } 202 203 /* Enable I/O mapping */ 204 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 205 cmd |= PCIM_CMD_PORTEN; 206 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 207 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 208 if ((cmd & PCIM_CMD_PORTEN) == 0) { 209 log(LOG_ERR, "%s: can't enable memory map\n", 210 device_get_nameunit(dev)); 211 error = ENXIO; 212 goto fail; 213 } 214 215 /* Enable device */ 216 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 217 218 /* Done */ 219 return (ichsmb_attach(dev)); 220 221fail: 222 /* Attach failed, release resources */ 223 ichsmb_release_resources(sc); 224 return (error); 225} 226 227