1136849Sscottl/* 2149871Sscottl * Copyright (c) 2004-2005 MARVELL SEMICONDUCTOR ISRAEL, LTD. 3136849Sscottl * All rights reserved. 4136849Sscottl * 5136849Sscottl * Redistribution and use in source and binary forms, with or without 6136849Sscottl * modification, are permitted provided that the following conditions 7136849Sscottl * are met: 8136849Sscottl * 1. Redistributions of source code must retain the above copyright 9136849Sscottl * notice, this list of conditions and the following disclaimer. 10136849Sscottl * 2. Redistributions in binary form must reproduce the above copyright 11136849Sscottl * notice, this list of conditions and the following disclaimer in the 12136849Sscottl * documentation and/or other materials provided with the distribution. 13136849Sscottl * 14136849Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15136849Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16136849Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17136849Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18136849Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19136849Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20136849Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21136849Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22136849Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23136849Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24136849Sscottl * SUCH DAMAGE. 25142988Sscottl * 26142988Sscottl * $FreeBSD: releng/11.0/sys/dev/hptmv/mvSata.h 190809 2009-04-07 16:38:25Z delphij $ 27136849Sscottl */ 28136849Sscottl#ifndef __INCmvSatah 29136849Sscottl#define __INCmvSatah 30136849Sscottl 31136849Sscottl#ifndef SUPPORT_MV_SATA_GEN_1 32136849Sscottl#define SUPPORT_MV_SATA_GEN_1 1 33136849Sscottl#endif 34136849Sscottl 35136849Sscottl#ifndef SUPPORT_MV_SATA_GEN_2 36136849Sscottl#define SUPPORT_MV_SATA_GEN_2 0 37136849Sscottl#endif 38136849Sscottl 39190809Sdelphij#ifndef SUPPORT_MV_SATA_GEN_2E 40190809Sdelphij#define SUPPORT_MV_SATA_GEN_2E 0 41190809Sdelphij#endif 42190809Sdelphij 43190809Sdelphij#if (SUPPORT_MV_SATA_GEN_1 + SUPPORT_MV_SATA_GEN_2 + SUPPORT_MV_SATA_GEN_2E) > 1 44190809Sdelphij 45136849Sscottl#define MV_SATA_GEN_1(x) ((x)->sataAdapterGeneration==1) 46190809Sdelphij#define MV_SATA_GEN_2(x) ((x)->sataAdapterGeneration>=2) 47190809Sdelphij#define MV_SATA_GEN_2E(x) ((x)->sataAdapterGeneration==3) 48190809Sdelphij 49136849Sscottl#elif SUPPORT_MV_SATA_GEN_1==1 50190809Sdelphij 51136849Sscottl#define MV_SATA_GEN_1(x) 1 52136849Sscottl#define MV_SATA_GEN_2(x) 0 53190809Sdelphij#define MV_SATA_GEN_2E(x) 0 54190809Sdelphij 55136849Sscottl#elif SUPPORT_MV_SATA_GEN_2==1 56190809Sdelphij 57136849Sscottl#define MV_SATA_GEN_1(x) 0 58136849Sscottl#define MV_SATA_GEN_2(x) 1 59190809Sdelphij#define MV_SATA_GEN_2E(x) 0 60190809Sdelphij 61190809Sdelphij#elif SUPPORT_MV_SATA_GEN_2E==1 62190809Sdelphij 63190809Sdelphij#define MV_SATA_GEN_1(x) 0 64190809Sdelphij#define MV_SATA_GEN_2(x) 1 /* gen2E impiles gen2 */ 65190809Sdelphij#define MV_SATA_GEN_2E(x) 1 66190809Sdelphij 67136849Sscottl#else 68136849Sscottl#error "Which IC do you support?" 69136849Sscottl#endif 70136849Sscottl 71136849Sscottl/* Definitions */ 72136849Sscottl/* MV88SX50XX specific defines */ 73136849Sscottl#define MV_SATA_VENDOR_ID 0x11AB 74136849Sscottl#define MV_SATA_DEVICE_ID_5080 0x5080 75136849Sscottl#define MV_SATA_DEVICE_ID_5081 0x5081 76136849Sscottl#define MV_SATA_DEVICE_ID_6080 0x6080 77136849Sscottl#define MV_SATA_DEVICE_ID_6081 0x6081 78190809Sdelphij 79190809Sdelphij#if defined(RR2310) || defined(RR1740) || defined(RR2210) || defined (RR2522) 80190809Sdelphij#define MV_SATA_CHANNELS_NUM 4 81190809Sdelphij#define MV_SATA_UNITS_NUM 1 82190809Sdelphij#else 83136849Sscottl#define MV_SATA_CHANNELS_NUM 8 84136849Sscottl#define MV_SATA_UNITS_NUM 2 85190809Sdelphij#endif 86190809Sdelphij 87136849Sscottl#define MV_SATA_PCI_BAR0_SPACE_SIZE (1<<18) /* 256 Kb*/ 88136849Sscottl 89136849Sscottl#define CHANNEL_QUEUE_LENGTH 32 90136849Sscottl#define CHANNEL_QUEUE_MASK 0x1F 91136849Sscottl 92136849Sscottl#define MV_EDMA_QUEUE_LENGTH 32 /* Up to 32 outstanding */ 93136849Sscottl /* commands per SATA channel*/ 94136849Sscottl#define MV_EDMA_QUEUE_MASK 0x1F 95136849Sscottl#define MV_EDMA_REQUEST_QUEUE_SIZE 1024 /* 32*32 = 1KBytes */ 96136849Sscottl#define MV_EDMA_RESPONSE_QUEUE_SIZE 256 /* 32*8 = 256 Bytes */ 97136849Sscottl 98136849Sscottl#define MV_EDMA_REQUEST_ENTRY_SIZE 32 99136849Sscottl#define MV_EDMA_RESPONSE_ENTRY_SIZE 8 100136849Sscottl 101136849Sscottl#define MV_EDMA_PRD_ENTRY_SIZE 16 /* 16Bytes*/ 102136849Sscottl#define MV_EDMA_PRD_NO_SNOOP_FLAG 0x00000001 /* MV_BIT0 */ 103136849Sscottl#define MV_EDMA_PRD_EOT_FLAG 0x00008000 /* MV_BIT15 */ 104136849Sscottl 105136849Sscottl#define MV_ATA_IDENTIFY_DEV_DATA_LENGTH 256 /* number of words(2 byte)*/ 106136849Sscottl#define MV_ATA_MODEL_NUMBER_LEN 40 107136849Sscottl#define ATA_SECTOR_SIZE 512 108136849Sscottl/* Log messages level defines */ 109136849Sscottl#define MV_DEBUG 0x1 110136849Sscottl#define MV_DEBUG_INIT 0x2 111136849Sscottl#define MV_DEBUG_INTERRUPTS 0x4 112136849Sscottl#define MV_DEBUG_SATA_LINK 0x8 113136849Sscottl#define MV_DEBUG_UDMA_COMMAND 0x10 114136849Sscottl#define MV_DEBUG_NON_UDMA_COMMAND 0x20 115136849Sscottl#define MV_DEBUG_ERROR 0x40 116136849Sscottl 117136849Sscottl 118136849Sscottl/* Typedefs */ 119136849Sscottltypedef enum mvUdmaType 120136849Sscottl{ 121136849Sscottl MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE 122136849Sscottl} MV_UDMA_TYPE; 123136849Sscottl 124136849Sscottltypedef enum mvFlushType 125136849Sscottl{ 126136849Sscottl MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE 127136849Sscottl} MV_FLUSH_TYPE; 128136849Sscottl 129136849Sscottltypedef enum mvCompletionType 130136849Sscottl{ 131136849Sscottl MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR, 132136849Sscottl MV_COMPLETION_TYPE_ABORT 133136849Sscottl} MV_COMPLETION_TYPE; 134136849Sscottl 135136849Sscottltypedef enum mvEventType 136136849Sscottl{ 137136849Sscottl MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE 138136849Sscottl} MV_EVENT_TYPE; 139136849Sscottl 140136849Sscottltypedef enum mvEdmaMode 141136849Sscottl{ 142136849Sscottl MV_EDMA_MODE_QUEUED, 143136849Sscottl MV_EDMA_MODE_NOT_QUEUED, 144136849Sscottl MV_EDMA_MODE_NATIVE_QUEUING 145136849Sscottl} MV_EDMA_MODE; 146136849Sscottl 147136849Sscottltypedef enum mvEdmaQueueResult 148136849Sscottl{ 149136849Sscottl MV_EDMA_QUEUE_RESULT_OK = 0, 150136849Sscottl MV_EDMA_QUEUE_RESULT_EDMA_DISABLED, 151136849Sscottl MV_EDMA_QUEUE_RESULT_FULL, 152136849Sscottl MV_EDMA_QUEUE_RESULT_BAD_LBA_ADDRESS, 153136849Sscottl MV_EDMA_QUEUE_RESULT_BAD_PARAMS 154136849Sscottl} MV_EDMA_QUEUE_RESULT; 155136849Sscottl 156136849Sscottltypedef enum mvQueueCommandResult 157136849Sscottl{ 158136849Sscottl MV_QUEUE_COMMAND_RESULT_OK = 0, 159136849Sscottl MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED, 160136849Sscottl MV_QUEUE_COMMAND_RESULT_FULL, 161136849Sscottl MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS, 162136849Sscottl MV_QUEUE_COMMAND_RESULT_BAD_PARAMS 163136849Sscottl} MV_QUEUE_COMMAND_RESULT; 164136849Sscottl 165136849Sscottltypedef enum mvNonUdmaProtocol 166136849Sscottl{ 167136849Sscottl MV_NON_UDMA_PROTOCOL_NON_DATA, 168136849Sscottl MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 169136849Sscottl MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT 170136849Sscottl} MV_NON_UDMA_PROTOCOL; 171136849Sscottl 172136849Sscottl 173136849Sscottlstruct mvDmaRequestQueueEntry; 174136849Sscottlstruct mvDmaResponseQueueEntry; 175136849Sscottlstruct mvDmaCommandEntry; 176136849Sscottl 177136849Sscottlstruct mvSataAdapter; 178136849Sscottlstruct mvStorageDevRegisters; 179136849Sscottl 180136849Sscottltypedef MV_BOOLEAN (* HPTLIBAPI mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *, 181136849Sscottl MV_U8, 182136849Sscottl MV_COMPLETION_TYPE, 183136849Sscottl MV_VOID_PTR, MV_U16, 184136849Sscottl MV_U32, 185190809Sdelphij struct mvStorageDevRegisters SS_SEG*); 186136849Sscottl 187136849Sscottltypedef enum mvQueuedCommandType 188136849Sscottl{ 189136849Sscottl MV_QUEUED_COMMAND_TYPE_UDMA, 190136849Sscottl MV_QUEUED_COMMAND_TYPE_NONE_UDMA 191136849Sscottl} MV_QUEUED_COMMAND_TYPE; 192136849Sscottl 193136849Sscottltypedef struct mvUdmaCommandParams 194136849Sscottl{ 195136849Sscottl MV_UDMA_TYPE readWrite; 196136849Sscottl MV_BOOLEAN isEXT; 197136849Sscottl MV_U32 lowLBAAddress; 198136849Sscottl MV_U16 highLBAAddress; 199136849Sscottl MV_U16 numOfSectors; 200136849Sscottl MV_U32 prdLowAddr; 201136849Sscottl MV_U32 prdHighAddr; 202136849Sscottl mvSataCommandCompletionCallBack_t callBack; 203136849Sscottl MV_VOID_PTR commandId; 204136849Sscottl} MV_UDMA_COMMAND_PARAMS; 205136849Sscottl 206136849Sscottltypedef struct mvNoneUdmaCommandParams 207136849Sscottl{ 208136849Sscottl MV_NON_UDMA_PROTOCOL protocolType; 209136849Sscottl MV_BOOLEAN isEXT; 210136849Sscottl MV_U16_PTR bufPtr; 211136849Sscottl MV_U32 count; 212136849Sscottl MV_U16 features; 213136849Sscottl MV_U16 sectorCount; 214136849Sscottl MV_U16 lbaLow; 215136849Sscottl MV_U16 lbaMid; 216136849Sscottl MV_U16 lbaHigh; 217136849Sscottl MV_U8 device; 218136849Sscottl MV_U8 command; 219136849Sscottl mvSataCommandCompletionCallBack_t callBack; 220136849Sscottl MV_VOID_PTR commandId; 221136849Sscottl} MV_NONE_UDMA_COMMAND_PARAMS; 222136849Sscottl 223136849Sscottltypedef struct mvQueueCommandInfo 224136849Sscottl{ 225136849Sscottl MV_QUEUED_COMMAND_TYPE type; 226136849Sscottl union 227136849Sscottl { 228136849Sscottl MV_UDMA_COMMAND_PARAMS udmaCommand; 229136849Sscottl MV_NONE_UDMA_COMMAND_PARAMS NoneUdmaCommand; 230136849Sscottl } commandParams; 231136849Sscottl} MV_QUEUE_COMMAND_INFO; 232136849Sscottl 233136849Sscottl/* The following structure is for the Core Driver internal usage */ 234136849Sscottltypedef struct mvQueuedCommandEntry 235136849Sscottl{ 236136849Sscottl MV_BOOLEAN isFreeEntry; 237136849Sscottl MV_U8 commandTag; 238136849Sscottl struct mvQueuedCommandEntry *next; 239136849Sscottl struct mvQueuedCommandEntry *prev; 240136849Sscottl MV_QUEUE_COMMAND_INFO commandInfo; 241136849Sscottl} MV_QUEUED_COMMAND_ENTRY; 242136849Sscottl 243136849Sscottl/* The following structures are part of the Core Driver API */ 244136849Sscottltypedef struct mvSataChannel 245136849Sscottl{ 246136849Sscottl /* Fields set by Intermediate Application Layer */ 247136849Sscottl MV_U8 channelNumber; 248136849Sscottl MV_BOOLEAN waitingForInterrupt; 249136849Sscottl MV_BOOLEAN lba48Address; 250136849Sscottl MV_BOOLEAN maxReadTransfer; 251190809Sdelphij struct mvDmaRequestQueueEntry SS_SEG *requestQueue; 252190809Sdelphij struct mvDmaResponseQueueEntry SS_SEG *responseQueue; 253136849Sscottl MV_U32 requestQueuePciHiAddress; 254136849Sscottl MV_U32 requestQueuePciLowAddress; 255136849Sscottl MV_U32 responseQueuePciHiAddress; 256136849Sscottl MV_U32 responseQueuePciLowAddress; 257136849Sscottl /* Fields set by CORE driver */ 258136849Sscottl struct mvSataAdapter *mvSataAdapter; 259136849Sscottl MV_OS_SEMAPHORE semaphore; 260136849Sscottl MV_U32 eDmaRegsOffset; 261136849Sscottl MV_U16 identifyDevice[MV_ATA_IDENTIFY_DEV_DATA_LENGTH]; 262136849Sscottl MV_BOOLEAN EdmaActive; 263136849Sscottl MV_EDMA_MODE queuedDMA; 264136849Sscottl MV_U8 outstandingCommands; 265136849Sscottl MV_BOOLEAN workAroundDone; 266136849Sscottl struct mvQueuedCommandEntry commandsQueue[CHANNEL_QUEUE_LENGTH]; 267136849Sscottl struct mvQueuedCommandEntry *commandsQueueHead; 268136849Sscottl struct mvQueuedCommandEntry *commandsQueueTail; 269136849Sscottl MV_BOOLEAN queueCommandsEnabled; 270136849Sscottl MV_U8 noneUdmaOutstandingCommands; 271136849Sscottl MV_U8 EdmaQueuedCommands; 272190809Sdelphij MV_U32 freeIDsStack[CHANNEL_QUEUE_LENGTH]; 273136849Sscottl MV_U32 freeIDsNum; 274136849Sscottl MV_U32 reqInPtr; 275136849Sscottl MV_U32 rspOutPtr; 276136849Sscottl} MV_SATA_CHANNEL; 277136849Sscottl 278136849Sscottltypedef struct mvSataAdapter 279136849Sscottl{ 280136849Sscottl /* Fields set by Intermediate Application Layer */ 281136849Sscottl MV_U32 adapterId; 282136849Sscottl MV_U8 pcbVersion; 283136849Sscottl MV_U8 pciConfigRevisionId; 284136849Sscottl MV_U16 pciConfigDeviceId; 285136849Sscottl MV_VOID_PTR IALData; 286136849Sscottl MV_BUS_ADDR_T adapterIoBaseAddress; 287136849Sscottl MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; 288136849Sscottl MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; 289136849Sscottl MV_BOOLEAN (* HPTLIBAPI mvSataEventNotify)(struct mvSataAdapter *, 290136849Sscottl MV_EVENT_TYPE, 291136849Sscottl MV_U32, MV_U32); 292136849Sscottl MV_SATA_CHANNEL *sataChannel[MV_SATA_CHANNELS_NUM]; 293136849Sscottl MV_U32 pciCommand; 294136849Sscottl MV_U32 pciSerrMask; 295136849Sscottl MV_U32 pciInterruptMask; 296136849Sscottl 297136849Sscottl /* Fields set by CORE driver */ 298136849Sscottl MV_OS_SEMAPHORE semaphore; 299136849Sscottl MV_U32 mainMask; 300136849Sscottl MV_OS_SEMAPHORE interruptsMaskSem; 301136849Sscottl MV_BOOLEAN implementA0Workarounds; 302136849Sscottl MV_BOOLEAN implement50XXB0Workarounds; 303136849Sscottl MV_BOOLEAN implement50XXB1Workarounds; 304136849Sscottl MV_BOOLEAN implement50XXB2Workarounds; 305136849Sscottl MV_BOOLEAN implement60X1A0Workarounds; 306136849Sscottl MV_BOOLEAN implement60X1A1Workarounds; 307136849Sscottl MV_BOOLEAN implement60X1B0Workarounds; 308190809Sdelphij MV_BOOLEAN implement7042A0Workarounds; 309190809Sdelphij MV_BOOLEAN implement7042A1Workarounds; 310136849Sscottl MV_U8 sataAdapterGeneration; 311190809Sdelphij MV_BOOLEAN isPEX; 312136849Sscottl MV_U8 failLEDMask; 313136849Sscottl MV_U8 signalAmps[MV_SATA_CHANNELS_NUM]; 314136849Sscottl MV_U8 pre[MV_SATA_CHANNELS_NUM]; 315136849Sscottl MV_BOOLEAN staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */ 316136849Sscottl} MV_SATA_ADAPTER; 317136849Sscottl 318136849Sscottltypedef struct mvSataAdapterStatus 319136849Sscottl{ 320136849Sscottl /* Fields set by CORE driver */ 321136849Sscottl MV_BOOLEAN channelConnected[MV_SATA_CHANNELS_NUM]; 322136849Sscottl MV_U32 pciDLLStatusAndControlRegister; 323136849Sscottl MV_U32 pciCommandRegister; 324136849Sscottl MV_U32 pciModeRegister; 325136849Sscottl MV_U32 pciSERRMaskRegister; 326136849Sscottl MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; 327136849Sscottl MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; 328136849Sscottl MV_U32 R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM]; 329136849Sscottl}MV_SATA_ADAPTER_STATUS; 330136849Sscottl 331136849Sscottl 332136849Sscottltypedef struct mvSataChannelStatus 333136849Sscottl{ 334136849Sscottl /* Fields set by CORE driver */ 335136849Sscottl MV_BOOLEAN isConnected; 336136849Sscottl MV_U8 modelNumber[MV_ATA_MODEL_NUMBER_LEN]; 337136849Sscottl MV_BOOLEAN DMAEnabled; 338136849Sscottl MV_EDMA_MODE queuedDMA; 339136849Sscottl MV_U8 outstandingCommands; 340136849Sscottl MV_U32 EdmaConfigurationRegister; 341136849Sscottl MV_U32 EdmaRequestQueueBaseAddressHighRegister; 342136849Sscottl MV_U32 EdmaRequestQueueInPointerRegister; 343136849Sscottl MV_U32 EdmaRequestQueueOutPointerRegister; 344136849Sscottl MV_U32 EdmaResponseQueueBaseAddressHighRegister; 345136849Sscottl MV_U32 EdmaResponseQueueInPointerRegister; 346136849Sscottl MV_U32 EdmaResponseQueueOutPointerRegister; 347136849Sscottl MV_U32 EdmaCommandRegister; 348136849Sscottl MV_U32 PHYModeRegister; 349136849Sscottl}MV_SATA_CHANNEL_STATUS; 350136849Sscottl 351136849Sscottl/* this structure used by the IAL defines the PRD entries used by the EDMA HW */ 352136849Sscottltypedef struct mvSataEdmaPRDEntry 353136849Sscottl{ 354136849Sscottl volatile MV_U32 lowBaseAddr; 355136849Sscottl volatile MV_U16 byteCount; 356136849Sscottl volatile MV_U16 flags; 357136849Sscottl volatile MV_U32 highBaseAddr; 358136849Sscottl volatile MV_U32 reserved; 359136849Sscottl}MV_SATA_EDMA_PRD_ENTRY; 360136849Sscottl 361136849Sscottl/* API Functions */ 362136849Sscottl 363136849Sscottl/* CORE driver Adapter Management */ 364136849SscottlMV_BOOLEAN HPTLIBAPI mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter); 365136849Sscottl 366136849SscottlMV_BOOLEAN HPTLIBAPI mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter); 367136849Sscottl 368136849SscottlMV_BOOLEAN HPTLIBAPI mvSataGetAdapterStatus(MV_SATA_ADAPTER *pAdapter, 369136849Sscottl MV_SATA_ADAPTER_STATUS *pAdapterStatus); 370136849Sscottl 371136849SscottlMV_U32 HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset); 372136849Sscottl 373136849SscottlMV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset, 374136849Sscottl MV_U32 regValue); 375136849Sscottl 376136849SscottlMV_VOID HPTLIBAPI mvEnableAutoFlush(MV_VOID); 377136849SscottlMV_VOID HPTLIBAPI mvDisableAutoFlush(MV_VOID); 378136849Sscottl 379136849Sscottl 380136849Sscottl/* CORE driver SATA Channel Management */ 381136849SscottlMV_BOOLEAN HPTLIBAPI mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter, 382136849Sscottl MV_U8 channelIndex); 383136849Sscottl 384136849SscottlMV_BOOLEAN HPTLIBAPI mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); 385136849Sscottl 386136849SscottlMV_BOOLEAN HPTLIBAPI mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter, 387136849Sscottl MV_U8 channelIndex); 388136849Sscottl 389136849SscottlMV_BOOLEAN HPTLIBAPI mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter, 390136849Sscottl MV_U8 channelIndex); 391136849Sscottl 392136849SscottlMV_BOOLEAN HPTLIBAPI mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 393136849Sscottl MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth); 394136849Sscottl 395136849SscottlMV_BOOLEAN HPTLIBAPI mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter, 396136849Sscottl MV_U8 channelIndex); 397136849Sscottl 398136849SscottlMV_BOOLEAN HPTLIBAPI mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter, 399136849Sscottl MV_U8 channelIndex); 400136849Sscottl 401136849SscottlMV_BOOLEAN HPTLIBAPI mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 402136849Sscottl MV_FLUSH_TYPE flushType); 403136849Sscottl 404136849SscottlMV_U8 HPTLIBAPI mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); 405136849Sscottl 406136849SscottlMV_BOOLEAN HPTLIBAPI mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, 407136849Sscottl MV_U32 intCoalThre, MV_U32 intTimeThre); 408136849Sscottl 409136849SscottlMV_BOOLEAN HPTLIBAPI mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter, 410136849Sscottl MV_U8 channelIndex, 411136849Sscottl MV_U8 signalAmps, MV_U8 pre); 412136849Sscottl 413136849SscottlMV_BOOLEAN HPTLIBAPI mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter, 414136849Sscottl MV_U8 channelIndex); 415136849Sscottl 416136849SscottlMV_BOOLEAN HPTLIBAPI mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter, 417136849Sscottl MV_U8 channelIndex); 418136849Sscottl 419136849SscottlMV_BOOLEAN HPTLIBAPI mvSataChannelSetEdmaLoopBackMode(MV_SATA_ADAPTER *pAdapter, 420136849Sscottl MV_U8 channelIndex, 421136849Sscottl MV_BOOLEAN loopBackOn); 422136849Sscottl 423136849SscottlMV_BOOLEAN HPTLIBAPI mvSataGetChannelStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 424136849Sscottl MV_SATA_CHANNEL_STATUS *pChannelStatus); 425136849Sscottl 426136849SscottlMV_QUEUE_COMMAND_RESULT HPTLIBAPI mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter, 427136849Sscottl MV_U8 channelIndex, 428190809Sdelphij MV_QUEUE_COMMAND_INFO SS_SEG *pCommandParams); 429136849Sscottl 430136849Sscottl/* Interrupt Service Routine */ 431136849SscottlMV_BOOLEAN HPTLIBAPI mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter); 432136849Sscottl 433136849SscottlMV_BOOLEAN HPTLIBAPI mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); 434136849Sscottl 435136849SscottlMV_BOOLEAN HPTLIBAPI mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); 436136849Sscottl 437136849Sscottl/* Command Completion and Event Notification (user implemented) */ 438136849SscottlMV_BOOLEAN HPTLIBAPI mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE , 439136849Sscottl MV_U32, MV_U32); 440136849Sscottl 441136849Sscottl/* 442136849Sscottl * Staggered spin-ip support and SATA interface speed control 443136849Sscottl * (relevant for 60x1 adapters) 444136849Sscottl */ 445136849SscottlMV_BOOLEAN HPTLIBAPI mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); 446136849SscottlMV_BOOLEAN HPTLIBAPI mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); 447136849Sscottl 448136849Sscottl#endif 449