if_gemreg.h revision 91398
161765Smjacob/* 2139749Simp * Copyright (C) 2001 Eduardo Horvath. 362525Smjacob * All rights reserved. 461765Smjacob * 561765Smjacob * 661765Smjacob * Redistribution and use in source and binary forms, with or without 761765Smjacob * modification, are permitted provided that the following conditions 861765Smjacob * are met: 961765Smjacob * 1. Redistributions of source code must retain the above copyright 1061765Smjacob * notice, this list of conditions and the following disclaimer. 1161765Smjacob * 2. Redistributions in binary form must reproduce the above copyright 1261765Smjacob * notice, this list of conditions and the following disclaimer in the 1361765Smjacob * documentation and/or other materials provided with the distribution. 1461765Smjacob * 1561765Smjacob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1661765Smjacob * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1761765Smjacob * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1861765Smjacob * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1961765Smjacob * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2061765Smjacob * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2161765Smjacob * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2261765Smjacob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2361765Smjacob * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2461765Smjacob * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2561765Smjacob * SUCH DAMAGE. 2661765Smjacob * 2761765Smjacob * from: NetBSD: gemreg.h,v 1.2 2001/10/18 03:33:33 thorpej Exp 2862525Smjacob * 2961765Smjacob * $FreeBSD: head/sys/dev/gem/if_gemreg.h 91398 2002-02-27 17:41:06Z tmm $ 3062525Smjacob */ 3162525Smjacob 3285265Smjacob#ifndef _IF_GEMREG_H 3361765Smjacob#define _IF_GEMREG_H 3461765Smjacob 35124527Smjacob/* Register definitions for Sun GEM gigabit ethernet */ 3672345Smjacob 37160212Smjacob#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 3872345Smjacob#define GEM_CONFIG 0x0004 /* config reg */ 39124527Smjacob#define GEM_STATUS 0x000c /* status reg */ 4072345Smjacob/* Note: Reading the status reg clears bits 0-6 */ 4172345Smjacob#define GEM_INTMASK 0x0010 4272345Smjacob#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 4372345Smjacob#define GEM_STATUS_ALIAS 0x001c 4472345Smjacob/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 4572345Smjacob#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 4672345Smjacob#define GEM_ERROR_MASK 0x1004 47124527Smjacob#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 4872345Smjacob#define GEM_BIF_DIAG 0x100c 4972345Smjacob#define GEM_RESET 0x1010 /* Software reset register */ 5072345Smjacob 5172345Smjacob 52124527Smjacob/* Bits in GEM_SEB register */ 53124527Smjacob#define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 54124527Smjacob#define GEM_SEB_RXWON 0x000000004 5572345Smjacob 5672345Smjacob 57124527Smjacob/* Bits in GEM_CONFIG register */ 58124527Smjacob#define GEM_CONFIG_BURST_64 0x000000000 /* 0->infininte, 1->64KB */ 59124527Smjacob#define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infininte, 1->64KB */ 6072345Smjacob#define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 6172345Smjacob#define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 62124527Smjacob 6372345Smjacob#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 6472345Smjacob#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 65124527Smjacob 66124527Smjacob 67124527Smjacob/* Top part of GEM_STATUS has TX completion information */ 68124527Smjacob#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 69124527Smjacob 70124527Smjacob 71124527Smjacob/* Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. */ 7285265Smjacob#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 73124527Smjacob#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 74124527Smjacob#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 7585265Smjacob#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 76124527Smjacob#define GEM_INTR_RX_NOBUF 0x000000020 77124527Smjacob#define GEM_INTR_RX_TAG_ERR 0x000000040 7872345Smjacob#define GEM_INTR_PCS 0x000002000 7972345Smjacob#define GEM_INTR_TX_MAC 0x000004000 8072345Smjacob#define GEM_INTR_RX_MAC 0x000008000 81124527Smjacob#define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 82124527Smjacob#define GEM_INTR_MIF 0x000020000 83124527Smjacob#define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 84124527Smjacob#define GEM_INTR_BITS "\177\020" \ 85124527Smjacob "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 86124527Smjacob "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 8772345Smjacob "b\15PCS\0b\16TXMAC\0b\17RXMAC\0" \ 8885265Smjacob "b\20MAC_CONTROL\0b\21MIF\0b\22BERR\0\0" \ 8972345Smjacob 90124527Smjacob 91124527Smjacob 92124527Smjacob/* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */ 93124527Smjacob#define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 9472345Smjacob#define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 95124527Smjacob#define GEM_ERROR_STAT_OTHERS 0x000000004 96124527Smjacob 97124527Smjacob 98124527Smjacob/* GEM_BIF_CONFIG register bits */ 9972345Smjacob#define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 100124527Smjacob#define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 101124527Smjacob#define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 102124527Smjacob#define GEM_BIF_CONFIG_M66EN 0x000000008 10372345Smjacob 104124527Smjacob 105124527Smjacob/* GEM_RESET register bits -- TX and RX self clear when complete. */ 106124527Smjacob#define GEM_RESET_TX 0x000000001 /* Reset TX half */ 10772345Smjacob#define GEM_RESET_RX 0x000000002 /* Reset RX half */ 10872345Smjacob#define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 10972345Smjacob 11072345Smjacob 11172345Smjacob/* GEM TX DMA registers */ 112124527Smjacob#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 11372345Smjacob#define GEM_TX_CONFIG 0x2004 114124527Smjacob#define GEM_TX_RING_PTR_LO 0x2008 115124527Smjacob#define GEM_TX_RING_PTR_HI 0x200c 116124527Smjacob 117124527Smjacob#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 118124527Smjacob#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 119124527Smjacob#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 120124527Smjacob#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 121124527Smjacob#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 12272345Smjacob 12372345Smjacob#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 12485265Smjacob#define GEM_TX_DATA_PTR_LO 0x2030 12585265Smjacob#define GEM_TX_DATA_PTR_HI 0x2034 126124527Smjacob 127124527Smjacob#define GEM_TX_COMPLETION 0x2100 128124527Smjacob#define GEM_TX_FIFO_ADDRESS 0x2104 129124527Smjacob#define GEM_TX_FIFO_TAG 0x2108 13085265Smjacob#define GEM_TX_FIFO_DATA_LO 0x210c 131124527Smjacob#define GEM_TX_FIFO_DATA_HI_T1 0x2110 132124527Smjacob#define GEM_TX_FIFO_DATA_HI_T0 0x2114 133124527Smjacob#define GEM_TX_FIFO_SIZE 0x2118 13485265Smjacob#define GEM_TX_DEBUG 0x3028 135124527Smjacob 136124527Smjacob 13785265Smjacob/* GEM_TX_CONFIG register bits. */ 13885265Smjacob#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 13985265Smjacob#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 14085265Smjacob#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 141124527Smjacob#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 142124527Smjacob 143124527Smjacob#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 144124527Smjacob#define GEM_RING_SZ_64 (1<<1) 145124527Smjacob#define GEM_RING_SZ_128 (2<<1) 146124527Smjacob#define GEM_RING_SZ_256 (3<<1) 147124527Smjacob#define GEM_RING_SZ_512 (4<<1) 148124527Smjacob#define GEM_RING_SZ_1024 (5<<1) 149124527Smjacob#define GEM_RING_SZ_2048 (6<<1) 150124527Smjacob#define GEM_RING_SZ_4096 (7<<1) 151124527Smjacob#define GEM_RING_SZ_8192 (8<<1) 152124527Smjacob 15385265Smjacob 15485265Smjacob/* GEM_TX_COMPLETION register bits */ 15585265Smjacob#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 15685265Smjacob 15785265Smjacob 15885265Smjacob/* GEM RX DMA registers */ 15985265Smjacob#define GEM_RX_CONFIG 0x4000 16085265Smjacob#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 16185265Smjacob#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 16285265Smjacob 16385265Smjacob#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 16485265Smjacob#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 16585265Smjacob#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 16685265Smjacob#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 16785265Smjacob 16885265Smjacob#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 16985265Smjacob#define GEM_RX_PAUSE_THRESH 0x4020 17085265Smjacob 17185265Smjacob#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 17285265Smjacob#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 17385265Smjacob 17485265Smjacob#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 17585265Smjacob#define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 17685265Smjacob#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 17785265Smjacob 17885265Smjacob#define GEM_RX_FIFO_ADDRESS 0x410c 17985265Smjacob#define GEM_RX_FIFO_TAG 0x4110 18085265Smjacob#define GEM_RX_FIFO_DATA_LO 0x4114 18185265Smjacob#define GEM_RX_FIFO_DATA_HI_T1 0x4118 182124527Smjacob#define GEM_RX_FIFO_DATA_HI_T0 0x411c 18385265Smjacob#define GEM_RX_FIFO_SIZE 0x4120 18485265Smjacob 18585265Smjacob 18685265Smjacob/* GEM_RX_CONFIG register bits. */ 18785265Smjacob#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 18885265Smjacob#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 18985265Smjacob#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 19085265Smjacob#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 19185265Smjacob#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* checksum start offset */ 19285265Smjacob#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 19385265Smjacob 19485265Smjacob#define GEM_THRSH_64 0 19585265Smjacob#define GEM_THRSH_128 1 19685265Smjacob#define GEM_THRSH_256 2 19785265Smjacob#define GEM_THRSH_512 3 19885265Smjacob#define GEM_THRSH_1024 4 19985265Smjacob#define GEM_THRSH_2048 5 20085265Smjacob 20185265Smjacob#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 202124527Smjacob#define GEM_RX_CONFIG_FBOFF_SHFT 10 203124527Smjacob#define GEM_RX_CONFIG_CXM_START_SHFT 13 20485265Smjacob 205124527Smjacob 20685265Smjacob/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 207124527Smjacob#define GEM_RX_PTH_XOFF_THRESH 0x000001ff 208124527Smjacob#define GEM_RX_PTH_XON_THRESH 0x07fc0000 209124527Smjacob 210124527Smjacob 211124527Smjacob/* GEM_RX_BLANKING register bits */ 212124527Smjacob#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 213124527Smjacob#define GEM_RX_BLANKING_TIME 0x03fc0000 /* Delay intr for x ticks */ 214124527Smjacob/* One tick is 1048 PCI clocs, or 16us at 66MHz */ 215124527Smjacob 216124527Smjacob 217124527Smjacob/* GEM_MAC registers */ 218124527Smjacob#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 219124527Smjacob#define GEM_MAC_RXRESET 0x6004 /* ditto */ 220124527Smjacob#define GEM_MAC_SEND_PAUSE_CMD 0x6008 221124527Smjacob#define GEM_MAC_TX_STATUS 0x6010 222124527Smjacob#define GEM_MAC_RX_STATUS 0x6014 223124527Smjacob#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 224124527Smjacob#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 225124527Smjacob#define GEM_MAC_RX_MASK 0x6024 226124527Smjacob#define GEM_MAC_CONTROL_MASK 0x6028 227124527Smjacob#define GEM_MAC_TX_CONFIG 0x6030 228124527Smjacob#define GEM_MAC_RX_CONFIG 0x6034 229124527Smjacob#define GEM_MAC_CONTROL_CONFIG 0x6038 230124527Smjacob#define GEM_MAC_XIF_CONFIG 0x603c 231124527Smjacob#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 232124527Smjacob#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 233124527Smjacob#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 234124527Smjacob#define GEM_MAC_SLOT_TIME 0x604c 235124527Smjacob#define GEM_MAC_MAC_MIN_FRAME 0x6050 236124527Smjacob#define GEM_MAC_MAC_MAX_FRAME 0x6054 237124527Smjacob#define GEM_MAC_PREAMBLE_LEN 0x6058 238124527Smjacob#define GEM_MAC_JAM_SIZE 0x605c 239124527Smjacob#define GEM_MAC_ATTEMPT_LIMIT 0x6060 240124527Smjacob#define GEM_MAC_CONTROL_TYPE 0x6064 241124527Smjacob 242124527Smjacob#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 243124527Smjacob#define GEM_MAC_ADDR1 0x6084 244124527Smjacob#define GEM_MAC_ADDR2 0x6088 245124527Smjacob#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 246124527Smjacob#define GEM_MAC_ADDR4 0x6090 247124527Smjacob#define GEM_MAC_ADDR5 0x6094 248124527Smjacob#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 249124527Smjacob#define GEM_MAC_ADDR7 0x609c 250124527Smjacob#define GEM_MAC_ADDR8 0x60a0 251124527Smjacob 252124527Smjacob#define GEM_MAC_ADDR_FILTER0 0x60a4 253124527Smjacob#define GEM_MAC_ADDR_FILTER1 0x60a8 254124527Smjacob#define GEM_MAC_ADDR_FILTER2 0x60ac 255124527Smjacob#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 256124527Smjacob#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 257124527Smjacob 258124527Smjacob#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 259124527Smjacob#define GEM_MAC_HASH1 0x60c4 260124527Smjacob#define GEM_MAC_HASH2 0x60c8 261124527Smjacob#define GEM_MAC_HASH3 0x60cc 262124527Smjacob#define GEM_MAC_HASH4 0x60d0 263124527Smjacob#define GEM_MAC_HASH5 0x60d4 264124527Smjacob#define GEM_MAC_HASH6 0x60d8 265124527Smjacob#define GEM_MAC_HASH7 0x60dc 266124527Smjacob#define GEM_MAC_HASH8 0x60e0 267124527Smjacob#define GEM_MAC_HASH9 0x60e4 268124527Smjacob#define GEM_MAC_HASH10 0x60e8 269124527Smjacob#define GEM_MAC_HASH11 0x60ec 270124527Smjacob#define GEM_MAC_HASH12 0x60f0 271124527Smjacob#define GEM_MAC_HASH13 0x60f4 272124527Smjacob#define GEM_MAC_HASH14 0x60f8 273124527Smjacob#define GEM_MAC_HASH15 0x60fc 274124527Smjacob 275124527Smjacob#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 276124527Smjacob#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 277124527Smjacob#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 278124527Smjacob#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 279124527Smjacob#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 280124527Smjacob#define GEM_MAC_PEAK_ATTEMPTS 0x6114 281124527Smjacob#define GEM_MAC_RX_FRAME_COUNT 0x6118 282124527Smjacob#define GEM_MAC_RX_LEN_ERR_CNT 0x611c 283124527Smjacob#define GEM_MAC_RX_ALIGN_ERR 0x6120 284124527Smjacob#define GEM_MAC_RX_CRC_ERR_CNT 0x6124 285124527Smjacob#define GEM_MAC_RX_CODE_VIOL 0x6128 286124527Smjacob#define GEM_MAC_RANDOM_SEED 0x6130 287124527Smjacob#define GEM_MAC_MAC_STATE 0x6134 /* MAC sstate machine reg */ 288124527Smjacob 289124527Smjacob 290124527Smjacob/* GEM_MAC_SEND_PAUSE_CMD register bits */ 291124527Smjacob#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 292124527Smjacob#define GEM_MAC_PAUSE_CMD_SEND 0x00010000 293124527Smjacob 294124527Smjacob 295124527Smjacob/* GEM_MAC_TX_STATUS and _MASK register bits */ 296124527Smjacob#define GEM_MAC_TX_XMIT_DONE 0x00000001 297124527Smjacob#define GEM_MAC_TX_UNDERRUN 0x00000002 298124527Smjacob#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 299124527Smjacob#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 300124527Smjacob#define GEM_MAC_TX_ECC_EXP 0x00000010 301124527Smjacob#define GEM_MAC_TX_LCC_EXP 0x00000020 302124527Smjacob#define GEM_MAC_TX_FCC_EXP 0x00000040 303124527Smjacob#define GEM_MAC_TX_DEFER_EXP 0x00000080 304124527Smjacob#define GEM_MAC_TX_PEAK_EXP 0x00000100 305124527Smjacob 306124527Smjacob 307124527Smjacob/* GEM_MAC_RX_STATUS and _MASK register bits */ 308124527Smjacob#define GEM_MAC_RX_DONE 0x00000001 309124527Smjacob#define GEM_MAC_RX_OVERFLOW 0x00000002 310124527Smjacob#define GEM_MAC_RX_FRAME_CNT 0x00000004 311124527Smjacob#define GEM_MAC_RX_ALIGN_EXP 0x00000008 312124527Smjacob#define GEM_MAC_RX_CRC_EXP 0x00000010 313124527Smjacob#define GEM_MAC_RX_LEN_EXP 0x00000020 314124527Smjacob#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 315124527Smjacob 316124527Smjacob 31785265Smjacob/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 31885265Smjacob#define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 319124527Smjacob#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 320124527Smjacob#define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 321124527Smjacob#define GEM_MAC_PAUSE_TIME 0xffff0000 322124527Smjacob 32385265Smjacob/* GEM_MAC_XIF_CONFIG register bits */ 32485265Smjacob#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 32585265Smjacob#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 32685265Smjacob#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 32785265Smjacob#define GEM_MAC_XIF_MII_MODE 0x00000008 /* Select GMII/MII mode */ 328124527Smjacob#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 32985265Smjacob#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 330124527Smjacob#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 33185265Smjacob 332124527Smjacob/* GEM_MAC_TX_CONFIG register bits */ 33385265Smjacob#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 334124527Smjacob#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 33585265Smjacob#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collitions */ 336124527Smjacob#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 337124527Smjacob#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 338124527Smjacob#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 339124527Smjacob#define GEM_MAC_TX_NO_BACKOFF 0x00000040 340124527Smjacob#define GEM_MAC_TX_SLOWDOWN 0x00000080 341124527Smjacob#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 342124527Smjacob#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 34385265Smjacob/* Carrier Extension is required for half duplex Gbps operation */ 34485265Smjacob 345124527Smjacob 346124527Smjacob/* GEM_MAC_RX_CONFIG register bits */ 347124527Smjacob#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 348124527Smjacob#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 349124527Smjacob#define GEM_MAC_RX_STRIP_CRC 0x00000004 350124527Smjacob#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 35185265Smjacob#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 352124527Smjacob#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 353124527Smjacob#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 354124527Smjacob#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 35585265Smjacob#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 356124527Smjacob/* 357124527Smjacob * Carrier Extension enables reception of packet bursts generated by 358124527Smjacob * senders with carrier extension enabled. 35985265Smjacob */ 360124527Smjacob 361124527Smjacob 362124527Smjacob/* GEM_MAC_CONTROL_CONFIG bits */ 363124527Smjacob#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 364124527Smjacob#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 365124527Smjacob#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 366124527Smjacob 367124527Smjacob 368124527Smjacob/* GEM MIF registers */ 369124527Smjacob/* Bit bang registers use low bit only */ 370124527Smjacob#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 371124527Smjacob#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 372124527Smjacob#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 373124527Smjacob#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 374124527Smjacob#define GEM_MIF_CONFIG 0x6210 375124527Smjacob#define GEM_MIF_INTERRUPT_MASK 0x6214 376124527Smjacob#define GEM_MIF_BASIC_STATUS 0x6218 377124527Smjacob#define GEM_MIF_STATE_MACHINE 0x621c 378124527Smjacob 379124527Smjacob 380124527Smjacob/* GEM_MIF_FRAME bits */ 381124527Smjacob#define GEM_MIF_FRAME_DATA 0x0000ffff 382124527Smjacob#define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 383124527Smjacob#define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 384124527Smjacob#define GEM_MIF_FRAME_REG_ADDR 0x007c0000 385124527Smjacob#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */ 386124527Smjacob#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 387124527Smjacob#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 388124527Smjacob 389124527Smjacob#define GEM_MIF_FRAME_READ 0x60020000 390124527Smjacob#define GEM_MIF_FRAME_WRITE 0x50020000 391124527Smjacob 392124527Smjacob#define GEM_MIF_REG_SHIFT 18 393124527Smjacob#define GEM_MIF_PHY_SHIFT 23 394124527Smjacob 395124527Smjacob 396124527Smjacob/* GEM_MIF_CONFIG register bits */ 397124527Smjacob#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select */ 398124527Smjacob#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 399124527Smjacob#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 400124527Smjacob#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 401124527Smjacob#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 402124527Smjacob#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 403124527Smjacob#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 404124527Smjacob/* MDI0 is onboard tranciever MID1 is external, PHYAD for both is 0 */ 405124527Smjacob 406124527Smjacob 407124527Smjacob/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 408124527Smjacob#define GEM_MIF_STATUS 0x0000ffff 409124527Smjacob#define GEM_MIF_BASIC 0xffff0000 410124527Smjacob/* 411124527Smjacob * The Basic part is the last value read in the POLL field of the config 412124527Smjacob * register. 413124527Smjacob * 414124527Smjacob * The status part indicates the bits that have changed. 415124527Smjacob */ 416124527Smjacob 417124527Smjacob 418124527Smjacob/* The GEM PCS/Serial link register. */ 419124527Smjacob#define GEM_MII_CONTROL 0x9000 420124527Smjacob#define GEM_MII_STATUS 0x9004 421124527Smjacob#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 422124527Smjacob#define GEM_MII_ANLPAR 0x900c /* LP ability reg */ 423124527Smjacob#define GEM_MII_CONFIG 0x9010 424124527Smjacob#define GEM_MII_STATE_MACHINE 0x9014 425124527Smjacob#define GEM_MII_INTERRUP_STATUS 0x9018 426124527Smjacob#define GEM_MII_DATAPATH_MODE 0x9050 427124527Smjacob#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 428124527Smjacob#define GEM_MII_OUTPUT_SELECT 0x9058 429124527Smjacob#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */ 430124527Smjacob 431124527Smjacob 432124527Smjacob/* GEM_MII_CONTROL bits */ 433124527Smjacob/* 434124527Smjacob * DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS. 435124527Smjacob */ 436124527Smjacob#define GEM_MII_CONTROL_RESET 0x00008000 437124527Smjacob#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 438124527Smjacob#define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */ 439124527Smjacob#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 440124527Smjacob#define GEM_MII_CONTROL_POWERDN 0x00000800 441124527Smjacob#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */ 442124527Smjacob#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotioation */ 443124527Smjacob#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 444124527Smjacob#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 445124527Smjacob 446124527Smjacob 447124527Smjacob/* GEM_MII_STATUS reg */ 448124527Smjacob#define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 449124527Smjacob#define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 450124527Smjacob#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ 451124527Smjacob#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 452124527Smjacob#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ 453124527Smjacob#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 454124527Smjacob#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 455124527Smjacob#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ 456124527Smjacob 457124527Smjacob 458124527Smjacob/* GEM_MII_ANAR and GEM_MII_ANLAR reg bits */ 459124527Smjacob#define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ 460124527Smjacob#define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ 461124527Smjacob /* Link Partner Capability */ 462124527Smjacob#define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */ 463124527Smjacob#define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */ 464124527Smjacob#define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ 465124527Smjacob#define GEM_MII_ANEG_HLF_DUPLX 0x00000040 466124527Smjacob#define GEM_MII_ANEG_FUL_DUPLX 0x00000020 467124527Smjacob 468124527Smjacob 469124527Smjacob/* GEM_MII_CONFIG reg */ 470124527Smjacob#define GEM_MII_CONFIG_TIMER 0x0000001c /* link monitor timer values */ 471124527Smjacob#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 472124527Smjacob 473124527Smjacob 474124527Smjacob/* GEM_MII_DATAPATH_MODE reg */ 475124527Smjacob#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ 476124527Smjacob#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 477124527Smjacob#define GEM_MII_DATAPATH_MII 0x00000004 /* Use MII, not PCS */ 478124527Smjacob#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ 479124527Smjacob 480124527Smjacob 481124527Smjacob/* GEM_MII_SLINK_CONTROL reg */ 482124527Smjacob#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl */ 483124527Smjacob#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 484124527Smjacob#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 485124527Smjacob#define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ 486124527Smjacob#define GEM_MII_SLINK_SELFTEST 0x000001c0 487124527Smjacob#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ 488124527Smjacob 489124527Smjacob 490124527Smjacob/* GEM_MII_SLINK_STATUS reg */ 491124527Smjacob#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 492124527Smjacob#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 493124527Smjacob#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 494124527Smjacob#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 495124527Smjacob 496124527Smjacob 497124527Smjacob/* Wired GEM PHY addresses */ 498124527Smjacob#define GEM_PHYAD_INTERNAL 1 499124527Smjacob#define GEM_PHYAD_EXTERNAL 0 500124527Smjacob 501124527Smjacob/* 502124527Smjacob * GEM descriptor table structures. 503124527Smjacob */ 504124527Smjacobstruct gem_desc { 505124527Smjacob uint64_t gd_flags; 506124527Smjacob uint64_t gd_addr; 507124527Smjacob}; 508124527Smjacob 509124527Smjacob/* Transmit flags */ 510124527Smjacob#define GEM_TD_BUFSIZE 0x0000000000007fffLL 511124527Smjacob#define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 512124527Smjacob#define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 513124527Smjacob#define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 514124527Smjacob#define GEM_TD_END_OF_PACKET 0x0000000040000000LL 515124527Smjacob#define GEM_TD_START_OF_PACKET 0x0000000080000000LL 516124527Smjacob#define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 517124527Smjacob#define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 518124527Smjacob/* 519124527Smjacob * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 520124527Smjacob * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 521124527Smjacob */ 522124527Smjacob 523124527Smjacob/* Receive flags */ 524124527Smjacob#define GEM_RD_CHECKSUM 0x000000000000ffffLL 525124527Smjacob#define GEM_RD_BUFSIZE 0x000000007fff0000LL 526124527Smjacob#define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 527124527Smjacob#define GEM_RD_HASHVAL 0x0ffff00000000000LL 528124527Smjacob#define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 529124527Smjacob#define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 530124527Smjacob#define GEM_RD_BAD_CRC 0x4000000000000000LL 531124527Smjacob 532124527Smjacob#define GEM_RD_BUFSHIFT 16 533124527Smjacob#define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 534124527Smjacob 535124527Smjacob/* PCI support */ 536124527Smjacob#define PCI_GEM_BASEADDR 0x10 537124527Smjacob 538124527Smjacob#endif 539124527Smjacob