if_gemreg.h revision 174987
1139749Simp/*- 291398Stmm * Copyright (C) 2001 Eduardo Horvath. 391398Stmm * All rights reserved. 491398Stmm * 591398Stmm * 691398Stmm * Redistribution and use in source and binary forms, with or without 791398Stmm * modification, are permitted provided that the following conditions 891398Stmm * are met: 991398Stmm * 1. Redistributions of source code must retain the above copyright 1091398Stmm * notice, this list of conditions and the following disclaimer. 1191398Stmm * 2. Redistributions in binary form must reproduce the above copyright 1291398Stmm * notice, this list of conditions and the following disclaimer in the 1391398Stmm * documentation and/or other materials provided with the distribution. 1491398Stmm * 1591398Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1691398Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1791398Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1891398Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1991398Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2091398Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2191398Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2291398Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2391398Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2491398Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2591398Stmm * SUCH DAMAGE. 2691398Stmm * 27172334Smarius * from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp 2891398Stmm * 2991398Stmm * $FreeBSD: head/sys/dev/gem/if_gemreg.h 174987 2007-12-30 01:32:03Z marius $ 3091398Stmm */ 3191398Stmm 3291398Stmm#ifndef _IF_GEMREG_H 3391398Stmm#define _IF_GEMREG_H 3491398Stmm 3591398Stmm/* Register definitions for Sun GEM gigabit ethernet */ 3691398Stmm 3791398Stmm#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 3891398Stmm#define GEM_CONFIG 0x0004 /* config reg */ 3991398Stmm#define GEM_STATUS 0x000c /* status reg */ 40174987Smarius/* Note: Reading the status reg clears bits 0-6. */ 4191398Stmm#define GEM_INTMASK 0x0010 4291398Stmm#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 4391398Stmm#define GEM_STATUS_ALIAS 0x001c 4491398Stmm/* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 4591398Stmm#define GEM_ERROR_STATUS 0x1000 /* PCI error status R/C */ 4691398Stmm#define GEM_ERROR_MASK 0x1004 4791398Stmm#define GEM_BIF_CONFIG 0x1008 /* BIF config reg */ 4891398Stmm#define GEM_BIF_DIAG 0x100c 4991398Stmm#define GEM_RESET 0x1010 /* Software reset register */ 5091398Stmm 5191398Stmm 5291398Stmm/* Bits in GEM_SEB register */ 5391398Stmm#define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 5491398Stmm#define GEM_SEB_RXWON 0x000000004 5591398Stmm 5691398Stmm 5791398Stmm/* Bits in GEM_CONFIG register */ 58172334Smarius#define GEM_CONFIG_BURST_64 0x000000000 /* maximum burst size 64KB */ 59172334Smarius#define GEM_CONFIG_BURST_INF 0x000000001 /* infinite for entire packet */ 6091398Stmm#define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 6191398Stmm#define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 62172334Smarius/* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 63172334Smarius#define GEM_CONFIG_RONPAULBIT 0x000000800 /* after infinite burst use */ 64172334Smarius /* memory read multiple for */ 65172334Smarius /* PCI commands */ 66172334Smarius#define GEM_CONFIG_BUG2FIX 0x000001000 /* fix RX hang after overflow */ 6791398Stmm 6891398Stmm#define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 6991398Stmm#define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 7091398Stmm 7191398Stmm 7291398Stmm/* Top part of GEM_STATUS has TX completion information */ 7391398Stmm#define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 7491398Stmm 7591398Stmm 76172334Smarius/* 77174987Smarius * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs 78172334Smarius * Bits 0-6 auto-clear when read. 79172334Smarius */ 8091398Stmm#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 8191398Stmm#define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 8291398Stmm#define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 8391398Stmm#define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 8491398Stmm#define GEM_INTR_RX_NOBUF 0x000000020 8591398Stmm#define GEM_INTR_RX_TAG_ERR 0x000000040 86172334Smarius#define GEM_INTR_PERR 0x000000080 /* Parity error */ 87172334Smarius#define GEM_INTR_PCS 0x000002000 /* Physical Code Sub-layer */ 8891398Stmm#define GEM_INTR_TX_MAC 0x000004000 8991398Stmm#define GEM_INTR_RX_MAC 0x000008000 9091398Stmm#define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 9191398Stmm#define GEM_INTR_MIF 0x000020000 9291398Stmm#define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 93172334Smarius#define GEM_INTR_BITS "\177\020" \ 9491398Stmm "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 9591398Stmm "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 96172334Smarius "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 97172334Smarius "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 9891398Stmm 9991398Stmm 10091398Stmm/* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */ 10191398Stmm#define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 10291398Stmm#define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 10391398Stmm#define GEM_ERROR_STAT_OTHERS 0x000000004 104172334Smarius#define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 10591398Stmm 10691398Stmm 10791398Stmm/* GEM_BIF_CONFIG register bits */ 10891398Stmm#define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 10991398Stmm#define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 11091398Stmm#define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 11191398Stmm#define GEM_BIF_CONFIG_M66EN 0x000000008 112172334Smarius#define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 113172334Smarius "b\2B64DIS\0b\3M66EN\0\0" 11491398Stmm 11591398Stmm 11691398Stmm/* GEM_RESET register bits -- TX and RX self clear when complete. */ 11791398Stmm#define GEM_RESET_TX 0x000000001 /* Reset TX half */ 11891398Stmm#define GEM_RESET_RX 0x000000002 /* Reset RX half */ 11991398Stmm#define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 12091398Stmm 12191398Stmm 12291398Stmm/* GEM TX DMA registers */ 12391398Stmm#define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 12491398Stmm#define GEM_TX_CONFIG 0x2004 12591398Stmm#define GEM_TX_RING_PTR_LO 0x2008 12691398Stmm#define GEM_TX_RING_PTR_HI 0x200c 12791398Stmm 12891398Stmm#define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 12991398Stmm#define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 13091398Stmm#define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 13191398Stmm#define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 13291398Stmm#define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 13391398Stmm 13491398Stmm#define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 13591398Stmm#define GEM_TX_DATA_PTR_LO 0x2030 13691398Stmm#define GEM_TX_DATA_PTR_HI 0x2034 13791398Stmm 13891398Stmm#define GEM_TX_COMPLETION 0x2100 13991398Stmm#define GEM_TX_FIFO_ADDRESS 0x2104 14091398Stmm#define GEM_TX_FIFO_TAG 0x2108 14191398Stmm#define GEM_TX_FIFO_DATA_LO 0x210c 14291398Stmm#define GEM_TX_FIFO_DATA_HI_T1 0x2110 14391398Stmm#define GEM_TX_FIFO_DATA_HI_T0 0x2114 14491398Stmm#define GEM_TX_FIFO_SIZE 0x2118 14591398Stmm#define GEM_TX_DEBUG 0x3028 14691398Stmm 14791398Stmm 148174987Smarius/* GEM_TX_CONFIG register bits */ 14991398Stmm#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 15091398Stmm#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 15191398Stmm#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 15291398Stmm#define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 15391398Stmm 15491398Stmm#define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 15591398Stmm#define GEM_RING_SZ_64 (1<<1) 15691398Stmm#define GEM_RING_SZ_128 (2<<1) 15791398Stmm#define GEM_RING_SZ_256 (3<<1) 15891398Stmm#define GEM_RING_SZ_512 (4<<1) 15991398Stmm#define GEM_RING_SZ_1024 (5<<1) 16091398Stmm#define GEM_RING_SZ_2048 (6<<1) 16191398Stmm#define GEM_RING_SZ_4096 (7<<1) 16291398Stmm#define GEM_RING_SZ_8192 (8<<1) 16391398Stmm 16491398Stmm 16591398Stmm/* GEM_TX_COMPLETION register bits */ 16691398Stmm#define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 16791398Stmm 16891398Stmm 16991398Stmm/* GEM RX DMA registers */ 17091398Stmm#define GEM_RX_CONFIG 0x4000 17191398Stmm#define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 17291398Stmm#define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 17391398Stmm 17491398Stmm#define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 17591398Stmm#define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 17691398Stmm#define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 17791398Stmm#define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 17891398Stmm 17991398Stmm#define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 18091398Stmm#define GEM_RX_PAUSE_THRESH 0x4020 18191398Stmm 18291398Stmm#define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 18391398Stmm#define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 18491398Stmm 18591398Stmm#define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 18691398Stmm#define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 18791398Stmm#define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 18891398Stmm 18991398Stmm#define GEM_RX_FIFO_ADDRESS 0x410c 19091398Stmm#define GEM_RX_FIFO_TAG 0x4110 19191398Stmm#define GEM_RX_FIFO_DATA_LO 0x4114 19291398Stmm#define GEM_RX_FIFO_DATA_HI_T1 0x4118 19391398Stmm#define GEM_RX_FIFO_DATA_HI_T0 0x411c 19491398Stmm#define GEM_RX_FIFO_SIZE 0x4120 19591398Stmm 19691398Stmm 197174987Smarius/* GEM_RX_CONFIG register bits */ 19891398Stmm#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 19991398Stmm#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 20091398Stmm#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 20191398Stmm#define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 202172334Smarius#define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 20391398Stmm#define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 20491398Stmm 20591398Stmm#define GEM_THRSH_64 0 20691398Stmm#define GEM_THRSH_128 1 20791398Stmm#define GEM_THRSH_256 2 20891398Stmm#define GEM_THRSH_512 3 20991398Stmm#define GEM_THRSH_1024 4 21091398Stmm#define GEM_THRSH_2048 5 21191398Stmm 21291398Stmm#define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 21391398Stmm#define GEM_RX_CONFIG_FBOFF_SHFT 10 21491398Stmm#define GEM_RX_CONFIG_CXM_START_SHFT 13 21591398Stmm 21691398Stmm 21791398Stmm/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 21891398Stmm#define GEM_RX_PTH_XOFF_THRESH 0x000001ff 21999726Sbenno#define GEM_RX_PTH_XON_THRESH 0x001ff000 22091398Stmm 22191398Stmm 22291398Stmm/* GEM_RX_BLANKING register bits */ 22391398Stmm#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 22499726Sbenno#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 22599726Sbenno#define GEM_RX_BLANKING_TIME_SHIFT 12 22699726Sbenno/* One tick is 2048 PCI clocks, or 16us at 66MHz */ 22791398Stmm 22891398Stmm 22991398Stmm/* GEM_MAC registers */ 23091398Stmm#define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 23191398Stmm#define GEM_MAC_RXRESET 0x6004 /* ditto */ 23291398Stmm#define GEM_MAC_SEND_PAUSE_CMD 0x6008 23391398Stmm#define GEM_MAC_TX_STATUS 0x6010 23491398Stmm#define GEM_MAC_RX_STATUS 0x6014 23591398Stmm#define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 23691398Stmm#define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 23791398Stmm#define GEM_MAC_RX_MASK 0x6024 23891398Stmm#define GEM_MAC_CONTROL_MASK 0x6028 23991398Stmm#define GEM_MAC_TX_CONFIG 0x6030 24091398Stmm#define GEM_MAC_RX_CONFIG 0x6034 24191398Stmm#define GEM_MAC_CONTROL_CONFIG 0x6038 24291398Stmm#define GEM_MAC_XIF_CONFIG 0x603c 24391398Stmm#define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 24491398Stmm#define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 24591398Stmm#define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 246172334Smarius#define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 24791398Stmm#define GEM_MAC_MAC_MIN_FRAME 0x6050 24891398Stmm#define GEM_MAC_MAC_MAX_FRAME 0x6054 24991398Stmm#define GEM_MAC_PREAMBLE_LEN 0x6058 25091398Stmm#define GEM_MAC_JAM_SIZE 0x605c 25191398Stmm#define GEM_MAC_ATTEMPT_LIMIT 0x6060 25291398Stmm#define GEM_MAC_CONTROL_TYPE 0x6064 25391398Stmm 25491398Stmm#define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 25591398Stmm#define GEM_MAC_ADDR1 0x6084 25691398Stmm#define GEM_MAC_ADDR2 0x6088 25791398Stmm#define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 25891398Stmm#define GEM_MAC_ADDR4 0x6090 25991398Stmm#define GEM_MAC_ADDR5 0x6094 26091398Stmm#define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 26191398Stmm#define GEM_MAC_ADDR7 0x609c 26291398Stmm#define GEM_MAC_ADDR8 0x60a0 26391398Stmm 26491398Stmm#define GEM_MAC_ADDR_FILTER0 0x60a4 26591398Stmm#define GEM_MAC_ADDR_FILTER1 0x60a8 26691398Stmm#define GEM_MAC_ADDR_FILTER2 0x60ac 26791398Stmm#define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 26891398Stmm#define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 26991398Stmm 27091398Stmm#define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 27191398Stmm#define GEM_MAC_HASH1 0x60c4 27291398Stmm#define GEM_MAC_HASH2 0x60c8 27391398Stmm#define GEM_MAC_HASH3 0x60cc 27491398Stmm#define GEM_MAC_HASH4 0x60d0 27591398Stmm#define GEM_MAC_HASH5 0x60d4 27691398Stmm#define GEM_MAC_HASH6 0x60d8 27791398Stmm#define GEM_MAC_HASH7 0x60dc 27891398Stmm#define GEM_MAC_HASH8 0x60e0 27991398Stmm#define GEM_MAC_HASH9 0x60e4 28091398Stmm#define GEM_MAC_HASH10 0x60e8 28191398Stmm#define GEM_MAC_HASH11 0x60ec 28291398Stmm#define GEM_MAC_HASH12 0x60f0 28391398Stmm#define GEM_MAC_HASH13 0x60f4 28491398Stmm#define GEM_MAC_HASH14 0x60f8 28591398Stmm#define GEM_MAC_HASH15 0x60fc 28691398Stmm 28791398Stmm#define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 28891398Stmm#define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 28991398Stmm#define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 29091398Stmm#define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 29191398Stmm#define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 29291398Stmm#define GEM_MAC_PEAK_ATTEMPTS 0x6114 29391398Stmm#define GEM_MAC_RX_FRAME_COUNT 0x6118 29491398Stmm#define GEM_MAC_RX_LEN_ERR_CNT 0x611c 29591398Stmm#define GEM_MAC_RX_ALIGN_ERR 0x6120 29691398Stmm#define GEM_MAC_RX_CRC_ERR_CNT 0x6124 29791398Stmm#define GEM_MAC_RX_CODE_VIOL 0x6128 29891398Stmm#define GEM_MAC_RANDOM_SEED 0x6130 299172334Smarius#define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */ 30091398Stmm 30191398Stmm 30291398Stmm/* GEM_MAC_SEND_PAUSE_CMD register bits */ 30391398Stmm#define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 30491398Stmm#define GEM_MAC_PAUSE_CMD_SEND 0x00010000 30591398Stmm 30691398Stmm 30791398Stmm/* GEM_MAC_TX_STATUS and _MASK register bits */ 30891398Stmm#define GEM_MAC_TX_XMIT_DONE 0x00000001 30991398Stmm#define GEM_MAC_TX_UNDERRUN 0x00000002 31091398Stmm#define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 31191398Stmm#define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 31291398Stmm#define GEM_MAC_TX_ECC_EXP 0x00000010 31391398Stmm#define GEM_MAC_TX_LCC_EXP 0x00000020 31491398Stmm#define GEM_MAC_TX_FCC_EXP 0x00000040 31591398Stmm#define GEM_MAC_TX_DEFER_EXP 0x00000080 31691398Stmm#define GEM_MAC_TX_PEAK_EXP 0x00000100 31791398Stmm 31891398Stmm 31991398Stmm/* GEM_MAC_RX_STATUS and _MASK register bits */ 32091398Stmm#define GEM_MAC_RX_DONE 0x00000001 32191398Stmm#define GEM_MAC_RX_OVERFLOW 0x00000002 32291398Stmm#define GEM_MAC_RX_FRAME_CNT 0x00000004 32391398Stmm#define GEM_MAC_RX_ALIGN_EXP 0x00000008 32491398Stmm#define GEM_MAC_RX_CRC_EXP 0x00000010 32591398Stmm#define GEM_MAC_RX_LEN_EXP 0x00000020 32691398Stmm#define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 32791398Stmm 32891398Stmm 32991398Stmm/* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 33091398Stmm#define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 33191398Stmm#define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 33291398Stmm#define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 333172334Smarius#define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */ 334172334Smarius#define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 33591398Stmm 336172334Smarius#define GEM_MAC_PAUSE_TIME_SHFT 16 337172334Smarius#define GEM_MAC_PAUSE_TIME(x) \ 338172334Smarius (((x) & GEM_MAC_PAUSE_TIME_SLTS) >> GEM_MAC_PAUSE_TIME_SHFT) 339172334Smarius 34091398Stmm/* GEM_MAC_XIF_CONFIG register bits */ 34191398Stmm#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 34291398Stmm#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 34391398Stmm#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 34499726Sbenno#define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 34591398Stmm#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 34691398Stmm#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 34791398Stmm#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 348172334Smarius#define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 349172334Smarius "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 350172334Smarius "b\6FDLED\0\0" 35191398Stmm 352172334Smarius/* 353172334Smarius * GEM_MAC_SLOT_TIME register 354172334Smarius * The slot time is used as PAUSE time unit, value depends on whether carrier 355172334Smarius * extension is enabled. 356172334Smarius */ 357172334Smarius#define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 358172334Smarius#define GEM_MAC_SLOT_TIME_NORMAL 0x40 359172334Smarius 36091398Stmm/* GEM_MAC_TX_CONFIG register bits */ 36191398Stmm#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 36291398Stmm#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 363172334Smarius#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 364174987Smarius#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ 36591398Stmm#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 36691398Stmm#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 36791398Stmm#define GEM_MAC_TX_NO_BACKOFF 0x00000040 36891398Stmm#define GEM_MAC_TX_SLOWDOWN 0x00000080 36991398Stmm#define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 37091398Stmm#define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 37191398Stmm/* Carrier Extension is required for half duplex Gbps operation */ 372172334Smarius#define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 373172334Smarius "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 374172334Smarius "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 375172334Smarius "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 376172334Smarius "b\x9TXCARREXT\0\0" 37791398Stmm 37891398Stmm 37991398Stmm/* GEM_MAC_RX_CONFIG register bits */ 38091398Stmm#define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 38191398Stmm#define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 38291398Stmm#define GEM_MAC_RX_STRIP_CRC 0x00000004 38391398Stmm#define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 38491398Stmm#define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 38591398Stmm#define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 38691398Stmm#define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 38791398Stmm#define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 38891398Stmm#define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 38991398Stmm/* 39091398Stmm * Carrier Extension enables reception of packet bursts generated by 39191398Stmm * senders with carrier extension enabled. 39291398Stmm */ 393172334Smarius#define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 394172334Smarius "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 395172334Smarius "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 396172334Smarius "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 39791398Stmm 39891398Stmm 39991398Stmm/* GEM_MAC_CONTROL_CONFIG bits */ 40091398Stmm#define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 40191398Stmm#define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 40291398Stmm#define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 403172334Smarius#define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 40491398Stmm 40591398Stmm 40691398Stmm/* GEM MIF registers */ 407174987Smarius/* Bit bang registers use low bit only. */ 40891398Stmm#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 40991398Stmm#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 41091398Stmm#define GEM_MIF_BB_OUTPUT_ENAB 0x6208 41191398Stmm#define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 41291398Stmm#define GEM_MIF_CONFIG 0x6210 41391398Stmm#define GEM_MIF_INTERRUPT_MASK 0x6214 41491398Stmm#define GEM_MIF_BASIC_STATUS 0x6218 41591398Stmm#define GEM_MIF_STATE_MACHINE 0x621c 41691398Stmm 41791398Stmm 41891398Stmm/* GEM_MIF_FRAME bits */ 41991398Stmm#define GEM_MIF_FRAME_DATA 0x0000ffff 42091398Stmm#define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 42191398Stmm#define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 42291398Stmm#define GEM_MIF_FRAME_REG_ADDR 0x007c0000 42391398Stmm#define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */ 42491398Stmm#define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 42591398Stmm#define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 42691398Stmm 42791398Stmm#define GEM_MIF_FRAME_READ 0x60020000 42891398Stmm#define GEM_MIF_FRAME_WRITE 0x50020000 42991398Stmm 43091398Stmm#define GEM_MIF_REG_SHIFT 18 43191398Stmm#define GEM_MIF_PHY_SHIFT 23 43291398Stmm 43391398Stmm 43491398Stmm/* GEM_MIF_CONFIG register bits */ 435172334Smarius#define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */ 43691398Stmm#define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 43791398Stmm#define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 43891398Stmm#define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 43991398Stmm#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ 44091398Stmm#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ 44191398Stmm#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 442174987Smarius/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ 443172334Smarius#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 444172334Smarius "b\x8MDIO0\0b\x9MDIO1\0\0" 44591398Stmm 44691398Stmm 44791398Stmm/* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */ 44891398Stmm#define GEM_MIF_STATUS 0x0000ffff 44991398Stmm#define GEM_MIF_BASIC 0xffff0000 45091398Stmm/* 45191398Stmm * The Basic part is the last value read in the POLL field of the config 45291398Stmm * register. 45391398Stmm * 45491398Stmm * The status part indicates the bits that have changed. 45591398Stmm */ 45691398Stmm 45791398Stmm 458174987Smarius/* GEM PCS/Serial link registers */ 459172334Smarius/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 46091398Stmm#define GEM_MII_CONTROL 0x9000 46191398Stmm#define GEM_MII_STATUS 0x9004 46291398Stmm#define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 463172334Smarius#define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 46491398Stmm#define GEM_MII_CONFIG 0x9010 46591398Stmm#define GEM_MII_STATE_MACHINE 0x9014 466172334Smarius#define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 46791398Stmm#define GEM_MII_DATAPATH_MODE 0x9050 46891398Stmm#define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 46991398Stmm#define GEM_MII_OUTPUT_SELECT 0x9058 47091398Stmm#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */ 47191398Stmm 47291398Stmm 473172334Smarius/* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */ 47491398Stmm#define GEM_MII_CONTROL_RESET 0x00008000 47591398Stmm#define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 47691398Stmm#define GEM_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */ 47791398Stmm#define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 47891398Stmm#define GEM_MII_CONTROL_POWERDN 0x00000800 47991398Stmm#define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */ 480172334Smarius#define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */ 48191398Stmm#define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 48291398Stmm#define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 483172334Smarius#define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 484172334Smarius "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 485172334Smarius "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 48691398Stmm 48791398Stmm 488172334Smarius/* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 48991398Stmm#define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 49091398Stmm#define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 491172334Smarius#define GEM_MII_STATUS_UNK 0x00000100 49291398Stmm#define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */ 49391398Stmm#define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 49491398Stmm#define GEM_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */ 49591398Stmm#define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 49691398Stmm#define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 49791398Stmm#define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */ 498172334Smarius#define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 499172334Smarius "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \ 500172334Smarius "b\xaGBFDX\0\0" 50191398Stmm 50291398Stmm 503172334Smarius/* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 50491398Stmm#define GEM_MII_ANEG_NP 0x00008000 /* next page bit */ 50591398Stmm#define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of */ 50691398Stmm /* Link Partner Capability */ 50791398Stmm#define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */ 50891398Stmm#define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */ 50991398Stmm#define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */ 51091398Stmm#define GEM_MII_ANEG_HLF_DUPLX 0x00000040 51191398Stmm#define GEM_MII_ANEG_FUL_DUPLX 0x00000020 512172334Smarius#define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 513172334Smarius "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 514172334Smarius "\b\xfNPBIT\0\0" 51591398Stmm 51691398Stmm 51791398Stmm/* GEM_MII_CONFIG reg */ 518172334Smarius#define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */ 519172334Smarius#define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */ 520172334Smarius#define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal 521172334Smarius * 1 high freq, 2 low freq */ 522172334Smarius#define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */ 523172334Smarius#define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */ 52491398Stmm#define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 525172334Smarius#define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 52691398Stmm 52791398Stmm 528172334Smarius/* 529172334Smarius * GEM_MII_STATE_MACHINE 530172334Smarius * XXX These are best guesses from observed behavior. 531172334Smarius */ 532172334Smarius#define GEM_MII_FSM_STOP 0x00000000 /* stopped */ 533172334Smarius#define GEM_MII_FSM_RUN 0x00000001 /* running */ 534172334Smarius#define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */ 535172334Smarius#define GEM_MII_FSM_DONE 0x00000101 /* complete */ 536172334Smarius 537172334Smarius 538172334Smarius/* 539172334Smarius * GEM_MII_INTERRUP_STATUS reg 540172334Smarius * No mask register; mask with the global interrupt mask register. 541172334Smarius */ 542172334Smarius#define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 543172334Smarius 544172334Smarius 54591398Stmm/* GEM_MII_DATAPATH_MODE reg */ 54691398Stmm#define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */ 54791398Stmm#define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 548172334Smarius#define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */ 54991398Stmm#define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */ 550172334Smarius#define GEM_MII_DATAPATH_BITS "\177\020" \ 551172334Smarius "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0" 55291398Stmm 55391398Stmm 55491398Stmm/* GEM_MII_SLINK_CONTROL reg */ 555172334Smarius#define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl, logic 556172334Smarius * reversed for SERDES */ 55791398Stmm#define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 55891398Stmm#define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 55991398Stmm#define GEM_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */ 56091398Stmm#define GEM_MII_SLINK_SELFTEST 0x000001c0 56191398Stmm#define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */ 562172334Smarius#define GEM_MII_SLINK_CONTROL_BITS \ 563172334Smarius "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 564172334Smarius "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" 56591398Stmm 56691398Stmm 56791398Stmm/* GEM_MII_SLINK_STATUS reg */ 56891398Stmm#define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 56991398Stmm#define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 57091398Stmm#define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 57191398Stmm#define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 57291398Stmm 573172334Smarius/* 574172334Smarius * PCI Expansion ROM runtime access 575172334Smarius * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 576172334Smarius * of the first register bank, although they only support up to 64KB ROMs. 577172334Smarius */ 578172334Smarius#define GEM_PCI_ROM_OFFSET 0x100000 579172334Smarius#define GEM_PCI_ROM_SIZE 0x10000 58091398Stmm 58191398Stmm/* Wired GEM PHY addresses */ 58291398Stmm#define GEM_PHYAD_INTERNAL 1 58391398Stmm#define GEM_PHYAD_EXTERNAL 0 58491398Stmm 58591398Stmm/* 586174987Smarius * GEM descriptor table structures 58791398Stmm */ 58891398Stmmstruct gem_desc { 58991398Stmm uint64_t gd_flags; 59091398Stmm uint64_t gd_addr; 59191398Stmm}; 59291398Stmm 59391398Stmm/* Transmit flags */ 59491398Stmm#define GEM_TD_BUFSIZE 0x0000000000007fffLL 59591398Stmm#define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 596170273Syongari#define GEM_TD_CXSUM_STARTSHFT 15 59791398Stmm#define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 598170273Syongari#define GEM_TD_CXSUM_STUFFSHFT 21 59991398Stmm#define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 60091398Stmm#define GEM_TD_END_OF_PACKET 0x0000000040000000LL 60191398Stmm#define GEM_TD_START_OF_PACKET 0x0000000080000000LL 60291398Stmm#define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 60391398Stmm#define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 60491398Stmm/* 60591398Stmm * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 60691398Stmm * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 60791398Stmm */ 60891398Stmm 60991398Stmm/* Receive flags */ 610172334Smarius#define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */ 61191398Stmm#define GEM_RD_BUFSIZE 0x000000007fff0000LL 61291398Stmm#define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 61391398Stmm#define GEM_RD_HASHVAL 0x0ffff00000000000LL 61491398Stmm#define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 61591398Stmm#define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 61691398Stmm#define GEM_RD_BAD_CRC 0x4000000000000000LL 61791398Stmm 61891398Stmm#define GEM_RD_BUFSHIFT 16 619172334Smarius#define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 62091398Stmm 62191398Stmm#endif 622