if_gem_pci.c revision 109650
1/* 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: if_gem_pci.c,v 1.7 2001/10/18 15:09:15 thorpej Exp 28 * 29 * $FreeBSD: head/sys/dev/gem/if_gem_pci.c 109650 2003-01-21 17:28:36Z tmm $ 30 */ 31 32/* 33 * PCI bindings for Sun GEM ethernet controllers. 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/resource.h> 42#include <sys/socket.h> 43 44#include <machine/endian.h> 45 46#include <net/ethernet.h> 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51 52#include <machine/bus.h> 53#include <machine/resource.h> 54#include <machine/ofw_machdep.h> 55 56#include <sys/rman.h> 57 58#include <dev/mii/mii.h> 59#include <dev/mii/miivar.h> 60 61#include <dev/gem/if_gemreg.h> 62#include <dev/gem/if_gemvar.h> 63 64#include <dev/pci/pcivar.h> 65#include <dev/pci/pcireg.h> 66 67#include "miibus_if.h" 68 69struct gem_pci_softc { 70 struct gem_softc gsc_gem; /* GEM device */ 71 struct resource *gsc_sres; 72 int gsc_srid; 73 struct resource *gsc_ires; 74 int gsc_irid; 75 void *gsc_ih; 76}; 77 78static int gem_pci_probe(device_t); 79static int gem_pci_attach(device_t); 80static int gem_pci_detach(device_t); 81static int gem_pci_suspend(device_t); 82static int gem_pci_resume(device_t); 83 84static device_method_t gem_pci_methods[] = { 85 /* Device interface */ 86 DEVMETHOD(device_probe, gem_pci_probe), 87 DEVMETHOD(device_attach, gem_pci_attach), 88 DEVMETHOD(device_detach, gem_pci_detach), 89 DEVMETHOD(device_suspend, gem_pci_suspend), 90 DEVMETHOD(device_resume, gem_pci_resume), 91 /* Use the suspend handler here, it is all that is required. */ 92 DEVMETHOD(device_shutdown, gem_pci_suspend), 93 94 /* bus interface */ 95 DEVMETHOD(bus_print_child, bus_generic_print_child), 96 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 97 98 /* MII interface */ 99 DEVMETHOD(miibus_readreg, gem_mii_readreg), 100 DEVMETHOD(miibus_writereg, gem_mii_writereg), 101 DEVMETHOD(miibus_statchg, gem_mii_statchg), 102 103 { 0, 0 } 104}; 105 106static driver_t gem_pci_driver = { 107 "gem", 108 gem_pci_methods, 109 sizeof(struct gem_pci_softc) 110}; 111 112 113DRIVER_MODULE(if_gem, pci, gem_pci_driver, gem_devclass, 0, 0); 114 115struct gem_pci_dev { 116 u_int32_t gpd_devid; 117 int gpd_variant; 118 char *gpd_desc; 119} gem_pci_devlist[] = { 120 { 0x1101108e, GEM_SUN_GEM, "Sun ERI 10/100 Ethernet Adaptor" }, 121 { 0x2bad108e, GEM_SUN_GEM, "Sun GEM Gigabit Ethernet Adaptor" }, 122 { 0x0021106b, GEM_APPLE_GMAC, "Apple GMAC Ethernet Adaptor" }, 123 { 0x0024106b, GEM_APPLE_GMAC, "Apple GMAC2 Ethernet Adaptor" }, 124 { 0, NULL } 125}; 126 127/* 128 * Attach routines need to be split out to different bus-specific files. 129 */ 130static int 131gem_pci_probe(dev) 132 device_t dev; 133{ 134 int i; 135 u_int32_t devid; 136 struct gem_pci_softc *gsc; 137 138 devid = pci_get_devid(dev); 139 for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) { 140 if (devid == gem_pci_devlist[i].gpd_devid) { 141 device_set_desc(dev, gem_pci_devlist[i].gpd_desc); 142 gsc = device_get_softc(dev); 143 gsc->gsc_gem.sc_variant = 144 gem_pci_devlist[i].gpd_variant; 145 return (0); 146 } 147 } 148 149 return (ENXIO); 150} 151 152static int 153gem_pci_attach(dev) 154 device_t dev; 155{ 156 struct gem_pci_softc *gsc = device_get_softc(dev); 157 struct gem_softc *sc = &gsc->gsc_gem; 158 159 /* 160 * Enable bus master and memory access. The firmware does in some 161 * cases not do this for us on sparc64 machines. 162 */ 163 pci_enable_busmaster(dev); 164 pci_enable_io(dev, SYS_RES_MEMORY); 165 166 sc->sc_dev = dev; 167 sc->sc_pci = 1; /* XXX */ 168 169 gsc->gsc_srid = PCI_GEM_BASEADDR; 170 gsc->gsc_sres = bus_alloc_resource(dev, SYS_RES_MEMORY, &gsc->gsc_srid, 171 0, ~0, 1, RF_ACTIVE); 172 if (gsc->gsc_sres == NULL) { 173 device_printf(dev, "failed to allocate bus space resource\n"); 174 return (ENXIO); 175 } 176 177 gsc->gsc_irid = 0; 178 gsc->gsc_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &gsc->gsc_irid, 0, 179 ~0, 1, RF_SHAREABLE | RF_ACTIVE); 180 if (gsc->gsc_ires == NULL) { 181 device_printf(dev, "failed to allocate interrupt resource\n"); 182 goto fail_sres; 183 } 184 185 sc->sc_bustag = rman_get_bustag(gsc->gsc_sres); 186 sc->sc_h = rman_get_bushandle(gsc->gsc_sres); 187 188 /* All platform that this driver is used on must provide this. */ 189 OF_getetheraddr(dev, sc->sc_arpcom.ac_enaddr); 190 191 /* 192 * call the main configure 193 */ 194 if (gem_attach(sc) != 0) { 195 device_printf(dev, "could not be configured\n"); 196 goto fail_ires; 197 } 198 199 if (bus_setup_intr(dev, gsc->gsc_ires, INTR_TYPE_NET, gem_intr, sc, 200 &gsc->gsc_ih) != 0) { 201 device_printf(dev, "failed to set up interrupt\n"); 202 gem_detach(sc); 203 goto fail_ires; 204 } 205 return (0); 206 207fail_ires: 208 bus_release_resource(dev, SYS_RES_IRQ, gsc->gsc_irid, gsc->gsc_ires); 209fail_sres: 210 bus_release_resource(dev, SYS_RES_MEMORY, gsc->gsc_srid, gsc->gsc_sres); 211 return (ENXIO); 212} 213 214static int 215gem_pci_detach(dev) 216 device_t dev; 217{ 218 struct gem_pci_softc *gsc = device_get_softc(dev); 219 struct gem_softc *sc = &gsc->gsc_gem; 220 221 gem_detach(sc); 222 223 bus_teardown_intr(dev, gsc->gsc_ires, gsc->gsc_ih); 224 bus_release_resource(dev, SYS_RES_IRQ, gsc->gsc_irid, gsc->gsc_ires); 225 bus_release_resource(dev, SYS_RES_MEMORY, gsc->gsc_srid, gsc->gsc_sres); 226 return (0); 227} 228 229static int 230gem_pci_suspend(dev) 231 device_t dev; 232{ 233 struct gem_pci_softc *gsc = device_get_softc(dev); 234 struct gem_softc *sc = &gsc->gsc_gem; 235 236 gem_suspend(sc); 237 return (0); 238} 239 240static int 241gem_pci_resume(dev) 242 device_t dev; 243{ 244 struct gem_pci_softc *gsc = device_get_softc(dev); 245 struct gem_softc *sc = &gsc->gsc_gem; 246 247 gem_resume(sc); 248 return (0); 249} 250