if_fxpvar.h revision 112982
133965Sjdp/* 2218822Sdim * Copyright (c) 1995, David Greenman 3218822Sdim * All rights reserved. 460484Sobrien * 533965Sjdp * Redistribution and use in source and binary forms, with or without 633965Sjdp * modification, are permitted provided that the following conditions 733965Sjdp * are met: 833965Sjdp * 1. Redistributions of source code must retain the above copyright 933965Sjdp * notice unmodified, this list of conditions, and the following 1033965Sjdp * disclaimer. 1133965Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1233965Sjdp * notice, this list of conditions and the following disclaimer in the 1333965Sjdp * documentation and/or other materials provided with the distribution. 1433965Sjdp * 1533965Sjdp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1633965Sjdp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1733965Sjdp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1833965Sjdp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1933965Sjdp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2033965Sjdp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21218822Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22218822Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2333965Sjdp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2433965Sjdp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2560484Sobrien * SUCH DAMAGE. 2633965Sjdp * 2733965Sjdp * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 112982 2003-04-02 16:47:16Z mux $ 2860484Sobrien */ 2933965Sjdp 3033965Sjdp/* 3133965Sjdp * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 3233965Sjdp * Ethernet driver 3333965Sjdp */ 3489857Sobrien 3533965Sjdp/* 3633965Sjdp * Number of transmit control blocks. This determines the number 3789857Sobrien * of transmit buffers that can be chained in the CB list. 3833965Sjdp * This must be a power of two. 3933965Sjdp */ 4033965Sjdp#define FXP_NTXCB 128 4133965Sjdp 4233965Sjdp/* 4333965Sjdp * Size of the TxCB list. 4433965Sjdp */ 4533965Sjdp#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx)) 4633965Sjdp 4733965Sjdp/* 4833965Sjdp * Macro to obtain the DMA address of a virtual address in the 4933965Sjdp * TxCB list based on the base DMA address of the TxCB list. 5033965Sjdp */ 5133965Sjdp#define FXP_TXCB_DMA_ADDR(sc, addr) \ 5233965Sjdp (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \ 5333965Sjdp (uintptr_t)sc->fxp_desc.cbl_list) 5433965Sjdp 5533965Sjdp/* 5633965Sjdp * Number of completed TX commands at which point an interrupt 57218822Sdim * will be generated to garbage collect the attached buffers. 58218822Sdim * Must be at least one less than FXP_NTXCB, and should be 59218822Sdim * enough less so that the transmitter doesn't becomes idle 60218822Sdim * during the buffer rundown (which would reduce performance). 6133965Sjdp */ 62218822Sdim#define FXP_CXINT_THRESH 120 63218822Sdim 64218822Sdim/* 65218822Sdim * TxCB list index mask. This is used to do list wrap-around. 66218822Sdim */ 67218822Sdim#define FXP_TXCB_MASK (FXP_NTXCB - 1) 68218822Sdim 6933965Sjdp/* 70218822Sdim * Number of receive frame area buffers. These are large so chose 71218822Sdim * wisely. 72218822Sdim */ 73218822Sdim#ifdef DEVICE_POLLING 74218822Sdim#define FXP_NRFABUFS 192 75218822Sdim#else 76218822Sdim#define FXP_NRFABUFS 64 77218822Sdim#endif 7833965Sjdp 79218822Sdim/* 80218822Sdim * Maximum number of seconds that the receiver can be idle before we 81218822Sdim * assume it's dead and attempt to reset it by reprogramming the 82218822Sdim * multicast filter. This is part of a work-around for a bug in the 83218822Sdim * NIC. See fxp_stats_update(). 84218822Sdim */ 85218822Sdim#define FXP_MAX_RX_IDLE 15 86218822Sdim 87218822Sdim/* 88218822Sdim * Default maximum time, in microseconds, that an interrupt may be delayed 89218822Sdim * in an attempt to coalesce interrupts. This is only effective if the Intel 90218822Sdim * microcode is loaded, and may be changed via either loader tunables or 91218822Sdim * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 92218822Sdim */ 93218822Sdim#define TUNABLE_INT_DELAY 1000 94218822Sdim 95218822Sdim/* 96218822Sdim * Default number of packets that will be bundled, before an interrupt is 97218822Sdim * generated. This is only effective if the Intel microcode is loaded, and 98218822Sdim * may be changed via either loader tunables or sysctl. This may not be 99218822Sdim * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 100218822Sdim * entry in rcvbundl.h. 101218822Sdim */ 102218822Sdim#define TUNABLE_BUNDLE_MAX 6 103218822Sdim 104218822Sdim#if __FreeBSD_version < 500000 105218822Sdim#define FXP_LOCK(_sc) 106218822Sdim#define FXP_UNLOCK(_sc) 107218822Sdim#define mtx_init(a, b, c, d) 108218822Sdim#define mtx_destroy(a) 109218822Sdimstruct mtx { int dummy; }; 110218822Sdim#else 111218822Sdim#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 112218822Sdim#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 113218822Sdim#endif 114218822Sdim 115218822Sdim/* 116218822Sdim * Structures to handle TX and RX descriptors. 117218822Sdim */ 118218822Sdimstruct fxp_rx { 119218822Sdim struct fxp_rx *rx_next; 120218822Sdim struct mbuf *rx_mbuf; 121218822Sdim bus_dmamap_t rx_map; 122218822Sdim u_int32_t rx_addr; 123218822Sdim}; 124218822Sdim 125218822Sdimstruct fxp_tx { 126218822Sdim struct fxp_tx *tx_next; 127218822Sdim struct fxp_cb_tx *tx_cb; 128218822Sdim struct mbuf *tx_mbuf; 129218822Sdim bus_dmamap_t tx_map; 130218822Sdim}; 131218822Sdim 132218822Sdimstruct fxp_desc_list { 133218822Sdim struct fxp_rx rx_list[FXP_NRFABUFS]; 134218822Sdim struct fxp_tx tx_list[FXP_NTXCB]; 135218822Sdim struct fxp_tx mcs_tx; 136218822Sdim struct fxp_rx *rx_head; 137218822Sdim struct fxp_rx *rx_tail; 138218822Sdim struct fxp_tx *tx_first; 139218822Sdim struct fxp_tx *tx_last; 140218822Sdim struct fxp_rfa *rfa_list; 141218822Sdim struct fxp_cb_tx *cbl_list; 142218822Sdim u_int32_t cbl_addr; 143218822Sdim bus_dma_tag_t rx_tag; 144218822Sdim}; 145218822Sdim 146218822Sdim/* 147218822Sdim * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 148218822Sdim * for functional grouping. 149218822Sdim */ 150218822Sdimstruct fxp_softc { 151218822Sdim struct arpcom arpcom; /* per-interface network data */ 152218822Sdim struct resource *mem; /* resource descriptor for registers */ 153218822Sdim int rtp; /* register resource type */ 154218822Sdim int rgd; /* register descriptor in use */ 155218822Sdim struct resource *irq; /* resource descriptor for interrupt */ 156218822Sdim void *ih; /* interrupt handler cookie */ 157218822Sdim struct mtx sc_mtx; 158218822Sdim bus_space_tag_t sc_st; /* bus space tag */ 159218822Sdim bus_space_handle_t sc_sh; /* bus space handle */ 160218822Sdim bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */ 161218822Sdim bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ 162218822Sdim bus_dmamap_t fxp_smap; /* bus DMA map for stats */ 163218822Sdim bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ 164218822Sdim bus_dmamap_t cbl_map; /* DMA map for the TxCB list */ 165218822Sdim bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */ 166218822Sdim bus_dmamap_t mcs_map; /* DMA map for the multicast setup */ 167218822Sdim bus_dmamap_t spare_map; /* spare DMA map */ 168218822Sdim struct fxp_desc_list fxp_desc; /* descriptors management struct */ 169218822Sdim int tx_queued; /* # of active TxCB's */ 170218822Sdim int need_mcsetup; /* multicast filter needs programming */ 171218822Sdim struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 172218822Sdim u_int32_t stats_addr; /* DMA address of the stats structure */ 173218822Sdim int rx_idle_secs; /* # of seconds RX has been idle */ 174218822Sdim struct callout_handle stat_ch; /* Handle for canceling our stat timeout */ 175218822Sdim struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 176218822Sdim u_int32_t mcs_addr; /* DMA address of the multicast cmd */ 177218822Sdim struct ifmedia sc_media; /* media information */ 178218822Sdim device_t miibus; 179218822Sdim device_t dev; 180218822Sdim struct sysctl_ctx_list sysctl_ctx; 181218822Sdim struct sysctl_oid *sysctl_tree; 182218822Sdim int tunable_int_delay; /* interrupt delay value for ucode */ 183218822Sdim int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 184218822Sdim int eeprom_size; /* size of serial EEPROM */ 185218822Sdim int suspended; /* 0 = normal 1 = suspended (APM) */ 186218822Sdim int cu_resume_bug; 187218822Sdim int revision; 188218822Sdim int flags; 189218822Sdim u_int32_t saved_maps[5]; /* pci data */ 190218822Sdim u_int32_t saved_biosaddr; 191218822Sdim u_int8_t saved_intline; 192218822Sdim u_int8_t saved_cachelnsz; 193218822Sdim u_int8_t saved_lattimer; 194218822Sdim u_int8_t rfa_size; 195218822Sdim u_int32_t tx_cmd; 19633965Sjdp}; 197218822Sdim 19833965Sjdp#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 19933965Sjdp#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 20033965Sjdp#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 20133965Sjdp#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 20233965Sjdp#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 20333965Sjdp#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 20460484Sobrien#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ 20533965Sjdp#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 206218822Sdim#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 20733965Sjdp#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ 20833965Sjdp#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ 20933965Sjdp 21033965Sjdp/* Macros to ease CSR access. */ 21133965Sjdp#define CSR_READ_1(sc, reg) \ 21233965Sjdp bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 21333965Sjdp#define CSR_READ_2(sc, reg) \ 214218822Sdim bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 21533965Sjdp#define CSR_READ_4(sc, reg) \ 21633965Sjdp bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 21733965Sjdp#define CSR_WRITE_1(sc, reg, val) \ 21833965Sjdp bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 21933965Sjdp#define CSR_WRITE_2(sc, reg, val) \ 22033965Sjdp bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 22133965Sjdp#define CSR_WRITE_4(sc, reg, val) \ 222218822Sdim bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 22333965Sjdp 22433965Sjdp#define sc_if arpcom.ac_if 22533965Sjdp 22633965Sjdp#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit 22733965Sjdp