if_fxpvar.h revision 276169
1139749Simp/*- 229138Sdg * Copyright (c) 1995, David Greenman 329138Sdg * All rights reserved. 4185269Syongari * 529138Sdg * Redistribution and use in source and binary forms, with or without 629138Sdg * modification, are permitted provided that the following conditions 7185269Syongari * are met: 829138Sdg * 1. Redistributions of source code must retain the above copyright 929138Sdg * notice unmodified, this list of conditions, and the following 10185269Syongari * disclaimer. 1129138Sdg * 2. Redistributions in binary form must reproduce the above copyright 1229138Sdg * notice, this list of conditions and the following disclaimer in the 1329138Sdg * documentation and/or other materials provided with the distribution. 1429138Sdg * 1529138Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1629138Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1729138Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1829138Sdg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1929138Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2029138Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2129138Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2229138Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2329138Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2429138Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2529138Sdg * SUCH DAMAGE. 2629138Sdg * 2750477Speter * $FreeBSD: head/sys/dev/fxp/if_fxpvar.h 276169 2014-12-24 03:49:33Z imp $ 2829138Sdg */ 2929138Sdg 3029138Sdg/* 3129138Sdg * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 3229138Sdg * Ethernet driver 3329138Sdg */ 3474178Sjlemon 3538006Sdg/* 3674178Sjlemon * Number of transmit control blocks. This determines the number 3774178Sjlemon * of transmit buffers that can be chained in the CB list. 3874178Sjlemon * This must be a power of two. 3974178Sjlemon */ 4074178Sjlemon#define FXP_NTXCB 128 41185285Syongari#define FXP_NTXCB_HIWAT ((FXP_NTXCB * 7) / 10) 4274178Sjlemon 4374178Sjlemon/* 44185330Syongari * Maximum size of a DMA segment. 45185330Syongari */ 46185330Syongari#define FXP_TSO_SEGSIZE 4096 47185330Syongari 48185330Syongari/* 49112982Smux * Size of the TxCB list. 50112982Smux */ 51112982Smux#define FXP_TXCB_SZ (FXP_NTXCB * sizeof(struct fxp_cb_tx)) 52112982Smux 53112982Smux/* 54112982Smux * Macro to obtain the DMA address of a virtual address in the 55112982Smux * TxCB list based on the base DMA address of the TxCB list. 56112982Smux */ 57112982Smux#define FXP_TXCB_DMA_ADDR(sc, addr) \ 58112982Smux (sc->fxp_desc.cbl_addr + (uintptr_t)addr - \ 59112982Smux (uintptr_t)sc->fxp_desc.cbl_list) 60112982Smux 61112982Smux/* 6274178Sjlemon * Number of completed TX commands at which point an interrupt 6374178Sjlemon * will be generated to garbage collect the attached buffers. 6474178Sjlemon * Must be at least one less than FXP_NTXCB, and should be 6574178Sjlemon * enough less so that the transmitter doesn't becomes idle 6674178Sjlemon * during the buffer rundown (which would reduce performance). 6774178Sjlemon */ 6874178Sjlemon#define FXP_CXINT_THRESH 120 6974178Sjlemon 7074178Sjlemon/* 7174178Sjlemon * TxCB list index mask. This is used to do list wrap-around. 7274178Sjlemon */ 7374178Sjlemon#define FXP_TXCB_MASK (FXP_NTXCB - 1) 7474178Sjlemon 7574178Sjlemon/* 7674178Sjlemon * Number of receive frame area buffers. These are large so chose 7774178Sjlemon * wisely. 7874178Sjlemon */ 7987902Sluigi#ifdef DEVICE_POLLING 8087902Sluigi#define FXP_NRFABUFS 192 8187902Sluigi#else 8274178Sjlemon#define FXP_NRFABUFS 64 8387902Sluigi#endif 8474178Sjlemon 8574178Sjlemon/* 8674178Sjlemon * Maximum number of seconds that the receiver can be idle before we 8774178Sjlemon * assume it's dead and attempt to reset it by reprogramming the 8874178Sjlemon * multicast filter. This is part of a work-around for a bug in the 8974178Sjlemon * NIC. See fxp_stats_update(). 9074178Sjlemon */ 9174178Sjlemon#define FXP_MAX_RX_IDLE 15 9274178Sjlemon 9385461Sjlemon/* 9485461Sjlemon * Default maximum time, in microseconds, that an interrupt may be delayed 95185269Syongari * in an attempt to coalesce interrupts. This is only effective if the Intel 9685461Sjlemon * microcode is loaded, and may be changed via either loader tunables or 9785461Sjlemon * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 9885461Sjlemon */ 9985461Sjlemon#define TUNABLE_INT_DELAY 1000 10085461Sjlemon 10185461Sjlemon/* 102185269Syongari * Default number of packets that will be bundled, before an interrupt is 10385461Sjlemon * generated. This is only effective if the Intel microcode is loaded, and 104185269Syongari * may be changed via either loader tunables or sysctl. This may not be 10585461Sjlemon * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 10685461Sjlemon * entry in rcvbundl.h. 10785461Sjlemon */ 10885461Sjlemon#define TUNABLE_BUNDLE_MAX 6 10985461Sjlemon 11074178Sjlemon#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 11174178Sjlemon#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 112130020Smux#define FXP_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 11374178Sjlemon 114112982Smux/* 115112982Smux * Structures to handle TX and RX descriptors. 116112982Smux */ 117112982Smuxstruct fxp_rx { 118112982Smux struct fxp_rx *rx_next; 119112982Smux struct mbuf *rx_mbuf; 120112982Smux bus_dmamap_t rx_map; 121143167Smux uint32_t rx_addr; 122112982Smux}; 12374178Sjlemon 124112982Smuxstruct fxp_tx { 125112982Smux struct fxp_tx *tx_next; 126112982Smux struct fxp_cb_tx *tx_cb; 127112982Smux struct mbuf *tx_mbuf; 128112982Smux bus_dmamap_t tx_map; 129112982Smux}; 130112982Smux 131112982Smuxstruct fxp_desc_list { 132112982Smux struct fxp_rx rx_list[FXP_NRFABUFS]; 133112982Smux struct fxp_tx tx_list[FXP_NTXCB]; 134112982Smux struct fxp_tx mcs_tx; 135112982Smux struct fxp_rx *rx_head; 136112982Smux struct fxp_rx *rx_tail; 137112982Smux struct fxp_tx *tx_first; 138112982Smux struct fxp_tx *tx_last; 139112982Smux struct fxp_rfa *rfa_list; 140112982Smux struct fxp_cb_tx *cbl_list; 141143167Smux uint32_t cbl_addr; 142112982Smux bus_dma_tag_t rx_tag; 143112982Smux}; 144112982Smux 145194574Syongaristruct fxp_ident { 146276169Simp uint16_t vendor; 147276169Simp uint16_t device; 148194574Syongari int16_t revid; /* -1 matches anything */ 149194574Syongari uint8_t ich; 150215768Smarius const char *name; 151194574Syongari}; 152194574Syongari 153207832Syongaristruct fxp_hwstats { 154207832Syongari uint32_t tx_good; 155207832Syongari uint32_t tx_maxcols; 156207832Syongari uint32_t tx_latecols; 157207832Syongari uint32_t tx_underruns; 158207832Syongari uint32_t tx_lostcrs; 159207832Syongari uint32_t tx_deffered; 160207832Syongari uint32_t tx_single_collisions; 161207832Syongari uint32_t tx_multiple_collisions; 162207832Syongari uint32_t tx_total_collisions; 163207832Syongari uint32_t tx_pause; 164207832Syongari uint32_t tx_tco; 165207832Syongari uint32_t rx_good; 166207832Syongari uint32_t rx_crc_errors; 167207832Syongari uint32_t rx_alignment_errors; 168207832Syongari uint32_t rx_rnr_errors; 169207832Syongari uint32_t rx_overrun_errors; 170207832Syongari uint32_t rx_cdt_errors; 171207832Syongari uint32_t rx_shortframes; 172207832Syongari uint32_t rx_pause; 173207832Syongari uint32_t rx_controls; 174207832Syongari uint32_t rx_tco; 175207832Syongari}; 176207832Syongari 17774178Sjlemon/* 17838006Sdg * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 17938006Sdg * for functional grouping. 18038006Sdg */ 18129138Sdgstruct fxp_softc { 182266977Smarcel void *ifp; /* per-interface network data */ 183150610Smux struct resource *fxp_res[2]; /* I/O and IRQ resources */ 184150610Smux struct resource_spec *fxp_spec; /* the resource spec we used */ 18545720Speter void *ih; /* interrupt handler cookie */ 186215768Smarius const struct fxp_ident *ident; 18765983Scp struct mtx sc_mtx; 188194569Syongari bus_dma_tag_t fxp_txmtag; /* bus DMA tag for Tx mbufs */ 189194569Syongari bus_dma_tag_t fxp_rxmtag; /* bus DMA tag for Rx mbufs */ 190112982Smux bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */ 191112982Smux bus_dmamap_t fxp_smap; /* bus DMA map for stats */ 192112982Smux bus_dma_tag_t cbl_tag; /* DMA tag for the TxCB list */ 193112982Smux bus_dmamap_t cbl_map; /* DMA map for the TxCB list */ 194112982Smux bus_dma_tag_t mcs_tag; /* DMA tag for the multicast setup */ 195112982Smux bus_dmamap_t mcs_map; /* DMA map for the multicast setup */ 196112982Smux bus_dmamap_t spare_map; /* spare DMA map */ 197112982Smux struct fxp_desc_list fxp_desc; /* descriptors management struct */ 198143243Smux int maxtxseg; /* maximum # of TX segments */ 199185330Syongari int maxsegsize; /* maximum size of a TX segment */ 20031447Sdg int tx_queued; /* # of active TxCB's */ 20129138Sdg struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 202143167Smux uint32_t stats_addr; /* DMA address of the stats structure */ 203207832Syongari struct fxp_hwstats fxp_hwstats; 20431447Sdg int rx_idle_secs; /* # of seconds RX has been idle */ 205119786Ssam struct callout stat_ch; /* stat callout */ 206164771Sglebius int watchdog_timer; /* seconds until chip reset */ 20731447Sdg struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 208143167Smux uint32_t mcs_addr; /* DMA address of the multicast cmd */ 20938006Sdg struct ifmedia sc_media; /* media information */ 21074178Sjlemon device_t miibus; 21174178Sjlemon device_t dev; 21285461Sjlemon int tunable_int_delay; /* interrupt delay value for ucode */ 21385461Sjlemon int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 214130019Smux int rnr; /* RNR events */ 21558715Sdg int eeprom_size; /* size of serial EEPROM */ 216114269Simp int suspended; /* 0 = normal 1 = suspended or dead */ 21776777Sjlemon int cu_resume_bug; 21885461Sjlemon int revision; 21974178Sjlemon int flags; 220194573Syongari int if_flags; 221143167Smux uint8_t rfa_size; 222143167Smux uint32_t tx_cmd; 223233586Syongari uint16_t eeprom[256]; 22429138Sdg}; 22529138Sdg 22674178Sjlemon#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 22774178Sjlemon#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 22874178Sjlemon#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 22974178Sjlemon#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 23074178Sjlemon#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 23174178Sjlemon#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 23276777Sjlemon#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 23385461Sjlemon#define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 234106554Siedowse#define FXP_FLAG_DEFERRED_RNR 0x0200 /* DEVICE_POLLING deferred RNR */ 235111578Swpaul#define FXP_FLAG_EXT_RFA 0x0400 /* extended RFDs for csum offload */ 236129718Syar#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */ 237185329Syongari#define FXP_FLAG_82559_RXCSUM 0x1000 /* 82559 compatible RX checksum */ 238185354Syongari#define FXP_FLAG_WOLCAP 0x2000 /* WOL capability */ 239185354Syongari#define FXP_FLAG_WOL 0x4000 /* WOL active */ 240194571Syongari#define FXP_FLAG_RXBUG 0x8000 /* Rx lock-up bug */ 241233585Syongari#define FXP_FLAG_NO_UCODE 0x10000 /* ucode is not applicable */ 24274178Sjlemon 24329138Sdg/* Macros to ease CSR access. */ 244150610Smux#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg) 245150610Smux#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) 246150610Smux#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg) 247150610Smux#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) 248150610Smux#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) 249150610Smux#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val) 250