if_fxpreg.h revision 233586
1139749Simp/*- 274259Sjlemon * Copyright (c) 1995, David Greenman 374178Sjlemon * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 412510Sdg * All rights reserved. 512510Sdg * 612510Sdg * Redistribution and use in source and binary forms, with or without 712510Sdg * modification, are permitted provided that the following conditions 812510Sdg * are met: 912510Sdg * 1. Redistributions of source code must retain the above copyright 1012510Sdg * notice unmodified, this list of conditions, and the following 1112510Sdg * disclaimer. 1212510Sdg * 2. Redistributions in binary form must reproduce the above copyright 1312510Sdg * notice, this list of conditions and the following disclaimer in the 1412510Sdg * documentation and/or other materials provided with the distribution. 1512510Sdg * 1612510Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1712510Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1812510Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1912510Sdg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2012510Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2112510Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2212510Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2312510Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2412510Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2512510Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2612510Sdg * SUCH DAMAGE. 2712510Sdg * 2850477Speter * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 233586 2012-03-28 01:27:27Z yongari $ 2912510Sdg */ 3012510Sdg 3112510Sdg#define FXP_VENDORID_INTEL 0x8086 3212510Sdg 3312510Sdg#define FXP_PCI_MMBA 0x10 3412510Sdg#define FXP_PCI_IOBA 0x14 3512510Sdg 3629138Sdg/* 3729138Sdg * Control/status registers. 3829138Sdg */ 3929138Sdg#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 4029138Sdg#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 4129138Sdg#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 4229138Sdg#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 4329138Sdg#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 4429138Sdg#define FXP_CSR_PORT 8 /* port (4 bytes) */ 4529138Sdg#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 4629138Sdg#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 4729138Sdg#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48215906Smarius#define FXP_CSR_FC_THRESH 0x19 /* flow control (1 byte) */ 49215906Smarius#define FXP_CSR_FC_STATUS 0x1A /* flow control status (1 byte) */ 50185354Syongari#define FXP_CSR_PMDR 0x1B /* power management driver (1 byte) */ 5182425Sjlemon#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 5212510Sdg 5329138Sdg/* 5429138Sdg * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 5529138Sdg * 56143167Smux * volatile uint8_t :2, 5729138Sdg * scb_rus:4, 5829138Sdg * scb_cus:2; 5929138Sdg */ 6029138Sdg 6122255Sdg#define FXP_PORT_SOFTWARE_RESET 0 6222255Sdg#define FXP_PORT_SELFTEST 1 6322255Sdg#define FXP_PORT_SELECTIVE_RESET 2 6422255Sdg#define FXP_PORT_DUMP 3 6522255Sdg 6612510Sdg#define FXP_SCB_RUS_IDLE 0 6712510Sdg#define FXP_SCB_RUS_SUSPENDED 1 6812510Sdg#define FXP_SCB_RUS_NORESOURCES 2 6912510Sdg#define FXP_SCB_RUS_READY 4 7012510Sdg#define FXP_SCB_RUS_SUSP_NORBDS 9 7112510Sdg#define FXP_SCB_RUS_NORES_NORBDS 10 7212510Sdg#define FXP_SCB_RUS_READY_NORBDS 12 7312510Sdg 7412510Sdg#define FXP_SCB_CUS_IDLE 0 7512510Sdg#define FXP_SCB_CUS_SUSPENDED 1 7612510Sdg#define FXP_SCB_CUS_ACTIVE 2 7712510Sdg 7876526Sjlemon#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 7976526Sjlemon#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 8076526Sjlemon#define FXP_SCB_INTMASK_FCP 0x04 8176526Sjlemon#define FXP_SCB_INTMASK_ER 0x08 8276526Sjlemon#define FXP_SCB_INTMASK_RNR 0x10 8376526Sjlemon#define FXP_SCB_INTMASK_CNA 0x20 8476526Sjlemon#define FXP_SCB_INTMASK_FR 0x40 8576526Sjlemon#define FXP_SCB_INTMASK_CXTNO 0x80 8676526Sjlemon 8776526Sjlemon#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 8876526Sjlemon#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 8912510Sdg#define FXP_SCB_STATACK_SWI 0x04 9012510Sdg#define FXP_SCB_STATACK_MDI 0x08 9112510Sdg#define FXP_SCB_STATACK_RNR 0x10 9212510Sdg#define FXP_SCB_STATACK_CNA 0x20 9312510Sdg#define FXP_SCB_STATACK_FR 0x40 9412510Sdg#define FXP_SCB_STATACK_CXTNO 0x80 9512510Sdg 9612510Sdg#define FXP_SCB_COMMAND_CU_NOP 0x00 9712510Sdg#define FXP_SCB_COMMAND_CU_START 0x10 9812510Sdg#define FXP_SCB_COMMAND_CU_RESUME 0x20 9912510Sdg#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 10012510Sdg#define FXP_SCB_COMMAND_CU_DUMP 0x50 10112510Sdg#define FXP_SCB_COMMAND_CU_BASE 0x60 10212510Sdg#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 10312510Sdg 10412510Sdg#define FXP_SCB_COMMAND_RU_NOP 0 10512510Sdg#define FXP_SCB_COMMAND_RU_START 1 10612510Sdg#define FXP_SCB_COMMAND_RU_RESUME 2 10712510Sdg#define FXP_SCB_COMMAND_RU_ABORT 4 10812510Sdg#define FXP_SCB_COMMAND_RU_LOADHDS 5 10912510Sdg#define FXP_SCB_COMMAND_RU_BASE 6 11012510Sdg#define FXP_SCB_COMMAND_RU_RBDRESUME 7 11112510Sdg 11212510Sdg/* 11312510Sdg * Command block definitions 11412510Sdg */ 11512510Sdgstruct fxp_cb_nop { 116143167Smux uint16_t cb_status; 117143167Smux uint16_t cb_command; 118143167Smux uint32_t link_addr; 11912510Sdg}; 12012510Sdgstruct fxp_cb_ias { 121143167Smux uint16_t cb_status; 122143167Smux uint16_t cb_command; 123143167Smux uint32_t link_addr; 124143167Smux uint8_t macaddr[6]; 12512510Sdg}; 126113151Smux 12712510Sdg/* I hate bit-fields :-( */ 128113151Smux#if BYTE_ORDER == LITTLE_ENDIAN 129113151Smux#define __FXP_BITFIELD2(a, b) a, b 130113151Smux#define __FXP_BITFIELD3(a, b, c) a, b, c 131113151Smux#define __FXP_BITFIELD4(a, b, c, d) a, b, c, d 132113151Smux#define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e 133113151Smux#define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f 134113151Smux#define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g 135113151Smux#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h 136113151Smux#else 137113151Smux#define __FXP_BITFIELD2(a, b) b, a 138113151Smux#define __FXP_BITFIELD3(a, b, c) c, b, a 139113151Smux#define __FXP_BITFIELD4(a, b, c, d) d, c, b, a 140113151Smux#define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a 141113151Smux#define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a 142113151Smux#define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a 143113151Smux#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a 144113151Smux#endif 145113151Smux 14612510Sdgstruct fxp_cb_config { 147143167Smux uint16_t cb_status; 148143167Smux uint16_t cb_command; 149143167Smux uint32_t link_addr; 150113151Smux 151113151Smux /* Bytes 0 - 21 -- common to all i8255x */ 152113183Smux u_int __FXP_BITFIELD2(byte_count:6, :2); 153113183Smux u_int __FXP_BITFIELD3(rx_fifo_limit:4, tx_fifo_limit:3, :1); 154143167Smux uint8_t adaptive_ifs; 155113183Smux u_int __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */ 156113151Smux type_enable:1, /* 8,9 */ 157113151Smux read_align_en:1, /* 8,9 */ 158113151Smux end_wr_on_cl:1, /* 8,9 */ 159113151Smux :4); 160113183Smux u_int __FXP_BITFIELD2(rx_dma_bytecount:7, :1); 161113183Smux u_int __FXP_BITFIELD2(tx_dma_bytecount:7, dma_mbce:1); 162113183Smux u_int __FXP_BITFIELD8(late_scb:1, /* 7 */ 163113151Smux direct_dma_dis:1, /* 8,9 */ 164113151Smux tno_int_or_tco_en:1, /* 7,9 */ 165113151Smux ci_int:1, 166113151Smux ext_txcb_dis:1, /* 8,9 */ 167113151Smux ext_stats_dis:1, /* 8,9 */ 168113151Smux keep_overrun_rx:1, 169113151Smux save_bf:1); 170113183Smux u_int __FXP_BITFIELD6(disc_short_rx:1, 171113151Smux underrun_retry:2, 172113151Smux :2, 173113151Smux ext_rfa:1, /* 550 */ 174113151Smux two_frames:1, /* 8,9 */ 175113151Smux dyn_tbd:1); /* 8,9 */ 176113183Smux u_int __FXP_BITFIELD3(mediatype:1, /* 7 */ 177113151Smux :6, 178113151Smux csma_dis:1); /* 8,9 */ 179113183Smux u_int __FXP_BITFIELD6(tcp_udp_cksum:1, /* 9 */ 180113151Smux :3, 181113151Smux vlan_tco:1, /* 8,9 */ 182113151Smux link_wake_en:1, /* 8,9 */ 183113151Smux arp_wake_en:1, /* 8 */ 184113151Smux mc_wake_en:1); /* 8 */ 185113183Smux u_int __FXP_BITFIELD4(:3, 186113151Smux nsai:1, 187113151Smux preamble_length:2, 188113151Smux loopback:2); 189113183Smux u_int __FXP_BITFIELD2(linear_priority:3, /* 7 */ 190113151Smux :5); 191113183Smux u_int __FXP_BITFIELD3(linear_pri_mode:1, /* 7 */ 192113151Smux :3, 193113151Smux interfrm_spacing:4); 194113183Smux u_int :8; 195113183Smux u_int :8; 196113183Smux u_int __FXP_BITFIELD8(promiscuous:1, 197113151Smux bcast_disable:1, 198113151Smux wait_after_win:1, /* 8,9 */ 199113151Smux :1, 200113151Smux ignore_ul:1, /* 8,9 */ 201113151Smux crc16_en:1, /* 9 */ 202113151Smux :1, 203113151Smux crscdt:1); 204113183Smux u_int fc_delay_lsb:8; /* 8,9 */ 205113183Smux u_int fc_delay_msb:8; /* 8,9 */ 206113183Smux u_int __FXP_BITFIELD6(stripping:1, 207113151Smux padding:1, 208113151Smux rcv_crc_xfer:1, 209113151Smux long_rx_en:1, /* 8,9 */ 210113151Smux pri_fc_thresh:3, /* 8,9 */ 211113151Smux :1); 212113183Smux u_int __FXP_BITFIELD8(ia_wake_en:1, /* 8 */ 213113151Smux magic_pkt_dis:1, /* 8,9,!9ER */ 214113151Smux tx_fc_dis:1, /* 8,9 */ 215113151Smux rx_fc_restop:1, /* 8,9 */ 216113151Smux rx_fc_restart:1, /* 8,9 */ 217113151Smux fc_filter:1, /* 8,9 */ 218113151Smux force_fdx:1, 219113151Smux fdx_pin_en:1); 220113183Smux u_int __FXP_BITFIELD4(:5, 221113151Smux pri_fc_loc:1, /* 8,9 */ 222113151Smux multi_ia:1, 223113151Smux :1); 224113183Smux u_int __FXP_BITFIELD3(:3, mc_all:1, :4); 225113151Smux 226113151Smux /* Bytes 22 - 31 -- i82550 only */ 227113183Smux u_int __FXP_BITFIELD3(gamla_rx:1, 228185540Syongari vlan_strip_en:1, 229113151Smux :6); 230143167Smux uint8_t pad[9]; 23112510Sdg}; 23229974Sdg 23329974Sdg#define MAXMCADDR 80 23429974Sdgstruct fxp_cb_mcs { 235143167Smux uint16_t cb_status; 236143167Smux uint16_t cb_command; 237143167Smux uint32_t link_addr; 238143167Smux uint16_t mc_cnt; 239143167Smux uint8_t mc_addr[MAXMCADDR][6]; 24029974Sdg}; 24129974Sdg 24285460Sjlemon#define MAXUCODESIZE 192 24385460Sjlemonstruct fxp_cb_ucode { 244143167Smux uint16_t cb_status; 245143167Smux uint16_t cb_command; 246143167Smux uint32_t link_addr; 247143167Smux uint32_t ucode[MAXUCODESIZE]; 24885460Sjlemon}; 24985460Sjlemon 25029974Sdg/* 251112982Smux * Number of DMA segments in a TxCB. 25229974Sdg */ 253112982Smux#define FXP_NTXSEG 32 25429974Sdg 25512510Sdgstruct fxp_tbd { 256143167Smux uint32_t tb_addr; 257143167Smux uint32_t tb_size; 25812510Sdg}; 259111578Swpaul 260111578Swpaulstruct fxp_ipcb { 261111578Swpaul /* 262111578Swpaul * The following fields are valid only when 263111578Swpaul * using the IPCB command block for TX checksum offload 264111578Swpaul * (and TCP large send, VLANs, and (I think) IPsec). To use 265111578Swpaul * them, you must enable extended TxCBs (available only 266111578Swpaul * on the 82559 and later) and use the IPCBXMIT command. 267111578Swpaul * Note that Intel defines the IPCB to be 32 bytes long, 268111578Swpaul * the last 8 bytes of which comprise the first entry 269111578Swpaul * in the TBD array (see note below). This means we only 270111578Swpaul * have to define 8 extra bytes here. 271111578Swpaul */ 272143167Smux uint16_t ipcb_schedule_low; 273143167Smux uint8_t ipcb_ip_schedule; 274143167Smux uint8_t ipcb_ip_activation_high; 275143167Smux uint16_t ipcb_vlan_id; 276143167Smux uint8_t ipcb_ip_header_offset; 277143167Smux uint8_t ipcb_tcp_header_offset; 278111578Swpaul}; 279111578Swpaul 28012510Sdgstruct fxp_cb_tx { 281143167Smux uint16_t cb_status; 282143167Smux uint16_t cb_command; 283143167Smux uint32_t link_addr; 284143167Smux uint32_t tbd_array_addr; 285143167Smux uint16_t byte_count; 286143167Smux uint8_t tx_threshold; 287143167Smux uint8_t tbd_number; 288111578Swpaul 28912510Sdg /* 29074259Sjlemon * The following structure isn't actually part of the TxCB, 29174259Sjlemon * unless the extended TxCB feature is being used. In this 292185269Syongari * case, the first two elements of the structure below are 29374259Sjlemon * fetched along with the TxCB. 29412510Sdg */ 295111578Swpaul union { 296115003Smux struct fxp_ipcb ipcb; 297185330Syongari struct fxp_tbd tbd[FXP_NTXSEG + 1]; 298111578Swpaul } tx_cb_u; 29912510Sdg}; 30012510Sdg 301111578Swpaul#define tbd tx_cb_u.tbd 302115003Smux#define ipcb_schedule_low tx_cb_u.ipcb.ipcb_schedule_low 303115003Smux#define ipcb_ip_schedule tx_cb_u.ipcb.ipcb_ip_schedule 304115003Smux#define ipcb_ip_activation_high tx_cb_u.ipcb.ipcb_ip_activation_high 305115003Smux#define ipcb_vlan_id tx_cb_u.ipcb.ipcb_vlan_id 306115003Smux#define ipcb_ip_header_offset tx_cb_u.ipcb.ipcb_ip_header_offset 307115003Smux#define ipcb_tcp_header_offset tx_cb_u.ipcb.ipcb_tcp_header_offset 308111578Swpaul 30912510Sdg/* 310111578Swpaul * IPCB field definitions 311111578Swpaul */ 312111578Swpaul#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 313111578Swpaul#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 314111578Swpaul#define FXP_IPCB_TCP_PACKET 0x40 315111578Swpaul#define FXP_IPCB_LARGESEND_ENABLE 0x80 316111578Swpaul#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 317111578Swpaul#define FXP_IPCB_INSERTVLAN_ENABLE 0x02 318111578Swpaul 319111578Swpaul/* 32012510Sdg * Control Block (CB) definitions 32112510Sdg */ 32212510Sdg 32312510Sdg/* status */ 32412510Sdg#define FXP_CB_STATUS_OK 0x2000 32512510Sdg#define FXP_CB_STATUS_C 0x8000 32612510Sdg/* commands */ 32712510Sdg#define FXP_CB_COMMAND_NOP 0x0 32812510Sdg#define FXP_CB_COMMAND_IAS 0x1 32912510Sdg#define FXP_CB_COMMAND_CONFIG 0x2 33029974Sdg#define FXP_CB_COMMAND_MCAS 0x3 33112510Sdg#define FXP_CB_COMMAND_XMIT 0x4 33285460Sjlemon#define FXP_CB_COMMAND_UCODE 0x5 33312510Sdg#define FXP_CB_COMMAND_DUMP 0x6 33412510Sdg#define FXP_CB_COMMAND_DIAG 0x7 335111578Swpaul#define FXP_CB_COMMAND_LOADFILT 0x8 336111578Swpaul#define FXP_CB_COMMAND_IPCBXMIT 0x9 337111578Swpaul 33812510Sdg/* command flags */ 33912510Sdg#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 34012510Sdg#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 34112510Sdg#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 34212510Sdg#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 34312510Sdg 34412510Sdg/* 34512510Sdg * RFA definitions 34612510Sdg */ 34712510Sdg 34812510Sdgstruct fxp_rfa { 349143167Smux uint16_t rfa_status; 350143167Smux uint16_t rfa_control; 351143167Smux uint32_t link_addr; 352143167Smux uint32_t rbd_addr; 353143167Smux uint16_t actual_size; 354143167Smux uint16_t size; 355111578Swpaul 356111578Swpaul /* 357111578Swpaul * The following fields are only available when using 358111578Swpaul * extended receive mode on an 82550/82551 chipset. 359111578Swpaul */ 360143167Smux uint16_t rfax_vlan_id; 361143167Smux uint8_t rfax_rx_parser_sts; 362143167Smux uint8_t rfax_rsvd0; 363143167Smux uint16_t rfax_security_sts; 364143167Smux uint8_t rfax_csum_sts; 365143167Smux uint8_t rfax_zerocopy_sts; 366143167Smux uint8_t rfax_pad[8]; 367114950Smux} __packed; 368111578Swpaul#define FXP_RFAX_LEN 16 369111578Swpaul 37012510Sdg#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 37112510Sdg#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 372111578Swpaul#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 373111578Swpaul#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 37412510Sdg#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 37512510Sdg#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 37612510Sdg#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 37712510Sdg#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 37812510Sdg#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 37912510Sdg#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 38012510Sdg#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 381185540Syongari#define FXP_RFA_STATUS_VLAN 0x1000 /* VLAN tagged frame */ 38212510Sdg#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 38312510Sdg#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 38412510Sdg#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 38512510Sdg#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 38612510Sdg#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 38712510Sdg#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 38812510Sdg 389111578Swpaul/* Bits in the 'csum_sts' byte */ 390111578Swpaul#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 391111578Swpaul#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 392111578Swpaul#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 393111578Swpaul#define FXP_RFDX_CS_IP_CSUM_VALID 0x02 394111578Swpaul 395111578Swpaul/* Bits in the 'packet parser' byte */ 396111578Swpaul#define FXP_RFDX_P_PARSE_BIT 0x08 397111578Swpaul#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 398111578Swpaul#define FXP_RFDX_P_TCP_PACKET 0x00 399111578Swpaul#define FXP_RFDX_P_UDP_PACKET 0x01 400111578Swpaul#define FXP_RFDX_P_IP_PACKET 0x03 401111578Swpaul 40212510Sdg/* 40312510Sdg * Statistics dump area definitions 40412510Sdg */ 40512510Sdgstruct fxp_stats { 406143167Smux uint32_t tx_good; 407143167Smux uint32_t tx_maxcols; 408143167Smux uint32_t tx_latecols; 409143167Smux uint32_t tx_underruns; 410143167Smux uint32_t tx_lostcrs; 411143167Smux uint32_t tx_deffered; 412143167Smux uint32_t tx_single_collisions; 413143167Smux uint32_t tx_multiple_collisions; 414143167Smux uint32_t tx_total_collisions; 415143167Smux uint32_t rx_good; 416143167Smux uint32_t rx_crc_errors; 417143167Smux uint32_t rx_alignment_errors; 418143167Smux uint32_t rx_rnr_errors; 419143167Smux uint32_t rx_overrun_errors; 420143167Smux uint32_t rx_cdt_errors; 421143167Smux uint32_t rx_shortframes; 422207832Syongari uint32_t tx_pause; 423207832Syongari uint32_t rx_pause; 424207832Syongari uint32_t rx_controls; 425207832Syongari uint16_t tx_tco; 426207832Syongari uint16_t rx_tco; 427143167Smux uint32_t completion_status; 428207832Syongari uint32_t reserved0; 429207832Syongari uint32_t reserved1; 430207832Syongari uint32_t reserved2; 43112510Sdg}; 43212510Sdg#define FXP_STATS_DUMP_COMPLETE 0xa005 43312510Sdg#define FXP_STATS_DR_COMPLETE 0xa007 434185269Syongari 43512510Sdg/* 43612510Sdg * Serial EEPROM control register bits 43712510Sdg */ 43874178Sjlemon#define FXP_EEPROM_EESK 0x01 /* shift clock */ 43974178Sjlemon#define FXP_EEPROM_EECS 0x02 /* chip select */ 44074178Sjlemon#define FXP_EEPROM_EEDI 0x04 /* data in */ 44174178Sjlemon#define FXP_EEPROM_EEDO 0x08 /* data out */ 44212510Sdg 44312510Sdg/* 44412510Sdg * Serial EEPROM opcodes, including start bit 44512510Sdg */ 44612510Sdg#define FXP_EEPROM_OPC_ERASE 0x4 44712510Sdg#define FXP_EEPROM_OPC_WRITE 0x5 44812510Sdg#define FXP_EEPROM_OPC_READ 0x6 44923964Sdg 45023964Sdg/* 451233586Syongari * EEPROM map 452233586Syongari */ 453233586Syongari#define FXP_EEPROM_MAP_IA0 0x00 /* Station address */ 454233586Syongari#define FXP_EEPROM_MAP_IA1 0x01 455233586Syongari#define FXP_EEPROM_MAP_IA2 0x02 456233586Syongari#define FXP_EEPROM_MAP_COMPAT 0x03 /* Compatibility */ 457233586Syongari#define FXP_EEPROM_MAP_CNTR 0x05 /* Controller/connector type */ 458233586Syongari#define FXP_EEPROM_MAP_PRI_PHY 0x06 /* Primary PHY record */ 459233586Syongari#define FXP_EEPROM_MAP_SEC_PHY 0x07 /* Secondary PHY record */ 460233586Syongari#define FXP_EEPROM_MAP_PWA0 0x08 /* Printed wire assembly num. */ 461233586Syongari#define FXP_EEPROM_MAP_PWA1 0x09 /* Printed wire assembly num. */ 462233586Syongari#define FXP_EEPROM_MAP_ID 0x0A /* EEPROM ID */ 463233586Syongari#define FXP_EEPROM_MAP_SUBSYS 0x0B /* Subsystem ID */ 464233586Syongari#define FXP_EEPROM_MAP_SUBVEN 0x0C /* Subsystem vendor ID */ 465233586Syongari#define FXP_EEPROM_MAP_CKSUM64 0x3F /* 64-word EEPROM checksum */ 466233586Syongari#define FXP_EEPROM_MAP_CKSUM256 0xFF /* 256-word EEPROM checksum */ 467233586Syongari 468233586Syongari/* 46923964Sdg * Management Data Interface opcodes 47023964Sdg */ 47123964Sdg#define FXP_MDI_WRITE 0x1 47223964Sdg#define FXP_MDI_READ 0x2 47323964Sdg 47423964Sdg/* 47523964Sdg * PHY device types 47623964Sdg */ 47776630Sjlemon#define FXP_PHY_DEVICE_MASK 0x3f00 47874178Sjlemon#define FXP_PHY_SERIAL_ONLY 0x8000 47923964Sdg#define FXP_PHY_NONE 0 48023964Sdg#define FXP_PHY_82553A 1 48123964Sdg#define FXP_PHY_82553C 2 48223964Sdg#define FXP_PHY_82503 3 48323964Sdg#define FXP_PHY_DP83840 4 48423964Sdg#define FXP_PHY_80C240 5 48523964Sdg#define FXP_PHY_80C24 6 48626623Sdg#define FXP_PHY_82555 7 48724079Sdg#define FXP_PHY_DP83840A 10 48834014Sdg#define FXP_PHY_82555B 11 48985460Sjlemon 49085460Sjlemon/* 49185460Sjlemon * Chip revision values. 49285460Sjlemon */ 49385460Sjlemon#define FXP_REV_82557 1 /* catchall 82557 chip type */ 49485460Sjlemon#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 49585460Sjlemon#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 49685460Sjlemon#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 49785460Sjlemon#define FXP_REV_82559S_A 9 /* 82559S A stepping */ 49885460Sjlemon#define FXP_REV_82550 12 49985460Sjlemon#define FXP_REV_82550_C 13 /* 82550 C stepping */ 500145401Smux#define FXP_REV_82551_E 14 /* 82551 */ 501145401Smux#define FXP_REV_82551_F 15 /* 82551 */ 502145401Smux#define FXP_REV_82551_10 16 /* 82551 */ 503