if_fxpreg.h revision 113151
112510Sdg/* 274259Sjlemon * Copyright (c) 1995, David Greenman 374178Sjlemon * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 412510Sdg * All rights reserved. 512510Sdg * 612510Sdg * Redistribution and use in source and binary forms, with or without 712510Sdg * modification, are permitted provided that the following conditions 812510Sdg * are met: 912510Sdg * 1. Redistributions of source code must retain the above copyright 1012510Sdg * notice unmodified, this list of conditions, and the following 1112510Sdg * disclaimer. 1212510Sdg * 2. Redistributions in binary form must reproduce the above copyright 1312510Sdg * notice, this list of conditions and the following disclaimer in the 1412510Sdg * documentation and/or other materials provided with the distribution. 1512510Sdg * 1612510Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1712510Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1812510Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1912510Sdg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2012510Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2112510Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2212510Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2312510Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2412510Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2512510Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2612510Sdg * SUCH DAMAGE. 2712510Sdg * 2850477Speter * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 113151 2003-04-05 23:46:58Z mux $ 2912510Sdg */ 3012510Sdg 3112510Sdg#define FXP_VENDORID_INTEL 0x8086 3212510Sdg 3312510Sdg#define FXP_PCI_MMBA 0x10 3412510Sdg#define FXP_PCI_IOBA 0x14 3512510Sdg 3629138Sdg/* 3729138Sdg * Control/status registers. 3829138Sdg */ 3929138Sdg#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 4029138Sdg#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 4129138Sdg#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 4229138Sdg#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 4329138Sdg#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 4429138Sdg#define FXP_CSR_PORT 8 /* port (4 bytes) */ 4529138Sdg#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 4629138Sdg#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 4729138Sdg#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 4876526Sjlemon#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 4982425Sjlemon#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 5012510Sdg 5129138Sdg/* 5229138Sdg * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 5329138Sdg * 5429138Sdg * volatile u_int8_t :2, 5529138Sdg * scb_rus:4, 5629138Sdg * scb_cus:2; 5729138Sdg */ 5829138Sdg 5922255Sdg#define FXP_PORT_SOFTWARE_RESET 0 6022255Sdg#define FXP_PORT_SELFTEST 1 6122255Sdg#define FXP_PORT_SELECTIVE_RESET 2 6222255Sdg#define FXP_PORT_DUMP 3 6322255Sdg 6412510Sdg#define FXP_SCB_RUS_IDLE 0 6512510Sdg#define FXP_SCB_RUS_SUSPENDED 1 6612510Sdg#define FXP_SCB_RUS_NORESOURCES 2 6712510Sdg#define FXP_SCB_RUS_READY 4 6812510Sdg#define FXP_SCB_RUS_SUSP_NORBDS 9 6912510Sdg#define FXP_SCB_RUS_NORES_NORBDS 10 7012510Sdg#define FXP_SCB_RUS_READY_NORBDS 12 7112510Sdg 7212510Sdg#define FXP_SCB_CUS_IDLE 0 7312510Sdg#define FXP_SCB_CUS_SUSPENDED 1 7412510Sdg#define FXP_SCB_CUS_ACTIVE 2 7512510Sdg 7676526Sjlemon#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 7776526Sjlemon#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 7876526Sjlemon#define FXP_SCB_INTMASK_FCP 0x04 7976526Sjlemon#define FXP_SCB_INTMASK_ER 0x08 8076526Sjlemon#define FXP_SCB_INTMASK_RNR 0x10 8176526Sjlemon#define FXP_SCB_INTMASK_CNA 0x20 8276526Sjlemon#define FXP_SCB_INTMASK_FR 0x40 8376526Sjlemon#define FXP_SCB_INTMASK_CXTNO 0x80 8476526Sjlemon 8576526Sjlemon#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 8676526Sjlemon#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 8712510Sdg#define FXP_SCB_STATACK_SWI 0x04 8812510Sdg#define FXP_SCB_STATACK_MDI 0x08 8912510Sdg#define FXP_SCB_STATACK_RNR 0x10 9012510Sdg#define FXP_SCB_STATACK_CNA 0x20 9112510Sdg#define FXP_SCB_STATACK_FR 0x40 9212510Sdg#define FXP_SCB_STATACK_CXTNO 0x80 9312510Sdg 9412510Sdg#define FXP_SCB_COMMAND_CU_NOP 0x00 9512510Sdg#define FXP_SCB_COMMAND_CU_START 0x10 9612510Sdg#define FXP_SCB_COMMAND_CU_RESUME 0x20 9712510Sdg#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 9812510Sdg#define FXP_SCB_COMMAND_CU_DUMP 0x50 9912510Sdg#define FXP_SCB_COMMAND_CU_BASE 0x60 10012510Sdg#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 10112510Sdg 10212510Sdg#define FXP_SCB_COMMAND_RU_NOP 0 10312510Sdg#define FXP_SCB_COMMAND_RU_START 1 10412510Sdg#define FXP_SCB_COMMAND_RU_RESUME 2 10512510Sdg#define FXP_SCB_COMMAND_RU_ABORT 4 10612510Sdg#define FXP_SCB_COMMAND_RU_LOADHDS 5 10712510Sdg#define FXP_SCB_COMMAND_RU_BASE 6 10812510Sdg#define FXP_SCB_COMMAND_RU_RBDRESUME 7 10912510Sdg 11012510Sdg/* 11112510Sdg * Command block definitions 11212510Sdg */ 11312510Sdgstruct fxp_cb_nop { 114113017Smux u_int16_t cb_status; 115113017Smux u_int16_t cb_command; 116113017Smux u_int32_t link_addr; 11712510Sdg}; 11812510Sdgstruct fxp_cb_ias { 119113017Smux u_int16_t cb_status; 120113017Smux u_int16_t cb_command; 121113017Smux u_int32_t link_addr; 122113017Smux u_int8_t macaddr[6]; 12312510Sdg}; 124113151Smux 12512510Sdg/* I hate bit-fields :-( */ 126113151Smux#if BYTE_ORDER == LITTLE_ENDIAN 127113151Smux#define __FXP_BITFIELD2(a, b) a, b 128113151Smux#define __FXP_BITFIELD3(a, b, c) a, b, c 129113151Smux#define __FXP_BITFIELD4(a, b, c, d) a, b, c, d 130113151Smux#define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e 131113151Smux#define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f 132113151Smux#define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g 133113151Smux#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h 134113151Smux#else 135113151Smux#define __FXP_BITFIELD2(a, b) b, a 136113151Smux#define __FXP_BITFIELD3(a, b, c) c, b, a 137113151Smux#define __FXP_BITFIELD4(a, b, c, d) d, c, b, a 138113151Smux#define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a 139113151Smux#define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a 140113151Smux#define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a 141113151Smux#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a 142113151Smux#endif 143113151Smux 14412510Sdgstruct fxp_cb_config { 145113017Smux u_int16_t cb_status; 146113017Smux u_int16_t cb_command; 147113017Smux u_int32_t link_addr; 148113151Smux 149113151Smux /* Bytes 0 - 21 -- common to all i8255x */ 150113151Smux u_int8_t __FXP_BITFIELD2(byte_count:6, :2); 151113151Smux u_int8_t __FXP_BITFIELD3(rx_fifo_limit:4, tx_fifo_limit:3, :1); 152113017Smux u_int8_t adaptive_ifs; 153113151Smux u_int8_t __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */ 154113151Smux type_enable:1, /* 8,9 */ 155113151Smux read_align_en:1, /* 8,9 */ 156113151Smux end_wr_on_cl:1, /* 8,9 */ 157113151Smux :4); 158113151Smux u_int8_t __FXP_BITFIELD2(rx_dma_bytecount:7, :1); 159113151Smux u_int8_t __FXP_BITFIELD2(tx_dma_bytecount:7, dma_mbce:1); 160113151Smux u_int8_t __FXP_BITFIELD8(late_scb:1, /* 7 */ 161113151Smux direct_dma_dis:1, /* 8,9 */ 162113151Smux tno_int_or_tco_en:1, /* 7,9 */ 163113151Smux ci_int:1, 164113151Smux ext_txcb_dis:1, /* 8,9 */ 165113151Smux ext_stats_dis:1, /* 8,9 */ 166113151Smux keep_overrun_rx:1, 167113151Smux save_bf:1); 168113151Smux u_int8_t __FXP_BITFIELD6(disc_short_rx:1, 169113151Smux underrun_retry:2, 170113151Smux :2, 171113151Smux ext_rfa:1, /* 550 */ 172113151Smux two_frames:1, /* 8,9 */ 173113151Smux dyn_tbd:1); /* 8,9 */ 174113151Smux u_int8_t __FXP_BITFIELD3(mediatype:1, /* 7 */ 175113151Smux :6, 176113151Smux csma_dis:1); /* 8,9 */ 177113151Smux u_int8_t __FXP_BITFIELD6(tcp_udp_cksum:1, /* 9 */ 178113151Smux :3, 179113151Smux vlan_tco:1, /* 8,9 */ 180113151Smux link_wake_en:1, /* 8,9 */ 181113151Smux arp_wake_en:1, /* 8 */ 182113151Smux mc_wake_en:1); /* 8 */ 183113151Smux u_int8_t __FXP_BITFIELD4(:3, 184113151Smux nsai:1, 185113151Smux preamble_length:2, 186113151Smux loopback:2); 187113151Smux u_int8_t __FXP_BITFIELD2(linear_priority:3, /* 7 */ 188113151Smux :5); 189113151Smux u_int8_t __FXP_BITFIELD3(linear_pri_mode:1, /* 7 */ 190113151Smux :3, 191113151Smux interfrm_spacing:4); 192113151Smux u_int8_t :8; 193113151Smux u_int8_t :8; 194113151Smux u_int8_t __FXP_BITFIELD8(promiscuous:1, 195113151Smux bcast_disable:1, 196113151Smux wait_after_win:1, /* 8,9 */ 197113151Smux :1, 198113151Smux ignore_ul:1, /* 8,9 */ 199113151Smux crc16_en:1, /* 9 */ 200113151Smux :1, 201113151Smux crscdt:1); 202113151Smux u_int8_t fc_delay_lsb:8; /* 8,9 */ 203113151Smux u_int8_t fc_delay_msb:8; /* 8,9 */ 204113151Smux u_int8_t __FXP_BITFIELD6(stripping:1, 205113151Smux padding:1, 206113151Smux rcv_crc_xfer:1, 207113151Smux long_rx_en:1, /* 8,9 */ 208113151Smux pri_fc_thresh:3, /* 8,9 */ 209113151Smux :1); 210113151Smux u_int8_t __FXP_BITFIELD8(ia_wake_en:1, /* 8 */ 211113151Smux magic_pkt_dis:1, /* 8,9,!9ER */ 212113151Smux tx_fc_dis:1, /* 8,9 */ 213113151Smux rx_fc_restop:1, /* 8,9 */ 214113151Smux rx_fc_restart:1, /* 8,9 */ 215113151Smux fc_filter:1, /* 8,9 */ 216113151Smux force_fdx:1, 217113151Smux fdx_pin_en:1); 218113151Smux u_int8_t __FXP_BITFIELD4(:5, 219113151Smux pri_fc_loc:1, /* 8,9 */ 220113151Smux multi_ia:1, 221113151Smux :1); 222113151Smux u_int8_t __FXP_BITFIELD3(:3, mc_all:1, :4); 223113151Smux 224113151Smux /* Bytes 22 - 31 -- i82550 only */ 225113151Smux u_int8_t __FXP_BITFIELD3(gamla_rx:1, 226113151Smux vlan_drop_en:1, 227113151Smux :6); 228113151Smux u_int8_t pad[9]; 22912510Sdg}; 23029974Sdg 23129974Sdg#define MAXMCADDR 80 23229974Sdgstruct fxp_cb_mcs { 233113017Smux u_int16_t cb_status; 234113017Smux u_int16_t cb_command; 235113017Smux u_int32_t link_addr; 236113017Smux u_int16_t mc_cnt; 237113017Smux u_int8_t mc_addr[MAXMCADDR][6]; 23829974Sdg}; 23929974Sdg 24085460Sjlemon#define MAXUCODESIZE 192 24185460Sjlemonstruct fxp_cb_ucode { 24285460Sjlemon u_int16_t cb_status; 24385460Sjlemon u_int16_t cb_command; 24485460Sjlemon u_int32_t link_addr; 24585460Sjlemon u_int32_t ucode[MAXUCODESIZE]; 24685460Sjlemon}; 24785460Sjlemon 24829974Sdg/* 249112982Smux * Number of DMA segments in a TxCB. 25029974Sdg */ 251112982Smux#define FXP_NTXSEG 32 25229974Sdg 25312510Sdgstruct fxp_tbd { 254113017Smux u_int32_t tb_addr; 255113017Smux u_int32_t tb_size; 25612510Sdg}; 257111578Swpaul 258111578Swpaulstruct fxp_ipcb { 259111578Swpaul /* 260111578Swpaul * The following fields are valid only when 261111578Swpaul * using the IPCB command block for TX checksum offload 262111578Swpaul * (and TCP large send, VLANs, and (I think) IPsec). To use 263111578Swpaul * them, you must enable extended TxCBs (available only 264111578Swpaul * on the 82559 and later) and use the IPCBXMIT command. 265111578Swpaul * Note that Intel defines the IPCB to be 32 bytes long, 266111578Swpaul * the last 8 bytes of which comprise the first entry 267111578Swpaul * in the TBD array (see note below). This means we only 268111578Swpaul * have to define 8 extra bytes here. 269111578Swpaul */ 270113017Smux u_int16_t ipcb_schedule_low; 271113017Smux u_int8_t ipcb_ip_schedule; 272113017Smux u_int8_t ipcb_ip_activation_high; 273113017Smux u_int16_t ipcb_vlan_id; 274113017Smux u_int8_t ipcb_ip_header_offset; 275113017Smux u_int8_t ipcb_tcp_header_offset; 276111578Swpaul}; 277111578Swpaul 27812510Sdgstruct fxp_cb_tx { 279113017Smux u_int16_t cb_status; 280113017Smux u_int16_t cb_command; 281113017Smux u_int32_t link_addr; 282113017Smux u_int32_t tbd_array_addr; 283113017Smux u_int16_t byte_count; 284113017Smux u_int8_t tx_threshold; 285113017Smux u_int8_t tbd_number; 286111578Swpaul 28712510Sdg /* 28874259Sjlemon * The following structure isn't actually part of the TxCB, 28974259Sjlemon * unless the extended TxCB feature is being used. In this 29074259Sjlemon * case, the first two elements of the structure below are 29174259Sjlemon * fetched along with the TxCB. 29212510Sdg */ 293111578Swpaul union { 294113017Smux struct fxp_ipcb; 295113017Smux struct fxp_tbd tbd[FXP_NTXSEG]; 296111578Swpaul } tx_cb_u; 29712510Sdg}; 29812510Sdg 299111578Swpaul#define tbd tx_cb_u.tbd 300111578Swpaul#define ipcb_schedule_low tx_cb_u.ipcb_schedule_low 301111578Swpaul#define ipcb_ip_schedule tx_cb_u.ipcb_ip_schedule 302111578Swpaul#define ipcb_ip_activation_high tx_cb_u.ipcb_ip_activation_high 303111578Swpaul#define ipcb_vlan_id tx_cb_u.ipcb_vlan_id 304111578Swpaul#define ipcb_ip_header_offset tx_cb_u.ipcb_ip_header_offset 305111578Swpaul#define ipcb_tcp_header_offset tx_cb_u.ipcb_tcp_header_offset 306111578Swpaul 30712510Sdg/* 308111578Swpaul * IPCB field definitions 309111578Swpaul */ 310111578Swpaul#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 311111578Swpaul#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 312111578Swpaul#define FXP_IPCB_TCP_PACKET 0x40 313111578Swpaul#define FXP_IPCB_LARGESEND_ENABLE 0x80 314111578Swpaul#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 315111578Swpaul#define FXP_IPCB_INSERTVLAN_ENABLE 0x02 316111578Swpaul 317111578Swpaul/* 31812510Sdg * Control Block (CB) definitions 31912510Sdg */ 32012510Sdg 32112510Sdg/* status */ 32212510Sdg#define FXP_CB_STATUS_OK 0x2000 32312510Sdg#define FXP_CB_STATUS_C 0x8000 32412510Sdg/* commands */ 32512510Sdg#define FXP_CB_COMMAND_NOP 0x0 32612510Sdg#define FXP_CB_COMMAND_IAS 0x1 32712510Sdg#define FXP_CB_COMMAND_CONFIG 0x2 32829974Sdg#define FXP_CB_COMMAND_MCAS 0x3 32912510Sdg#define FXP_CB_COMMAND_XMIT 0x4 33085460Sjlemon#define FXP_CB_COMMAND_UCODE 0x5 33112510Sdg#define FXP_CB_COMMAND_DUMP 0x6 33212510Sdg#define FXP_CB_COMMAND_DIAG 0x7 333111578Swpaul#define FXP_CB_COMMAND_LOADFILT 0x8 334111578Swpaul#define FXP_CB_COMMAND_IPCBXMIT 0x9 335111578Swpaul 33612510Sdg/* command flags */ 33712510Sdg#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 33812510Sdg#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 33912510Sdg#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 34012510Sdg#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 34112510Sdg 34212510Sdg/* 34312510Sdg * RFA definitions 34412510Sdg */ 34512510Sdg 34612510Sdgstruct fxp_rfa { 347113017Smux u_int16_t rfa_status; 348113017Smux u_int16_t rfa_control; 349113026Smux u_int8_t link_addr[4]; 350113026Smux u_int8_t rbd_addr[4]; 351113017Smux u_int16_t actual_size; 352113017Smux u_int16_t size; 353111578Swpaul 354111578Swpaul /* 355111578Swpaul * The following fields are only available when using 356111578Swpaul * extended receive mode on an 82550/82551 chipset. 357111578Swpaul */ 358113017Smux u_int16_t rfax_vlan_id; 359113017Smux u_int8_t rfax_rx_parser_sts; 360113017Smux u_int8_t rfax_rsvd0; 361113017Smux u_int16_t rfax_security_sts; 362113017Smux u_int8_t rfax_csum_sts; 363113017Smux u_int8_t rfax_zerocopy_sts; 364113017Smux u_int8_t rfax_pad[8]; 36512510Sdg}; 366111578Swpaul#define FXP_RFAX_LEN 16 367111578Swpaul 36812510Sdg#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 36912510Sdg#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 370111578Swpaul#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 371111578Swpaul#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 37212510Sdg#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 37312510Sdg#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 37412510Sdg#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 37512510Sdg#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 37612510Sdg#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 37712510Sdg#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 37812510Sdg#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 37912510Sdg#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 38012510Sdg#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 38112510Sdg#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 38212510Sdg#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 38312510Sdg#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 38412510Sdg#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 38512510Sdg 386111578Swpaul/* Bits in the 'csum_sts' byte */ 387111578Swpaul#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 388111578Swpaul#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 389111578Swpaul#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 390111578Swpaul#define FXP_RFDX_CS_IP_CSUM_VALID 0x02 391111578Swpaul 392111578Swpaul/* Bits in the 'packet parser' byte */ 393111578Swpaul#define FXP_RFDX_P_PARSE_BIT 0x08 394111578Swpaul#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 395111578Swpaul#define FXP_RFDX_P_TCP_PACKET 0x00 396111578Swpaul#define FXP_RFDX_P_UDP_PACKET 0x01 397111578Swpaul#define FXP_RFDX_P_IP_PACKET 0x03 398111578Swpaul 39912510Sdg/* 40012510Sdg * Statistics dump area definitions 40112510Sdg */ 40212510Sdgstruct fxp_stats { 403113017Smux u_int32_t tx_good; 404113017Smux u_int32_t tx_maxcols; 405113017Smux u_int32_t tx_latecols; 406113017Smux u_int32_t tx_underruns; 407113017Smux u_int32_t tx_lostcrs; 408113017Smux u_int32_t tx_deffered; 409113017Smux u_int32_t tx_single_collisions; 410113017Smux u_int32_t tx_multiple_collisions; 411113017Smux u_int32_t tx_total_collisions; 412113017Smux u_int32_t rx_good; 413113017Smux u_int32_t rx_crc_errors; 414113017Smux u_int32_t rx_alignment_errors; 415113017Smux u_int32_t rx_rnr_errors; 416113017Smux u_int32_t rx_overrun_errors; 417113017Smux u_int32_t rx_cdt_errors; 418113017Smux u_int32_t rx_shortframes; 419113017Smux u_int32_t completion_status; 42012510Sdg}; 42112510Sdg#define FXP_STATS_DUMP_COMPLETE 0xa005 42212510Sdg#define FXP_STATS_DR_COMPLETE 0xa007 42312510Sdg 42412510Sdg/* 42512510Sdg * Serial EEPROM control register bits 42612510Sdg */ 42774178Sjlemon#define FXP_EEPROM_EESK 0x01 /* shift clock */ 42874178Sjlemon#define FXP_EEPROM_EECS 0x02 /* chip select */ 42974178Sjlemon#define FXP_EEPROM_EEDI 0x04 /* data in */ 43074178Sjlemon#define FXP_EEPROM_EEDO 0x08 /* data out */ 43112510Sdg 43212510Sdg/* 43312510Sdg * Serial EEPROM opcodes, including start bit 43412510Sdg */ 43512510Sdg#define FXP_EEPROM_OPC_ERASE 0x4 43612510Sdg#define FXP_EEPROM_OPC_WRITE 0x5 43712510Sdg#define FXP_EEPROM_OPC_READ 0x6 43823964Sdg 43923964Sdg/* 44023964Sdg * Management Data Interface opcodes 44123964Sdg */ 44223964Sdg#define FXP_MDI_WRITE 0x1 44323964Sdg#define FXP_MDI_READ 0x2 44423964Sdg 44523964Sdg/* 44623964Sdg * PHY device types 44723964Sdg */ 44876630Sjlemon#define FXP_PHY_DEVICE_MASK 0x3f00 44974178Sjlemon#define FXP_PHY_SERIAL_ONLY 0x8000 45023964Sdg#define FXP_PHY_NONE 0 45123964Sdg#define FXP_PHY_82553A 1 45223964Sdg#define FXP_PHY_82553C 2 45323964Sdg#define FXP_PHY_82503 3 45423964Sdg#define FXP_PHY_DP83840 4 45523964Sdg#define FXP_PHY_80C240 5 45623964Sdg#define FXP_PHY_80C24 6 45726623Sdg#define FXP_PHY_82555 7 45824079Sdg#define FXP_PHY_DP83840A 10 45934014Sdg#define FXP_PHY_82555B 11 46085460Sjlemon 46185460Sjlemon/* 46285460Sjlemon * Chip revision values. 46385460Sjlemon */ 46485460Sjlemon#define FXP_REV_82557 1 /* catchall 82557 chip type */ 46585460Sjlemon#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 46685460Sjlemon#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 46785460Sjlemon#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 46885460Sjlemon#define FXP_REV_82559S_A 9 /* 82559S A stepping */ 46985460Sjlemon#define FXP_REV_82550 12 47085460Sjlemon#define FXP_REV_82550_C 13 /* 82550 C stepping */ 471