if_fxpreg.h revision 112982
112510Sdg/* 274259Sjlemon * Copyright (c) 1995, David Greenman 374178Sjlemon * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 412510Sdg * All rights reserved. 512510Sdg * 612510Sdg * Redistribution and use in source and binary forms, with or without 712510Sdg * modification, are permitted provided that the following conditions 812510Sdg * are met: 912510Sdg * 1. Redistributions of source code must retain the above copyright 1012510Sdg * notice unmodified, this list of conditions, and the following 1112510Sdg * disclaimer. 1212510Sdg * 2. Redistributions in binary form must reproduce the above copyright 1312510Sdg * notice, this list of conditions and the following disclaimer in the 1412510Sdg * documentation and/or other materials provided with the distribution. 1512510Sdg * 1612510Sdg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1712510Sdg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1812510Sdg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1912510Sdg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2012510Sdg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2112510Sdg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2212510Sdg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2312510Sdg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2412510Sdg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2512510Sdg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2612510Sdg * SUCH DAMAGE. 2712510Sdg * 2850477Speter * $FreeBSD: head/sys/dev/fxp/if_fxpreg.h 112982 2003-04-02 16:47:16Z mux $ 2912510Sdg */ 3012510Sdg 3112510Sdg#define FXP_VENDORID_INTEL 0x8086 3212510Sdg 3312510Sdg#define FXP_PCI_MMBA 0x10 3412510Sdg#define FXP_PCI_IOBA 0x14 3512510Sdg 3629138Sdg/* 3729138Sdg * Control/status registers. 3829138Sdg */ 3929138Sdg#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 4029138Sdg#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 4129138Sdg#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 4229138Sdg#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 4329138Sdg#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 4429138Sdg#define FXP_CSR_PORT 8 /* port (4 bytes) */ 4529138Sdg#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 4629138Sdg#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 4729138Sdg#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 4876526Sjlemon#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 4982425Sjlemon#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 5012510Sdg 5129138Sdg/* 5229138Sdg * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 5329138Sdg * 5429138Sdg * volatile u_int8_t :2, 5529138Sdg * scb_rus:4, 5629138Sdg * scb_cus:2; 5729138Sdg */ 5829138Sdg 5922255Sdg#define FXP_PORT_SOFTWARE_RESET 0 6022255Sdg#define FXP_PORT_SELFTEST 1 6122255Sdg#define FXP_PORT_SELECTIVE_RESET 2 6222255Sdg#define FXP_PORT_DUMP 3 6322255Sdg 6412510Sdg#define FXP_SCB_RUS_IDLE 0 6512510Sdg#define FXP_SCB_RUS_SUSPENDED 1 6612510Sdg#define FXP_SCB_RUS_NORESOURCES 2 6712510Sdg#define FXP_SCB_RUS_READY 4 6812510Sdg#define FXP_SCB_RUS_SUSP_NORBDS 9 6912510Sdg#define FXP_SCB_RUS_NORES_NORBDS 10 7012510Sdg#define FXP_SCB_RUS_READY_NORBDS 12 7112510Sdg 7212510Sdg#define FXP_SCB_CUS_IDLE 0 7312510Sdg#define FXP_SCB_CUS_SUSPENDED 1 7412510Sdg#define FXP_SCB_CUS_ACTIVE 2 7512510Sdg 7676526Sjlemon#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 7776526Sjlemon#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 7876526Sjlemon#define FXP_SCB_INTMASK_FCP 0x04 7976526Sjlemon#define FXP_SCB_INTMASK_ER 0x08 8076526Sjlemon#define FXP_SCB_INTMASK_RNR 0x10 8176526Sjlemon#define FXP_SCB_INTMASK_CNA 0x20 8276526Sjlemon#define FXP_SCB_INTMASK_FR 0x40 8376526Sjlemon#define FXP_SCB_INTMASK_CXTNO 0x80 8476526Sjlemon 8576526Sjlemon#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 8676526Sjlemon#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 8712510Sdg#define FXP_SCB_STATACK_SWI 0x04 8812510Sdg#define FXP_SCB_STATACK_MDI 0x08 8912510Sdg#define FXP_SCB_STATACK_RNR 0x10 9012510Sdg#define FXP_SCB_STATACK_CNA 0x20 9112510Sdg#define FXP_SCB_STATACK_FR 0x40 9212510Sdg#define FXP_SCB_STATACK_CXTNO 0x80 9312510Sdg 9412510Sdg#define FXP_SCB_COMMAND_CU_NOP 0x00 9512510Sdg#define FXP_SCB_COMMAND_CU_START 0x10 9612510Sdg#define FXP_SCB_COMMAND_CU_RESUME 0x20 9712510Sdg#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 9812510Sdg#define FXP_SCB_COMMAND_CU_DUMP 0x50 9912510Sdg#define FXP_SCB_COMMAND_CU_BASE 0x60 10012510Sdg#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 10112510Sdg 10212510Sdg#define FXP_SCB_COMMAND_RU_NOP 0 10312510Sdg#define FXP_SCB_COMMAND_RU_START 1 10412510Sdg#define FXP_SCB_COMMAND_RU_RESUME 2 10512510Sdg#define FXP_SCB_COMMAND_RU_ABORT 4 10612510Sdg#define FXP_SCB_COMMAND_RU_LOADHDS 5 10712510Sdg#define FXP_SCB_COMMAND_RU_BASE 6 10812510Sdg#define FXP_SCB_COMMAND_RU_RBDRESUME 7 10912510Sdg 11012510Sdg/* 11112510Sdg * Command block definitions 11212510Sdg */ 11312510Sdgstruct fxp_cb_nop { 11412510Sdg volatile u_int16_t cb_status; 11512510Sdg volatile u_int16_t cb_command; 11612510Sdg volatile u_int32_t link_addr; 11712510Sdg}; 11812510Sdgstruct fxp_cb_ias { 11912510Sdg volatile u_int16_t cb_status; 12012510Sdg volatile u_int16_t cb_command; 12112510Sdg volatile u_int32_t link_addr; 12212510Sdg volatile u_int8_t macaddr[6]; 12312510Sdg}; 12412510Sdg/* I hate bit-fields :-( */ 12512510Sdgstruct fxp_cb_config { 12612510Sdg volatile u_int16_t cb_status; 12712510Sdg volatile u_int16_t cb_command; 12812510Sdg volatile u_int32_t link_addr; 12936767Sbde volatile u_int byte_count:6, 13012510Sdg :2; 13136767Sbde volatile u_int rx_fifo_limit:4, 13212510Sdg tx_fifo_limit:3, 13312510Sdg :1; 13412510Sdg volatile u_int8_t adaptive_ifs; 13574178Sjlemon volatile u_int mwi_enable:1, /* 8,9 */ 13674178Sjlemon type_enable:1, /* 8,9 */ 13774178Sjlemon read_align_en:1, /* 8,9 */ 13874178Sjlemon end_wr_on_cl:1, /* 8,9 */ 13974178Sjlemon :4; 14036767Sbde volatile u_int rx_dma_bytecount:7, 14112510Sdg :1; 14236767Sbde volatile u_int tx_dma_bytecount:7, 14374178Sjlemon dma_mbce:1; 14474178Sjlemon volatile u_int late_scb:1, /* 7 */ 14574178Sjlemon direct_dma_dis:1, /* 8,9 */ 14674178Sjlemon tno_int_or_tco_en:1, /* 7,9 */ 14712510Sdg ci_int:1, 14874178Sjlemon ext_txcb_dis:1, /* 8,9 */ 14974178Sjlemon ext_stats_dis:1, /* 8,9 */ 15074178Sjlemon keep_overrun_rx:1, 15112510Sdg save_bf:1; 15236767Sbde volatile u_int disc_short_rx:1, 15312510Sdg underrun_retry:2, 154111578Swpaul :2, 155111578Swpaul ext_rfa:1, /* 550 */ 15674178Sjlemon two_frames:1, /* 8,9 */ 15774178Sjlemon dyn_tbd:1; /* 8,9 */ 15874178Sjlemon volatile u_int mediatype:1, /* 7 */ 15974178Sjlemon :6, 16074178Sjlemon csma_dis:1; /* 8,9 */ 16174178Sjlemon volatile u_int tcp_udp_cksum:1, /* 9 */ 16274178Sjlemon :3, 16374178Sjlemon vlan_tco:1, /* 8,9 */ 16474178Sjlemon link_wake_en:1, /* 8,9 */ 16574178Sjlemon arp_wake_en:1, /* 8 */ 16674178Sjlemon mc_wake_en:1; /* 8 */ 16736767Sbde volatile u_int :3, 16812510Sdg nsai:1, 16912510Sdg preamble_length:2, 17012510Sdg loopback:2; 17174178Sjlemon volatile u_int linear_priority:3, /* 7 */ 17212510Sdg :5; 17374178Sjlemon volatile u_int linear_pri_mode:1, /* 7 */ 17412510Sdg :3, 17512510Sdg interfrm_spacing:4; 17636767Sbde volatile u_int :8; 17736767Sbde volatile u_int :8; 17836767Sbde volatile u_int promiscuous:1, 17912510Sdg bcast_disable:1, 18074178Sjlemon wait_after_win:1, /* 8,9 */ 18174178Sjlemon :1, 18274178Sjlemon ignore_ul:1, /* 8,9 */ 18374178Sjlemon crc16_en:1, /* 9 */ 18474178Sjlemon :1, 18512510Sdg crscdt:1; 18674178Sjlemon volatile u_int fc_delay_lsb:8; /* 8,9 */ 18774178Sjlemon volatile u_int fc_delay_msb:8; /* 8,9 */ 18836767Sbde volatile u_int stripping:1, 18912510Sdg padding:1, 19012510Sdg rcv_crc_xfer:1, 19174178Sjlemon long_rx_en:1, /* 8,9 */ 19274178Sjlemon pri_fc_thresh:3, /* 8,9 */ 19374178Sjlemon :1; 19474178Sjlemon volatile u_int ia_wake_en:1, /* 8 */ 19574178Sjlemon magic_pkt_dis:1, /* 8,9,!9ER */ 19674178Sjlemon tx_fc_dis:1, /* 8,9 */ 19774178Sjlemon rx_fc_restop:1, /* 8,9 */ 19874178Sjlemon rx_fc_restart:1, /* 8,9 */ 19974178Sjlemon fc_filter:1, /* 8,9 */ 20012510Sdg force_fdx:1, 20112510Sdg fdx_pin_en:1; 20274178Sjlemon volatile u_int :5, 20374178Sjlemon pri_fc_loc:1, /* 8,9 */ 20412510Sdg multi_ia:1, 20512510Sdg :1; 20636767Sbde volatile u_int :3, 20712510Sdg mc_all:1, 20812510Sdg :4; 209111578Swpaul volatile u_int8_t gamla_rx:1; /* 550 */ 210111578Swpaul volatile u_int8_t pad[9]; /* 550 */ 21112510Sdg}; 21229974Sdg 21329974Sdg#define MAXMCADDR 80 21429974Sdgstruct fxp_cb_mcs { 21529974Sdg volatile u_int16_t cb_status; 21629974Sdg volatile u_int16_t cb_command; 21729974Sdg volatile u_int32_t link_addr; 21829974Sdg volatile u_int16_t mc_cnt; 21929974Sdg volatile u_int8_t mc_addr[MAXMCADDR][6]; 22029974Sdg}; 22129974Sdg 22285460Sjlemon#define MAXUCODESIZE 192 22385460Sjlemonstruct fxp_cb_ucode { 22485460Sjlemon u_int16_t cb_status; 22585460Sjlemon u_int16_t cb_command; 22685460Sjlemon u_int32_t link_addr; 22785460Sjlemon u_int32_t ucode[MAXUCODESIZE]; 22885460Sjlemon}; 22985460Sjlemon 23029974Sdg/* 231112982Smux * Number of DMA segments in a TxCB. 23229974Sdg */ 233112982Smux#define FXP_NTXSEG 32 23429974Sdg 23512510Sdgstruct fxp_tbd { 23612510Sdg volatile u_int32_t tb_addr; 23712510Sdg volatile u_int32_t tb_size; 23812510Sdg}; 239111578Swpaul 240111578Swpaulstruct fxp_ipcb { 241111578Swpaul /* 242111578Swpaul * The following fields are valid only when 243111578Swpaul * using the IPCB command block for TX checksum offload 244111578Swpaul * (and TCP large send, VLANs, and (I think) IPsec). To use 245111578Swpaul * them, you must enable extended TxCBs (available only 246111578Swpaul * on the 82559 and later) and use the IPCBXMIT command. 247111578Swpaul * Note that Intel defines the IPCB to be 32 bytes long, 248111578Swpaul * the last 8 bytes of which comprise the first entry 249111578Swpaul * in the TBD array (see note below). This means we only 250111578Swpaul * have to define 8 extra bytes here. 251111578Swpaul */ 252111578Swpaul volatile u_int16_t ipcb_schedule_low; 253111578Swpaul volatile u_int8_t ipcb_ip_schedule; 254111578Swpaul volatile u_int8_t ipcb_ip_activation_high; 255111578Swpaul volatile u_int16_t ipcb_vlan_id; 256111578Swpaul volatile u_int8_t ipcb_ip_header_offset; 257111578Swpaul volatile u_int8_t ipcb_tcp_header_offset; 258111578Swpaul}; 259111578Swpaul 26012510Sdgstruct fxp_cb_tx { 26112510Sdg volatile u_int16_t cb_status; 26212510Sdg volatile u_int16_t cb_command; 26312510Sdg volatile u_int32_t link_addr; 26412510Sdg volatile u_int32_t tbd_array_addr; 26512510Sdg volatile u_int16_t byte_count; 26612510Sdg volatile u_int8_t tx_threshold; 26712510Sdg volatile u_int8_t tbd_number; 268111578Swpaul 26912510Sdg /* 27074259Sjlemon * The following structure isn't actually part of the TxCB, 27174259Sjlemon * unless the extended TxCB feature is being used. In this 27274259Sjlemon * case, the first two elements of the structure below are 27374259Sjlemon * fetched along with the TxCB. 27412510Sdg */ 275111578Swpaul union { 276111578Swpaul volatile struct fxp_ipcb; 277111578Swpaul volatile struct fxp_tbd tbd[FXP_NTXSEG]; 278111578Swpaul } tx_cb_u; 27912510Sdg}; 28012510Sdg 281111578Swpaul#define tbd tx_cb_u.tbd 282111578Swpaul#define ipcb_schedule_low tx_cb_u.ipcb_schedule_low 283111578Swpaul#define ipcb_ip_schedule tx_cb_u.ipcb_ip_schedule 284111578Swpaul#define ipcb_ip_activation_high tx_cb_u.ipcb_ip_activation_high 285111578Swpaul#define ipcb_vlan_id tx_cb_u.ipcb_vlan_id 286111578Swpaul#define ipcb_ip_header_offset tx_cb_u.ipcb_ip_header_offset 287111578Swpaul#define ipcb_tcp_header_offset tx_cb_u.ipcb_tcp_header_offset 288111578Swpaul 28912510Sdg/* 290111578Swpaul * IPCB field definitions 291111578Swpaul */ 292111578Swpaul#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10 293111578Swpaul#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20 294111578Swpaul#define FXP_IPCB_TCP_PACKET 0x40 295111578Swpaul#define FXP_IPCB_LARGESEND_ENABLE 0x80 296111578Swpaul#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01 297111578Swpaul#define FXP_IPCB_INSERTVLAN_ENABLE 0x02 298111578Swpaul 299111578Swpaul/* 30012510Sdg * Control Block (CB) definitions 30112510Sdg */ 30212510Sdg 30312510Sdg/* status */ 30412510Sdg#define FXP_CB_STATUS_OK 0x2000 30512510Sdg#define FXP_CB_STATUS_C 0x8000 30612510Sdg/* commands */ 30712510Sdg#define FXP_CB_COMMAND_NOP 0x0 30812510Sdg#define FXP_CB_COMMAND_IAS 0x1 30912510Sdg#define FXP_CB_COMMAND_CONFIG 0x2 31029974Sdg#define FXP_CB_COMMAND_MCAS 0x3 31112510Sdg#define FXP_CB_COMMAND_XMIT 0x4 31285460Sjlemon#define FXP_CB_COMMAND_UCODE 0x5 31312510Sdg#define FXP_CB_COMMAND_DUMP 0x6 31412510Sdg#define FXP_CB_COMMAND_DIAG 0x7 315111578Swpaul#define FXP_CB_COMMAND_LOADFILT 0x8 316111578Swpaul#define FXP_CB_COMMAND_IPCBXMIT 0x9 317111578Swpaul 31812510Sdg/* command flags */ 31912510Sdg#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 32012510Sdg#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 32112510Sdg#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 32212510Sdg#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 32312510Sdg 32412510Sdg/* 32512510Sdg * RFA definitions 32612510Sdg */ 32712510Sdg 32812510Sdgstruct fxp_rfa { 32912510Sdg volatile u_int16_t rfa_status; 33012510Sdg volatile u_int16_t rfa_control; 33151821Sgallatin volatile u_int8_t link_addr[4]; 33251821Sgallatin volatile u_int8_t rbd_addr[4]; 33312510Sdg volatile u_int16_t actual_size; 33412510Sdg volatile u_int16_t size; 335111578Swpaul 336111578Swpaul /* 337111578Swpaul * The following fields are only available when using 338111578Swpaul * extended receive mode on an 82550/82551 chipset. 339111578Swpaul */ 340111578Swpaul volatile u_int16_t rfax_vlan_id; 341111578Swpaul volatile u_int8_t rfax_rx_parser_sts; 342111578Swpaul volatile u_int8_t rfax_rsvd0; 343111578Swpaul volatile u_int16_t rfax_security_sts; 344111578Swpaul volatile u_int8_t rfax_csum_sts; 345111578Swpaul volatile u_int8_t rfax_zerocopy_sts; 346111578Swpaul volatile u_int8_t rfax_pad[8]; 34712510Sdg}; 348111578Swpaul#define FXP_RFAX_LEN 16 349111578Swpaul 35012510Sdg#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 35112510Sdg#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 352111578Swpaul#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */ 353111578Swpaul#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */ 35412510Sdg#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 35512510Sdg#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 35612510Sdg#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 35712510Sdg#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 35812510Sdg#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 35912510Sdg#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 36012510Sdg#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 36112510Sdg#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 36212510Sdg#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 36312510Sdg#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 36412510Sdg#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 36512510Sdg#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 36612510Sdg#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 36712510Sdg 368111578Swpaul/* Bits in the 'csum_sts' byte */ 369111578Swpaul#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10 370111578Swpaul#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20 371111578Swpaul#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01 372111578Swpaul#define FXP_RFDX_CS_IP_CSUM_VALID 0x02 373111578Swpaul 374111578Swpaul/* Bits in the 'packet parser' byte */ 375111578Swpaul#define FXP_RFDX_P_PARSE_BIT 0x08 376111578Swpaul#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03 377111578Swpaul#define FXP_RFDX_P_TCP_PACKET 0x00 378111578Swpaul#define FXP_RFDX_P_UDP_PACKET 0x01 379111578Swpaul#define FXP_RFDX_P_IP_PACKET 0x03 380111578Swpaul 38112510Sdg/* 38212510Sdg * Statistics dump area definitions 38312510Sdg */ 38412510Sdgstruct fxp_stats { 38512510Sdg volatile u_int32_t tx_good; 38612510Sdg volatile u_int32_t tx_maxcols; 38712510Sdg volatile u_int32_t tx_latecols; 38812510Sdg volatile u_int32_t tx_underruns; 38912510Sdg volatile u_int32_t tx_lostcrs; 39012510Sdg volatile u_int32_t tx_deffered; 39112510Sdg volatile u_int32_t tx_single_collisions; 39212510Sdg volatile u_int32_t tx_multiple_collisions; 39312510Sdg volatile u_int32_t tx_total_collisions; 39412510Sdg volatile u_int32_t rx_good; 39512510Sdg volatile u_int32_t rx_crc_errors; 39612510Sdg volatile u_int32_t rx_alignment_errors; 39712510Sdg volatile u_int32_t rx_rnr_errors; 39812510Sdg volatile u_int32_t rx_overrun_errors; 39912510Sdg volatile u_int32_t rx_cdt_errors; 40012510Sdg volatile u_int32_t rx_shortframes; 40112510Sdg volatile u_int32_t completion_status; 40212510Sdg}; 40312510Sdg#define FXP_STATS_DUMP_COMPLETE 0xa005 40412510Sdg#define FXP_STATS_DR_COMPLETE 0xa007 40512510Sdg 40612510Sdg/* 40712510Sdg * Serial EEPROM control register bits 40812510Sdg */ 40974178Sjlemon#define FXP_EEPROM_EESK 0x01 /* shift clock */ 41074178Sjlemon#define FXP_EEPROM_EECS 0x02 /* chip select */ 41174178Sjlemon#define FXP_EEPROM_EEDI 0x04 /* data in */ 41274178Sjlemon#define FXP_EEPROM_EEDO 0x08 /* data out */ 41312510Sdg 41412510Sdg/* 41512510Sdg * Serial EEPROM opcodes, including start bit 41612510Sdg */ 41712510Sdg#define FXP_EEPROM_OPC_ERASE 0x4 41812510Sdg#define FXP_EEPROM_OPC_WRITE 0x5 41912510Sdg#define FXP_EEPROM_OPC_READ 0x6 42023964Sdg 42123964Sdg/* 42223964Sdg * Management Data Interface opcodes 42323964Sdg */ 42423964Sdg#define FXP_MDI_WRITE 0x1 42523964Sdg#define FXP_MDI_READ 0x2 42623964Sdg 42723964Sdg/* 42823964Sdg * PHY device types 42923964Sdg */ 43076630Sjlemon#define FXP_PHY_DEVICE_MASK 0x3f00 43174178Sjlemon#define FXP_PHY_SERIAL_ONLY 0x8000 43223964Sdg#define FXP_PHY_NONE 0 43323964Sdg#define FXP_PHY_82553A 1 43423964Sdg#define FXP_PHY_82553C 2 43523964Sdg#define FXP_PHY_82503 3 43623964Sdg#define FXP_PHY_DP83840 4 43723964Sdg#define FXP_PHY_80C240 5 43823964Sdg#define FXP_PHY_80C24 6 43926623Sdg#define FXP_PHY_82555 7 44024079Sdg#define FXP_PHY_DP83840A 10 44134014Sdg#define FXP_PHY_82555B 11 44285460Sjlemon 44385460Sjlemon/* 44485460Sjlemon * Chip revision values. 44585460Sjlemon */ 44685460Sjlemon#define FXP_REV_82557 1 /* catchall 82557 chip type */ 44785460Sjlemon#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 44885460Sjlemon#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 44985460Sjlemon#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 45085460Sjlemon#define FXP_REV_82559S_A 9 /* 82559S A stepping */ 45185460Sjlemon#define FXP_REV_82550 12 45285460Sjlemon#define FXP_REV_82550_C 13 /* 82550 C stepping */ 453