fwohcireg.h revision 272214
138889Sjdp/*- 285815Sobrien * Copyright (c) 2003 Hidetoshi Shimokawa 338889Sjdp * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 438889Sjdp * All rights reserved. 585815Sobrien * 638889Sjdp * Redistribution and use in source and binary forms, with or without 785815Sobrien * modification, are permitted provided that the following conditions 885815Sobrien * are met: 985815Sobrien * 1. Redistributions of source code must retain the above copyright 1085815Sobrien * notice, this list of conditions and the following disclaimer. 1138889Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1285815Sobrien * notice, this list of conditions and the following disclaimer in the 1385815Sobrien * documentation and/or other materials provided with the distribution. 1485815Sobrien * 3. All advertising materials mentioning features or use of this software 1585815Sobrien * must display the acknowledgement as bellow: 1638889Sjdp * 1785815Sobrien * This product includes software developed by K. Kobayashi and H. Shimokawa 1885815Sobrien * 1985815Sobrien * 4. The name of the author may not be used to endorse or promote products 2038889Sjdp * derived from this software without specific prior written permission. 2138889Sjdp * 2238889Sjdp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2338889Sjdp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 2438889Sjdp * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 2538889Sjdp * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 2689857Sobrien * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 2738889Sjdp * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 2838889Sjdp * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2985815Sobrien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3038889Sjdp * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 3138889Sjdp * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3285815Sobrien * POSSIBILITY OF SUCH DAMAGE. 3385815Sobrien * 3485815Sobrien * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 272214 2014-09-27 16:50:21Z kan $ 3585815Sobrien * 3689857Sobrien */ 3789857Sobrien#define PCI_CBMEM PCIR_BAR(0) 3838889Sjdp 3938889Sjdp#define FW_VENDORID_NATSEMI 0x100B 4038889Sjdp#define FW_VENDORID_NEC 0x1033 4185815Sobrien#define FW_VENDORID_SIS 0x1039 4238889Sjdp#define FW_VENDORID_TI 0x104c 4338889Sjdp#define FW_VENDORID_SONY 0x104d 4438889Sjdp#define FW_VENDORID_VIA 0x1106 4538889Sjdp#define FW_VENDORID_RICOH 0x1180 4638889Sjdp#define FW_VENDORID_APPLE 0x106b 4785815Sobrien#define FW_VENDORID_LUCENT 0x11c1 4885815Sobrien#define FW_VENDORID_INTEL 0x8086 4985815Sobrien#define FW_VENDORID_ADAPTEC 0x9004 5085815Sobrien#define FW_VENDORID_SUN 0x108e 5185815Sobrien 5285815Sobrien#define FW_DEVICE_CS4210 (0x000f << 16) 5385815Sobrien#define FW_DEVICE_UPD861 (0x0063 << 16) 5485815Sobrien#define FW_DEVICE_UPD871 (0x00ce << 16) 5585815Sobrien#define FW_DEVICE_UPD72870 (0x00cd << 16) 5689857Sobrien#define FW_DEVICE_UPD72873 (0x00e7 << 16) 5785815Sobrien#define FW_DEVICE_UPD72874 (0x00f2 << 16) 5885815Sobrien#define FW_DEVICE_TITSB22 (0x8009 << 16) 5985815Sobrien#define FW_DEVICE_TITSB23 (0x8019 << 16) 6038889Sjdp#define FW_DEVICE_TITSB26 (0x8020 << 16) 6138889Sjdp#define FW_DEVICE_TITSB43 (0x8021 << 16) 6285815Sobrien#define FW_DEVICE_TITSB43A (0x8023 << 16) 6385815Sobrien#define FW_DEVICE_TITSB43AB23 (0x8024 << 16) 6485815Sobrien#define FW_DEVICE_TITSB82AA2 (0x8025 << 16) 6585815Sobrien#define FW_DEVICE_TITSB43AB21 (0x8026 << 16) 6685815Sobrien#define FW_DEVICE_TIPCI4410A (0x8017 << 16) 6785815Sobrien#define FW_DEVICE_TIPCI4450 (0x8011 << 16) 6885815Sobrien#define FW_DEVICE_TIPCI4451 (0x8027 << 16) 6985815Sobrien#define FW_DEVICE_CXD1947 (0x8009 << 16) 7085815Sobrien#define FW_DEVICE_CXD3222 (0x8039 << 16) 7189857Sobrien#define FW_DEVICE_VT6306 (0x3044 << 16) 7285815Sobrien#define FW_DEVICE_R5C551 (0x0551 << 16) 7385815Sobrien#define FW_DEVICE_R5C552 (0x0552 << 16) 7485815Sobrien#define FW_DEVICE_PANGEA (0x0030 << 16) 7538889Sjdp#define FW_DEVICE_UNINORTH (0x0031 << 16) 7638889Sjdp#define FW_DEVICE_AIC5800 (0x5800 << 16) 7785815Sobrien#define FW_DEVICE_FW322 (0x5811 << 16) 7885815Sobrien#define FW_DEVICE_7007 (0x7007 << 16) 7985815Sobrien#define FW_DEVICE_82372FB (0x7605 << 16) 8085815Sobrien#define FW_DEVICE_PCIO2FW (0x1102 << 16) 8185815Sobrien 8285815Sobrien#define PCI_INTERFACE_OHCI 0x10 8385815Sobrien 8485815Sobrien#define FW_OHCI_BASE_REG 0x10 8585815Sobrien 8689857Sobrien#define OHCI_DMA_ITCH 0x20 8785815Sobrien#define OHCI_DMA_IRCH 0x20 8885815Sobrien 8985815Sobrien#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 9038889Sjdp 9138889Sjdp 9285815Sobrientypedef uint32_t fwohcireg_t; 9385815Sobrien 9485815Sobrien/* for PCI */ 9585815Sobrien#if BYTE_ORDER == BIG_ENDIAN 9685815Sobrien#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 9785815Sobrien#define FWOHCI_DMA_READ(x) le32toh(x) 9885815Sobrien#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 9989857Sobrien#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 10085815Sobrien#else 10189857Sobrien#define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 10285815Sobrien#define FWOHCI_DMA_READ(x) (x) 10385815Sobrien#define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 10489857Sobrien#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 10538889Sjdp#endif 10638889Sjdp 10738889Sjdpstruct fwohcidb { 10838889Sjdp union { 10938889Sjdp struct { 11038889Sjdp uint32_t cmd; 11160484Sobrien uint32_t addr; 11238889Sjdp uint32_t depend; 11338889Sjdp uint32_t res; 11438889Sjdp } desc; 11538889Sjdp uint32_t immed[4]; 11638889Sjdp } db; 11738889Sjdp#define OHCI_STATUS_SHIFT 16 11838889Sjdp#define OHCI_COUNT_MASK 0xffff 11938889Sjdp#define OHCI_OUTPUT_MORE (0 << 28) 12038889Sjdp#define OHCI_OUTPUT_LAST (1 << 28) 12138889Sjdp#define OHCI_INPUT_MORE (2 << 28) 12238889Sjdp#define OHCI_INPUT_LAST (3 << 28) 12338889Sjdp#define OHCI_STORE_QUAD (4 << 28) 12438889Sjdp#define OHCI_LOAD_QUAD (5 << 28) 12538889Sjdp#define OHCI_NOP (6 << 28) 12660484Sobrien#define OHCI_STOP (7 << 28) 12738889Sjdp#define OHCI_STORE (8 << 28) 12838889Sjdp#define OHCI_CMD_MASK (0xf << 28) 12938889Sjdp 13038889Sjdp#define OHCI_UPDATE (1 << 27) 13189857Sobrien 13289857Sobrien#define OHCI_KEY_ST0 (0 << 24) 13389857Sobrien#define OHCI_KEY_ST1 (1 << 24) 13489857Sobrien#define OHCI_KEY_ST2 (2 << 24) 13538889Sjdp#define OHCI_KEY_ST3 (3 << 24) 13638889Sjdp#define OHCI_KEY_REGS (5 << 24) 13738889Sjdp#define OHCI_KEY_SYS (6 << 24) 13838889Sjdp#define OHCI_KEY_DEVICE (7 << 24) 13938889Sjdp#define OHCI_KEY_MASK (7 << 24) 14038889Sjdp 14138889Sjdp#define OHCI_INTERRUPT_NEVER (0 << 20) 14260484Sobrien#define OHCI_INTERRUPT_TRUE (1 << 20) 14338889Sjdp#define OHCI_INTERRUPT_FALSE (2 << 20) 14438889Sjdp#define OHCI_INTERRUPT_ALWAYS (3 << 20) 14538889Sjdp 14638889Sjdp#define OHCI_BRANCH_NEVER (0 << 18) 14738889Sjdp#define OHCI_BRANCH_TRUE (1 << 18) 14838889Sjdp#define OHCI_BRANCH_FALSE (2 << 18) 14938889Sjdp#define OHCI_BRANCH_ALWAYS (3 << 18) 15038889Sjdp#define OHCI_BRANCH_MASK (3 << 18) 15138889Sjdp 15238889Sjdp#define OHCI_WAIT_NEVER (0 << 16) 15338889Sjdp#define OHCI_WAIT_TRUE (1 << 16) 15438889Sjdp#define OHCI_WAIT_FALSE (2 << 16) 15538889Sjdp#define OHCI_WAIT_ALWAYS (3 << 16) 15638889Sjdp}; 15738889Sjdp 15838889Sjdp#define OHCI_SPD_S100 0x4 15989857Sobrien#define OHCI_SPD_S200 0x1 16038889Sjdp#define OHCI_SPD_S400 0x2 16185815Sobrien 16238889Sjdp 16385815Sobrien#define FWOHCIEV_NOSTAT 0 16485815Sobrien#define FWOHCIEV_LONGP 2 16585815Sobrien#define FWOHCIEV_MISSACK 3 16685815Sobrien#define FWOHCIEV_UNDRRUN 4 16785815Sobrien#define FWOHCIEV_OVRRUN 5 16885815Sobrien#define FWOHCIEV_DESCERR 6 16985815Sobrien#define FWOHCIEV_DTRDERR 7 17085815Sobrien#define FWOHCIEV_DTWRERR 8 17185815Sobrien#define FWOHCIEV_BUSRST 9 17285815Sobrien#define FWOHCIEV_TIMEOUT 0xa 17385815Sobrien#define FWOHCIEV_TCODERR 0xb 17485815Sobrien#define FWOHCIEV_UNKNOWN 0xe 17585815Sobrien#define FWOHCIEV_FLUSHED 0xf 17685815Sobrien#define FWOHCIEV_ACKCOMPL 0x11 17785815Sobrien#define FWOHCIEV_ACKPEND 0x12 17885815Sobrien#define FWOHCIEV_ACKBSX 0x14 17985815Sobrien#define FWOHCIEV_ACKBSA 0x15 18085815Sobrien#define FWOHCIEV_ACKBSB 0x16 18138889Sjdp#define FWOHCIEV_ACKTARD 0x1b 18285815Sobrien#define FWOHCIEV_ACKDERR 0x1d 18338889Sjdp#define FWOHCIEV_ACKTERR 0x1e 18438889Sjdp 18538889Sjdp#define FWOHCIEV_MASK 0x1f 18638889Sjdp 18738889Sjdpstruct ohci_dma { 18838889Sjdp fwohcireg_t cntl; 18938889Sjdp 19038889Sjdp#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 19160484Sobrien 19238889Sjdp#define OHCI_CNTL_BUFFIL (0x1 << 31) 19338889Sjdp#define OHCI_CNTL_ISOHDR (0x1 << 30) 19438889Sjdp#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 19585815Sobrien#define OHCI_CNTL_MULTICH (0x1 << 28) 19638889Sjdp 19785815Sobrien#define OHCI_CNTL_DMA_RUN (0x1 << 15) 19885815Sobrien#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 19938889Sjdp#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 20038889Sjdp#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 20185815Sobrien#define OHCI_CNTL_DMA_BT (0x1 << 8) 20285815Sobrien#define OHCI_CNTL_DMA_BAD (0x1 << 7) 20385815Sobrien#define OHCI_CNTL_DMA_STAT (0xff) 20485815Sobrien 20585815Sobrien fwohcireg_t cntl_clr; 20685815Sobrien fwohcireg_t dummy0; 20785815Sobrien fwohcireg_t cmd; 20885815Sobrien fwohcireg_t match; 20985815Sobrien fwohcireg_t dummy1; 21038889Sjdp fwohcireg_t dummy2; 21138889Sjdp fwohcireg_t dummy3; 21238889Sjdp}; 21338889Sjdp 21438889Sjdpstruct ohci_itdma { 21589857Sobrien fwohcireg_t cntl; 21689857Sobrien fwohcireg_t cntl_clr; 21789857Sobrien fwohcireg_t dummy0; 21889857Sobrien fwohcireg_t cmd; 21989857Sobrien}; 22089857Sobrien 22189857Sobrienstruct ohci_registers { 22289857Sobrien fwohcireg_t ver; /* Version No. 0x0 */ 22389857Sobrien fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 22489857Sobrien fwohcireg_t retry; /* AT retries 0x8 */ 22589857Sobrien#define FWOHCI_RETRY 0x8 22689857Sobrien fwohcireg_t csr_data; /* CSR data 0xc */ 22789857Sobrien fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 22889857Sobrien fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 22989857Sobrien fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 23089857Sobrien fwohcireg_t bus_id; /* BUS_ID 0x1c */ 23189857Sobrien fwohcireg_t bus_opt; /* BUS option 0x20 */ 23289857Sobrien#define FWOHCIGUID_H 0x24 23389857Sobrien#define FWOHCIGUID_L 0x28 23489857Sobrien fwohcireg_t guid_hi; /* GUID hi 0x24 */ 23589857Sobrien fwohcireg_t guid_lo; /* GUID lo 0x28 */ 23689857Sobrien fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 23789857Sobrien fwohcireg_t config_rom; /* config ROM map 0x34 */ 238104834Sobrien fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 23985815Sobrien fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 24085815Sobrien fwohcireg_t vendor; /* vendor ID 0x40 */ 24185815Sobrien fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 24285815Sobrien fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 24385815Sobrien fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 24485815Sobrien#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */ 24585815Sobrien#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 24638889Sjdp#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 24785815Sobrien#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 24885815Sobrien#define OHCI_HCC_LPS (1 << 19) /* LPS */ 24985815Sobrien#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 25085815Sobrien#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 25138889Sjdp#define OHCI_HCC_RESET (1 << 16) /* softReset */ 25238889Sjdp fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 253 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 254 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 255 fwohcireg_t sid_cnt; /* self id count 0x68 */ 256 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 257 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 258 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 259 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 260 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 261#define FWOHCI_INTSTAT 0x80 262#define FWOHCI_INTSTATCLR 0x84 263#define FWOHCI_INTMASK 0x88 264#define FWOHCI_INTMASKCLR 0x8c 265 fwohcireg_t int_stat; /* 0x80 */ 266 fwohcireg_t int_clear; /* 0x84 */ 267 fwohcireg_t int_mask; /* 0x88 */ 268 fwohcireg_t int_mask_clear; /* 0x8c */ 269 fwohcireg_t it_int_stat; /* 0x90 */ 270 fwohcireg_t it_int_clear; /* 0x94 */ 271 fwohcireg_t it_int_mask; /* 0x98 */ 272 fwohcireg_t it_mask_clear; /* 0x9c */ 273 fwohcireg_t ir_int_stat; /* 0xa0 */ 274 fwohcireg_t ir_int_clear; /* 0xa4 */ 275 fwohcireg_t ir_int_mask; /* 0xa8 */ 276 fwohcireg_t ir_mask_clear; /* 0xac */ 277 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 278 fwohcireg_t fairness; /* fairness control 0xdc */ 279 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 280 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 281#define FWOHCI_NODEID 0xe8 282 fwohcireg_t node; /* Node ID 0xe8 */ 283#define OHCI_NODE_VALID (1U << 31) 284#define OHCI_NODE_ROOT (1 << 30) 285 286#define OHCI_ASYSRCBUS 1 287 288 fwohcireg_t phy_access; /* PHY cntl 0xec */ 289#define PHYDEV_RDDONE (1<<31) 290#define PHYDEV_RDCMD (1<<15) 291#define PHYDEV_WRCMD (1<<14) 292#define PHYDEV_REGADDR 8 293#define PHYDEV_WRDATA 0 294#define PHYDEV_RDADDR 24 295#define PHYDEV_RDDATA 16 296 297 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 298 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 299 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 300 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 301 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 302 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 303 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 304 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 305 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 306 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 307 308 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 309 310 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 311 312 /* 0x180, 0x184, 0x188, 0x18c */ 313 /* 0x190, 0x194, 0x198, 0x19c */ 314 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 315 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 316 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 317 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 318 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 319 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 320 struct ohci_dma dma_ch[0x4]; 321 322 /* 0x200, 0x204, 0x208, 0x20c */ 323 /* 0x210, 0x204, 0x208, 0x20c */ 324 struct ohci_itdma dma_itch[0x20]; 325 326 /* 0x400, 0x404, 0x408, 0x40c */ 327 /* 0x410, 0x404, 0x408, 0x40c */ 328 struct ohci_dma dma_irch[0x20]; 329}; 330 331struct fwohcidb_tr { 332 STAILQ_ENTRY(fwohcidb_tr) link; 333 struct fw_xfer *xfer; 334 struct fwohcidb *db; 335 bus_dmamap_t dma_map; 336 caddr_t buf; 337 bus_addr_t bus_addr; 338 int dbcnt; 339}; 340 341/* 342 * OHCI info structure. 343 */ 344struct fwohci_txpkthdr { 345 union { 346 uint32_t ld[4]; 347 struct { 348#if BYTE_ORDER == BIG_ENDIAN 349 uint32_t spd:16, /* XXX include reserved field */ 350 :8, 351 tcode:4, 352 :4; 353#else 354 uint32_t :4, 355 tcode:4, 356 :8, 357 spd:16; /* XXX include reserved fields */ 358#endif 359 }common; 360 struct { 361#if BYTE_ORDER == BIG_ENDIAN 362 uint32_t :8, 363 srcbus:1, 364 :4, 365 spd:3, 366 tlrt:8, 367 tcode:4, 368 :4; 369#else 370 uint32_t :4, 371 tcode:4, 372 tlrt:8, 373 spd:3, 374 :4, 375 srcbus:1, 376 :8; 377#endif 378 BIT16x2(dst, ); 379 } asycomm; 380 struct { 381#if BYTE_ORDER == BIG_ENDIAN 382 uint32_t :13, 383 spd:3, 384 chtag:8, 385 tcode:4, 386 sy:4; 387#else 388 uint32_t sy:4, 389 tcode:4, 390 chtag:8, 391 spd:3, 392 :13; 393#endif 394 BIT16x2(len, ); 395 } stream; 396 } mode; 397}; 398 399struct fwohci_trailer { 400#if BYTE_ORDER == BIG_ENDIAN 401 uint32_t stat:16, 402 time:16; 403#else 404 uint32_t time:16, 405 stat:16; 406#endif 407}; 408 409#define OHCI_CNTL_CYCSRC (0x1 << 22) 410#define OHCI_CNTL_CYCMTR (0x1 << 21) 411#define OHCI_CNTL_CYCTIMER (0x1 << 20) 412#define OHCI_CNTL_PHYPKT (0x1 << 10) 413#define OHCI_CNTL_SID (0x1 << 9) 414 415/* 416 * defined in OHCI 1.1 417 * chapter 6.1 418 */ 419#define OHCI_INT_DMA_ATRQ (0x1 << 0) 420#define OHCI_INT_DMA_ATRS (0x1 << 1) 421#define OHCI_INT_DMA_ARRQ (0x1 << 2) 422#define OHCI_INT_DMA_ARRS (0x1 << 3) 423#define OHCI_INT_DMA_PRRQ (0x1 << 4) 424#define OHCI_INT_DMA_PRRS (0x1 << 5) 425#define OHCI_INT_DMA_IT (0x1 << 6) 426#define OHCI_INT_DMA_IR (0x1 << 7) 427#define OHCI_INT_PW_ERR (0x1 << 8) 428#define OHCI_INT_LR_ERR (0x1 << 9) 429#define OHCI_INT_PHY_SID (0x1 << 16) 430#define OHCI_INT_PHY_BUS_R (0x1 << 17) 431#define OHCI_INT_REG_FAIL (0x1 << 18) 432#define OHCI_INT_PHY_INT (0x1 << 19) 433#define OHCI_INT_CYC_START (0x1 << 20) 434#define OHCI_INT_CYC_64SECOND (0x1 << 21) 435#define OHCI_INT_CYC_LOST (0x1 << 22) 436#define OHCI_INT_CYC_ERR (0x1 << 23) 437#define OHCI_INT_ERR (0x1 << 24) 438#define OHCI_INT_CYC_LONG (0x1 << 25) 439#define OHCI_INT_PHY_REG (0x1 << 26) 440#define OHCI_INT_EN (0x1 << 31) 441 442#define IP_CHANNELS 0x0234 443#define FWOHCI_MAXREC 2048 444 445#define OHCI_ISORA 0x02 446#define OHCI_ISORB 0x04 447 448#define FWOHCITCODE_PHY 0xe 449