fwohcireg.h revision 113584
1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 113584 2003-04-17 03:38:03Z simokawa $ 35 * 36 */ 37#define PCI_CBMEM 0x10 38 39#define FW_VENDORID_NEC 0x1033 40#define FW_VENDORID_TI 0x104c 41#define FW_VENDORID_SONY 0x104d 42#define FW_VENDORID_VIA 0x1106 43#define FW_VENDORID_RICOH 0x1180 44#define FW_VENDORID_APPLE 0x106b 45#define FW_VENDORID_LUCENT 0x11c1 46 47#define FW_DEVICE_UPD861 (0x0063 << 16) 48#define FW_DEVICE_UPD871 (0x00ce << 16) 49#define FW_DEVICE_TITSB22 (0x8009 << 16) 50#define FW_DEVICE_TITSB23 (0x8019 << 16) 51#define FW_DEVICE_TITSB26 (0x8020 << 16) 52#define FW_DEVICE_TITSB43 (0x8021 << 16) 53#define FW_DEVICE_TITSB43A (0x8023 << 16) 54#define FW_DEVICE_TIPCI4450 (0x8011 << 16) 55#define FW_DEVICE_TIPCI4410A (0x8017 << 16) 56#define FW_DEVICE_CX3022 (0x8039 << 16) 57#define FW_DEVICE_VT6306 (0x3044 << 16) 58#define FW_DEVICE_R5C552 (0x0552 << 16) 59#define FW_DEVICE_PANGEA (0x0030 << 16) 60#define FW_DEVICE_UNINORTH (0x0031 << 16) 61#define FW_DEVICE_FW322 (0x5811 << 16) 62 63#define PCI_INTERFACE_OHCI 0x10 64 65#define FW_OHCI_BASE_REG 0x10 66 67#define OHCI_DMA_ITCH 0x20 68#define OHCI_DMA_IRCH 0x20 69 70#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 71 72 73typedef volatile u_int32_t fwohcireg_t; 74 75/* for PCI */ 76#if BYTE_ORDER == BIG_ENDIAN 77#define FWOHCI_DMA_WRITE(x, y) ((x) = htole32(y)) 78#define FWOHCI_DMA_READ(x) le32toh(x) 79#define FWOHCI_DMA_SET(x, y) ((x) |= htole32(y)) 80#define FWOHCI_DMA_CLEAR(x, y) ((x) &= htole32(~(y))) 81#else 82#define FWOHCI_DMA_WRITE(x, y) ((x) = (y)) 83#define FWOHCI_DMA_READ(x) (x) 84#define FWOHCI_DMA_SET(x, y) ((x) |= (y)) 85#define FWOHCI_DMA_CLEAR(x, y) ((x) &= ~(y)) 86#endif 87 88struct fwohcidb { 89 union { 90 struct { 91 volatile u_int32_t cmd; 92 volatile u_int32_t addr; 93 volatile u_int32_t depend; 94 volatile u_int32_t res; 95 } desc; 96 volatile u_int32_t immed[4]; 97 } db; 98#define OHCI_STATUS_SHIFT 16 99#define OHCI_COUNT_MASK 0xffff 100#define OHCI_OUTPUT_MORE (0 << 28) 101#define OHCI_OUTPUT_LAST (1 << 28) 102#define OHCI_INPUT_MORE (2 << 28) 103#define OHCI_INPUT_LAST (3 << 28) 104#define OHCI_STORE_QUAD (4 << 28) 105#define OHCI_LOAD_QUAD (5 << 28) 106#define OHCI_NOP (6 << 28) 107#define OHCI_STOP (7 << 28) 108#define OHCI_STORE (8 << 28) 109#define OHCI_CMD_MASK (0xf << 28) 110 111#define OHCI_UPDATE (1 << 27) 112 113#define OHCI_KEY_ST0 (0 << 24) 114#define OHCI_KEY_ST1 (1 << 24) 115#define OHCI_KEY_ST2 (2 << 24) 116#define OHCI_KEY_ST3 (3 << 24) 117#define OHCI_KEY_REGS (5 << 24) 118#define OHCI_KEY_SYS (6 << 24) 119#define OHCI_KEY_DEVICE (7 << 24) 120#define OHCI_KEY_MASK (7 << 24) 121 122#define OHCI_INTERRUPT_NEVER (0 << 20) 123#define OHCI_INTERRUPT_TRUE (1 << 20) 124#define OHCI_INTERRUPT_FALSE (2 << 20) 125#define OHCI_INTERRUPT_ALWAYS (3 << 20) 126 127#define OHCI_BRANCH_NEVER (0 << 18) 128#define OHCI_BRANCH_TRUE (1 << 18) 129#define OHCI_BRANCH_FALSE (2 << 18) 130#define OHCI_BRANCH_ALWAYS (3 << 18) 131#define OHCI_BRANCH_MASK (3 << 18) 132 133#define OHCI_WAIT_NEVER (0 << 16) 134#define OHCI_WAIT_TRUE (1 << 16) 135#define OHCI_WAIT_FALSE (2 << 16) 136#define OHCI_WAIT_ALWAYS (3 << 16) 137}; 138 139#define OHCI_SPD_S100 0x4 140#define OHCI_SPD_S200 0x1 141#define OHCI_SPD_S400 0x2 142 143 144#define FWOHCIEV_NOSTAT 0 145#define FWOHCIEV_LONGP 2 146#define FWOHCIEV_MISSACK 3 147#define FWOHCIEV_UNDRRUN 4 148#define FWOHCIEV_OVRRUN 5 149#define FWOHCIEV_DESCERR 6 150#define FWOHCIEV_DTRDERR 7 151#define FWOHCIEV_DTWRERR 8 152#define FWOHCIEV_BUSRST 9 153#define FWOHCIEV_TIMEOUT 0xa 154#define FWOHCIEV_TCODERR 0xb 155#define FWOHCIEV_UNKNOWN 0xe 156#define FWOHCIEV_FLUSHED 0xf 157#define FWOHCIEV_ACKCOMPL 0x11 158#define FWOHCIEV_ACKPEND 0x12 159#define FWOHCIEV_ACKBSX 0x14 160#define FWOHCIEV_ACKBSA 0x15 161#define FWOHCIEV_ACKBSB 0x16 162#define FWOHCIEV_ACKTARD 0x1b 163#define FWOHCIEV_ACKDERR 0x1d 164#define FWOHCIEV_ACKTERR 0x1e 165 166#define FWOHCIEV_MASK 0x1f 167 168struct ohci_registers { 169 fwohcireg_t ver; /* Version No. 0x0 */ 170 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 171 fwohcireg_t retry; /* AT retries 0x8 */ 172#define FWOHCI_RETRY 0x8 173 fwohcireg_t csr_data; /* CSR data 0xc */ 174 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 175 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 176 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 177 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 178 fwohcireg_t bus_opt; /* BUS option 0x20 */ 179#define FWOHCIGUID_H 0x24 180#define FWOHCIGUID_L 0x28 181 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 182 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 183 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 184 fwohcireg_t config_rom; /* config ROM map 0x34 */ 185 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 186 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 187 fwohcireg_t vender; /* vender ID 0x40 */ 188 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 189 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 190 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 191#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 192#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 193#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 194#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 195#define OHCI_HCC_LPS (1 << 19) /* LPS */ 196#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 197#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 198#define OHCI_HCC_RESET (1 << 16) /* softReset */ 199 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 200 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 201 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 202 fwohcireg_t sid_cnt; /* self id count 0x68 */ 203 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 204 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 205 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 206 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 207 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 208#define FWOHCI_INTSTAT 0x80 209#define FWOHCI_INTSTATCLR 0x84 210#define FWOHCI_INTMASK 0x88 211#define FWOHCI_INTMASKCLR 0x8c 212 fwohcireg_t int_stat; /* 0x80 */ 213 fwohcireg_t int_clear; /* 0x84 */ 214 fwohcireg_t int_mask; /* 0x88 */ 215 fwohcireg_t int_mask_clear; /* 0x8c */ 216 fwohcireg_t it_int_stat; /* 0x90 */ 217 fwohcireg_t it_int_clear; /* 0x94 */ 218 fwohcireg_t it_int_mask; /* 0x98 */ 219 fwohcireg_t it_mask_clear; /* 0x9c */ 220 fwohcireg_t ir_int_stat; /* 0xa0 */ 221 fwohcireg_t ir_int_clear; /* 0xa4 */ 222 fwohcireg_t ir_int_mask; /* 0xa8 */ 223 fwohcireg_t ir_mask_clear; /* 0xac */ 224 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 225 fwohcireg_t fairness; /* fairness control 0xdc */ 226 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 227 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 228#define FWOHCI_NODEID 0xe8 229 fwohcireg_t node; /* Node ID 0xe8 */ 230#define OHCI_NODE_VALID (1 << 31) 231#define OHCI_NODE_ROOT (1 << 30) 232 233#define OHCI_ASYSRCBUS 1 234 235 fwohcireg_t phy_access; /* PHY cntl 0xec */ 236#define PHYDEV_RDDONE (1<<31) 237#define PHYDEV_RDCMD (1<<15) 238#define PHYDEV_WRCMD (1<<14) 239#define PHYDEV_REGADDR 8 240#define PHYDEV_WRDATA 0 241#define PHYDEV_RDADDR 24 242#define PHYDEV_RDDATA 16 243 244 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 245 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 246 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 247 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 248 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 249 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 250 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 251 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 252 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 253 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 254 255 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 256 257 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 258 259 struct ohci_dma{ 260 fwohcireg_t cntl; 261 262#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 263 264#define OHCI_CNTL_BUFFIL (0x1 << 31) 265#define OHCI_CNTL_ISOHDR (0x1 << 30) 266#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 267#define OHCI_CNTL_MULTICH (0x1 << 28) 268 269#define OHCI_CNTL_DMA_RUN (0x1 << 15) 270#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 271#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 272#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 273#define OHCI_CNTL_DMA_BT (0x1 << 8) 274#define OHCI_CNTL_DMA_BAD (0x1 << 7) 275#define OHCI_CNTL_DMA_STAT (0xff) 276 277 fwohcireg_t cntl_clr; 278 fwohcireg_t dummy0; 279 fwohcireg_t cmd; 280 fwohcireg_t match; 281 fwohcireg_t dummy1; 282 fwohcireg_t dummy2; 283 fwohcireg_t dummy3; 284 }; 285 /* 0x180, 0x184, 0x188, 0x18c */ 286 /* 0x190, 0x194, 0x198, 0x19c */ 287 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 288 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 289 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 290 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 291 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 292 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 293 struct ohci_dma dma_ch[0x4]; 294 295 /* 0x200, 0x204, 0x208, 0x20c */ 296 /* 0x210, 0x204, 0x208, 0x20c */ 297 struct ohci_itdma{ 298 fwohcireg_t cntl; 299 fwohcireg_t cntl_clr; 300 fwohcireg_t dummy0; 301 fwohcireg_t cmd; 302 }; 303 struct ohci_itdma dma_itch[0x20]; 304 305 /* 0x400, 0x404, 0x408, 0x40c */ 306 /* 0x410, 0x404, 0x408, 0x40c */ 307 308 struct ohci_dma dma_irch[0x20]; 309}; 310 311struct fwohcidb_tr{ 312 STAILQ_ENTRY(fwohcidb_tr) link; 313 struct fw_xfer *xfer; 314 volatile struct fwohcidb *db; 315 bus_dmamap_t dma_map; 316 caddr_t buf; 317 bus_addr_t bus_addr; 318 int dbcnt; 319}; 320 321/* 322 * OHCI info structure. 323 */ 324struct fwohci_txpkthdr{ 325 union{ 326 u_int32_t ld[4]; 327 struct { 328#if BYTE_ORDER == BIG_ENDIAN 329 u_int32_t :13, 330 spd:3, 331 :8, 332 tcode:4, 333 :4; 334#else 335 u_int32_t :4, 336 tcode:4, 337 :8, 338 spd:3, 339 :13; 340#endif 341 }common; 342 struct { 343#if BYTE_ORDER == BIG_ENDIAN 344 u_int32_t :8, 345 srcbus:1, 346 :4, 347 spd:3, 348 tlrt:8, 349 tcode:4, 350 :4; 351#else 352 u_int32_t :4, 353 tcode:4, 354 tlrt:8, 355 spd:3, 356 :4, 357 srcbus:1, 358 :8; 359#endif 360 BIT16x2(dst, ); 361 }asycomm; 362 struct { 363#if BYTE_ORDER == BIG_ENDIAN 364 u_int32_t :13, 365 spd:3, 366 chtag:8, 367 tcode:4, 368 sy:4; 369#else 370 u_int32_t sy:4, 371 tcode:4, 372 chtag:8, 373 spd:3, 374 :13; 375#endif 376 BIT16x2(len, ); 377 }stream; 378 }mode; 379}; 380struct fwohci_trailer{ 381 u_int32_t time:16, 382 stat:16; 383}; 384 385#define OHCI_CNTL_CYCSRC (0x1 << 22) 386#define OHCI_CNTL_CYCMTR (0x1 << 21) 387#define OHCI_CNTL_CYCTIMER (0x1 << 20) 388#define OHCI_CNTL_PHYPKT (0x1 << 10) 389#define OHCI_CNTL_SID (0x1 << 9) 390 391#define OHCI_INT_DMA_ATRQ (0x1 << 0) 392#define OHCI_INT_DMA_ATRS (0x1 << 1) 393#define OHCI_INT_DMA_ARRQ (0x1 << 2) 394#define OHCI_INT_DMA_ARRS (0x1 << 3) 395#define OHCI_INT_DMA_PRRQ (0x1 << 4) 396#define OHCI_INT_DMA_PRRS (0x1 << 5) 397#define OHCI_INT_DMA_IT (0x1 << 6) 398#define OHCI_INT_DMA_IR (0x1 << 7) 399#define OHCI_INT_PW_ERR (0x1 << 8) 400#define OHCI_INT_LR_ERR (0x1 << 9) 401 402#define OHCI_INT_PHY_SID (0x1 << 16) 403#define OHCI_INT_PHY_BUS_R (0x1 << 17) 404 405#define OHCI_INT_REG_FAIL (0x1 << 18) 406 407#define OHCI_INT_PHY_INT (0x1 << 19) 408#define OHCI_INT_CYC_START (0x1 << 20) 409#define OHCI_INT_CYC_64SECOND (0x1 << 21) 410#define OHCI_INT_CYC_LOST (0x1 << 22) 411#define OHCI_INT_CYC_ERR (0x1 << 23) 412 413#define OHCI_INT_ERR (0x1 << 24) 414#define OHCI_INT_CYC_LONG (0x1 << 25) 415#define OHCI_INT_PHY_REG (0x1 << 26) 416 417#define OHCI_INT_EN (0x1 << 31) 418 419#define IP_CHANNELS 0x0234 420#define FWOHCI_MAXREC 2048 421 422#define OHCI_ISORA 0x02 423#define OHCI_ISORB 0x04 424 425#define FWOHCITCODE_PHY 0xe 426