fwohcireg.h revision 108276
1/* 2 * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 108276 2002-12-26 03:17:59Z simokawa $ 34 * 35 */ 36#define PCI_CBMEM 0x10 37 38#define FW_VENDORID_NEC 0x1033 39#define FW_VENDORID_TI 0x104c 40#define FW_VENDORID_SONY 0x104d 41#define FW_VENDORID_VIA 0x1106 42#define FW_VENDORID_RICOH 0x1180 43#define FW_VENDORID_APPLE 0x106b 44#define FW_VENDORID_LUCENT 0x11c1 45 46#define FW_DEVICE_UPD861 0x0063 47#define FW_DEVICE_TITSB22 0x8009 48#define FW_DEVICE_TITSB23 0x8019 49#define FW_DEVICE_TITSB26 0x8020 50#define FW_DEVICE_TITSB43 0x8021 51#define FW_DEVICE_CX3022 0x8039 52#define FW_DEVICE_VT6306 0x3044 53#define FW_DEVICE_R5C552 0x1180 54#define FW_DEVICE_PANGEA 0x0030 55#define FW_DEVICE_UNINORTH 0x0031 56#define FW_DEVICE_FW322 0x5811 57 58#define PCI_INTERFACE_OHCI 0x10 59 60#define FW_OHCI_BASE_REG 0x10 61 62#define OHCI_DMA_ITCH 0x20 63#define OHCI_DMA_IRCH 0x20 64 65#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 66 67 68typedef volatile u_int32_t fwohcireg_t; 69 70struct fwohcidb { 71 union { 72 struct { 73 volatile u_int32_t cmd; 74 volatile u_int32_t addr; 75 volatile u_int32_t depend; 76 volatile u_int32_t count:16, 77 status:16; 78 } desc; 79 volatile u_int32_t immed[4]; 80 } db; 81#define OHCI_OUTPUT_MORE (0 << 28) 82#define OHCI_OUTPUT_LAST (1 << 28) 83#define OHCI_INPUT_MORE (2 << 28) 84#define OHCI_INPUT_LAST (3 << 28) 85#define OHCI_STORE_QUAD (4 << 28) 86#define OHCI_LOAD_QUAD (5 << 28) 87#define OHCI_NOP (6 << 28) 88#define OHCI_STOP (7 << 28) 89#define OHCI_STORE (8 << 28) 90#define OHCI_CMD_MASK (0xf << 28) 91 92#define OHCI_UPDATE (1 << 27) 93 94#define OHCI_KEY_ST0 (0 << 24) 95#define OHCI_KEY_ST1 (1 << 24) 96#define OHCI_KEY_ST2 (2 << 24) 97#define OHCI_KEY_ST3 (3 << 24) 98#define OHCI_KEY_REGS (5 << 24) 99#define OHCI_KEY_SYS (6 << 24) 100#define OHCI_KEY_DEVICE (7 << 24) 101#define OHCI_KEY_MASK (7 << 24) 102 103#define OHCI_INTERRUPT_NEVER (0 << 20) 104#define OHCI_INTERRUPT_TRUE (1 << 20) 105#define OHCI_INTERRUPT_FALSE (2 << 20) 106#define OHCI_INTERRUPT_ALWAYS (3 << 20) 107 108#define OHCI_BRANCH_NEVER (0 << 18) 109#define OHCI_BRANCH_TRUE (1 << 18) 110#define OHCI_BRANCH_FALSE (2 << 18) 111#define OHCI_BRANCH_ALWAYS (3 << 18) 112#define OHCI_BRANCH_MASK (3 << 18) 113 114#define OHCI_WAIT_NEVER (0 << 16) 115#define OHCI_WAIT_TRUE (1 << 16) 116#define OHCI_WAIT_FALSE (2 << 16) 117#define OHCI_WAIT_ALWAYS (3 << 16) 118}; 119 120#define OHCI_SPD_S100 0x4 121#define OHCI_SPD_S200 0x1 122#define OHCI_SPD_S400 0x2 123 124 125#define FWOHCIEV_NOSTAT 0 126#define FWOHCIEV_LONGP 2 127#define FWOHCIEV_MISSACK 3 128#define FWOHCIEV_UNDRRUN 4 129#define FWOHCIEV_OVRRUN 5 130#define FWOHCIEV_DESCERR 6 131#define FWOHCIEV_DTRDERR 7 132#define FWOHCIEV_DTWRERR 8 133#define FWOHCIEV_BUSRST 9 134#define FWOHCIEV_TIMEOUT 0xa 135#define FWOHCIEV_TCODERR 0xb 136#define FWOHCIEV_UNKNOWN 0xe 137#define FWOHCIEV_FLUSHED 0xf 138#define FWOHCIEV_ACKCOMPL 0x11 139#define FWOHCIEV_ACKPEND 0x12 140#define FWOHCIEV_ACKBSX 0x14 141#define FWOHCIEV_ACKBSA 0x15 142#define FWOHCIEV_ACKBSB 0x16 143#define FWOHCIEV_ACKTARD 0x1b 144#define FWOHCIEV_ACKDERR 0x1d 145#define FWOHCIEV_ACKTERR 0x1e 146 147#define FWOHCIEV_MASK 0x1f 148 149struct ohci_registers { 150 fwohcireg_t ver; /* Version No. 0x0 */ 151 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 152 fwohcireg_t retry; /* AT retries 0x8 */ 153#define FWOHCI_RETRY 0x8 154 fwohcireg_t csr_data; /* CSR data 0xc */ 155 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 156 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 157 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 158 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 159 fwohcireg_t bus_opt; /* BUS option 0x20 */ 160#define FWOHCIGUID_H 0x24 161#define FWOHCIGUID_L 0x28 162 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 163 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 164 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 165 fwohcireg_t config_rom; /* config ROM map 0x34 */ 166 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 167 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 168 fwohcireg_t vender; /* vender ID 0x40 */ 169 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 170 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 171 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 172#define OHCI_HCC_BIGEND (1 << 30) 173#define OHCI_HCC_PRPHY (1 << 23) 174#define OHCI_HCC_PHYEN (1 << 22) 175#define OHCI_HCC_LPS (1 << 19) 176#define OHCI_HCC_POSTWR (1 << 18) 177#define OHCI_HCC_LINKEN (1 << 17) 178#define OHCI_HCC_RESET (1 << 16) 179 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 180 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 181 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 182 fwohcireg_t sid_cnt; /* self id count 0x68 */ 183 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 184 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 185 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 186 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 187 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 188#define FWOHCI_INTSTAT 0x80 189#define FWOHCI_INTSTATCLR 0x84 190#define FWOHCI_INTMASK 0x88 191#define FWOHCI_INTMASKCLR 0x8c 192 fwohcireg_t int_stat; /* 0x80 */ 193 fwohcireg_t int_clear; /* 0x84 */ 194 fwohcireg_t int_mask; /* 0x88 */ 195 fwohcireg_t int_mask_clear; /* 0x8c */ 196 fwohcireg_t it_int_stat; /* 0x90 */ 197 fwohcireg_t it_int_clear; /* 0x94 */ 198 fwohcireg_t it_int_mask; /* 0x98 */ 199 fwohcireg_t it_mask_clear; /* 0x9c */ 200 fwohcireg_t ir_int_stat; /* 0xa0 */ 201 fwohcireg_t ir_int_clear; /* 0xa4 */ 202 fwohcireg_t ir_int_mask; /* 0xa8 */ 203 fwohcireg_t ir_mask_clear; /* 0xac */ 204 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 205 fwohcireg_t fairness; /* fairness control 0xdc */ 206 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 207 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 208#define FWOHCI_NODEID 0xe8 209 fwohcireg_t node; /* Node ID 0xe8 */ 210#define OHCI_NODE_VALID (1 << 31) 211#define OHCI_NODE_ROOT (1 << 30) 212 213#define OHCI_ASYSRCBUS 1 214 215 fwohcireg_t phy_access; /* PHY cntl 0xec */ 216#define PHYDEV_RDDONE (1<<31) 217#define PHYDEV_RDCMD (1<<15) 218#define PHYDEV_WRCMD (1<<14) 219#define PHYDEV_REGADDR 8 220#define PHYDEV_WRDATA 0 221#define PHYDEV_RDADDR 24 222#define PHYDEV_RDDATA 16 223 224 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 225 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 226 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 227 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 228 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 229 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 230 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 231 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 232 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 233 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 234 235 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 236 237 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 238 239 struct ohci_dma{ 240 fwohcireg_t cntl; 241 242#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 243 244#define OHCI_CNTL_BUFFIL (0x1 << 31) 245#define OHCI_CNTL_ISOHDR (0x1 << 30) 246#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 247#define OHCI_CNTL_MULTICH (0x1 << 28) 248 249#define OHCI_CNTL_DMA_RUN (0x1 << 15) 250#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 251#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 252#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 253#define OHCI_CNTL_DMA_BT (0x1 << 8) 254#define OHCI_CNTL_DMA_BAD (0x1 << 7) 255#define OHCI_CNTL_DMA_STAT (0xff) 256 257 fwohcireg_t cntl_clr; 258 fwohcireg_t dummy0; 259 fwohcireg_t cmd; 260 fwohcireg_t match; 261 fwohcireg_t dummy1; 262 fwohcireg_t dummy2; 263 fwohcireg_t dummy3; 264 }; 265 /* 0x180, 0x184, 0x188, 0x18c */ 266 /* 0x190, 0x194, 0x198, 0x19c */ 267 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 268 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 269 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 270 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 271 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 272 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 273 struct ohci_dma dma_ch[0x4]; 274 275 /* 0x200, 0x204, 0x208, 0x20c */ 276 /* 0x210, 0x204, 0x208, 0x20c */ 277 struct ohci_itdma{ 278 fwohcireg_t cntl; 279 fwohcireg_t cntl_clr; 280 fwohcireg_t dummy0; 281 fwohcireg_t cmd; 282 }; 283 struct ohci_itdma dma_itch[0x20]; 284 285 /* 0x400, 0x404, 0x408, 0x40c */ 286 /* 0x410, 0x404, 0x408, 0x40c */ 287 288 struct ohci_dma dma_irch[0x20]; 289}; 290 291struct fwohcidb_tr{ 292 STAILQ_ENTRY(fwohcidb_tr) link; 293 struct fw_xfer *xfer; 294 volatile struct fwohcidb *db; 295 caddr_t buf; 296 caddr_t dummy; 297 int dbcnt; 298}; 299 300/* 301 * OHCI info structure. 302 */ 303struct fwohci_txpkthdr{ 304 union{ 305 u_int32_t ld[4]; 306 struct { 307 u_int32_t res3:4, 308 tcode:4, 309 res2:8, 310 spd:3, 311 res1:13; 312 }common; 313 struct { 314 u_int32_t res3:4, 315 tcode:4, 316 tlrt:8, 317 spd:3, 318 res2:4, 319 srcbus:1, 320 res1:8; 321 u_int32_t res4:16, 322 dst:16; 323 }asycomm; 324 struct { 325 u_int32_t sy:4, 326 tcode:4, 327 chtag:8, 328 spd:3, 329 res1:13; 330 u_int32_t res2:16, 331 len:16; 332 }stream; 333 }mode; 334}; 335struct fwohci_trailer{ 336 u_int32_t time:16, 337 stat:16; 338}; 339 340#define OHCI_CNTL_CYCSRC (0x1 << 22) 341#define OHCI_CNTL_CYCMTR (0x1 << 21) 342#define OHCI_CNTL_CYCTIMER (0x1 << 20) 343#define OHCI_CNTL_PHYPKT (0x1 << 10) 344#define OHCI_CNTL_SID (0x1 << 9) 345 346#define OHCI_INT_DMA_ATRQ (0x1 << 0) 347#define OHCI_INT_DMA_ATRS (0x1 << 1) 348#define OHCI_INT_DMA_ARRQ (0x1 << 2) 349#define OHCI_INT_DMA_ARRS (0x1 << 3) 350#define OHCI_INT_DMA_PRRQ (0x1 << 4) 351#define OHCI_INT_DMA_PRRS (0x1 << 5) 352#define OHCI_INT_DMA_IT (0x1 << 6) 353#define OHCI_INT_DMA_IR (0x1 << 7) 354#define OHCI_INT_PW_ERR (0x1 << 8) 355#define OHCI_INT_LR_ERR (0x1 << 9) 356 357#define OHCI_INT_PHY_SID (0x1 << 16) 358#define OHCI_INT_PHY_BUS_R (0x1 << 17) 359 360#define OHCI_INT_REG_FAIL (0x1 << 18) 361 362#define OHCI_INT_PHY_INT (0x1 << 19) 363#define OHCI_INT_CYC_START (0x1 << 20) 364#define OHCI_INT_CYC_64SECOND (0x1 << 21) 365#define OHCI_INT_CYC_LOST (0x1 << 22) 366#define OHCI_INT_CYC_ERR (0x1 << 23) 367 368#define OHCI_INT_ERR (0x1 << 24) 369#define OHCI_INT_CYC_LONG (0x1 << 25) 370#define OHCI_INT_PHY_REG (0x1 << 26) 371 372#define OHCI_INT_EN (0x1 << 31) 373 374#define IP_CHANNELS 0x0234 375#define FWOHCI_MAXREC 2048 376 377#define OHCI_ISORA 0x02 378#define OHCI_ISORB 0x04 379 380#define FWOHCITCODE_PHY 0xe 381