fwohcireg.h revision 103285
1/* 2 * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 103285 2002-09-13 12:31:56Z ikob $ 34 * 35 */ 36#define PCI_CBMEM 0x10 37 38#define FW_VENDORID_NEC 0x1033 39#define FW_VENDORID_TI 0x104c 40#define FW_VENDORID_SONY 0x104d 41#define FW_VENDORID_VIA 0x1106 42#define FW_VENDORID_RICOH 0x1180 43 44#define FW_DEVICE_UPD861 0x0063 45#define FW_DEVICE_TITSB22 0x8009 46#define FW_DEVICE_TITSB23 0x8019 47#define FW_DEVICE_TITSB26 0x8020 48#define FW_DEVICE_TITSB43 0x8021 49#define FW_DEVICE_CX3022 0x8039 50#define FW_DEVICE_VT6306 0x3044 51#define FW_DEVICE_R5C552 0x1180 52 53#define PCI_INTERFACE_OHCI 0x10 54 55#define FW_OHCI_BASE_REG 0x10 56 57#define OHCI_DMA_ITCH 0x20 58#define OHCI_DMA_IRCH 0x20 59 60#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 61 62 63typedef volatile u_int32_t fwohcireg_t; 64 65struct fwohcidb { 66 union { 67 struct { 68 volatile u_int32_t cmd; 69 volatile u_int32_t addr; 70 volatile u_int32_t depend; 71 volatile u_int32_t count:16, 72 status:16; 73 } desc; 74 volatile u_int32_t immed[4]; 75 } db; 76#define OHCI_OUTPUT_MORE (0 << 28) 77#define OHCI_OUTPUT_LAST (1 << 28) 78#define OHCI_INPUT_MORE (2 << 28) 79#define OHCI_INPUT_LAST (3 << 28) 80#define OHCI_STORE_QUAD (4 << 28) 81#define OHCI_LOAD_QUAD (5 << 28) 82#define OHCI_NOP (6 << 28) 83#define OHCI_STOP (7 << 28) 84#define OHCI_STORE (8 << 28) 85#define OHCI_CMD_MASK (0xf << 28) 86 87#define OHCI_UPDATE (1 << 27) 88 89#define OHCI_KEY_ST0 (0 << 24) 90#define OHCI_KEY_ST1 (1 << 24) 91#define OHCI_KEY_ST2 (2 << 24) 92#define OHCI_KEY_ST3 (3 << 24) 93#define OHCI_KEY_REGS (5 << 24) 94#define OHCI_KEY_SYS (6 << 24) 95#define OHCI_KEY_DEVICE (7 << 24) 96#define OHCI_KEY_MASK (7 << 24) 97 98#define OHCI_INTERRUPT_NEVER (0 << 20) 99#define OHCI_INTERRUPT_TRUE (1 << 20) 100#define OHCI_INTERRUPT_FALSE (2 << 20) 101#define OHCI_INTERRUPT_ALWAYS (3 << 20) 102 103#define OHCI_BRANCH_NEVER (0 << 18) 104#define OHCI_BRANCH_TRUE (1 << 18) 105#define OHCI_BRANCH_FALSE (2 << 18) 106#define OHCI_BRANCH_ALWAYS (3 << 18) 107#define OHCI_BRANCH_MASK (3 << 18) 108 109#define OHCI_WAIT_NEVER (0 << 16) 110#define OHCI_WAIT_TRUE (1 << 16) 111#define OHCI_WAIT_FALSE (2 << 16) 112#define OHCI_WAIT_ALWAYS (3 << 16) 113}; 114 115#define OHCI_SPD_S100 0x4 116#define OHCI_SPD_S200 0x1 117#define OHCI_SPD_S400 0x2 118 119 120#define FWOHCIEV_NOSTAT 0 121#define FWOHCIEV_LONGP 2 122#define FWOHCIEV_MISSACK 3 123#define FWOHCIEV_UNDRRUN 4 124#define FWOHCIEV_OVRRUN 5 125#define FWOHCIEV_DESCERR 6 126#define FWOHCIEV_DTRDERR 7 127#define FWOHCIEV_DTWRERR 8 128#define FWOHCIEV_BUSRST 9 129#define FWOHCIEV_TIMEOUT 0xa 130#define FWOHCIEV_TCODERR 0xb 131#define FWOHCIEV_UNKNOWN 0xe 132#define FWOHCIEV_FLUSHED 0xf 133#define FWOHCIEV_ACKCOMPL 0x11 134#define FWOHCIEV_ACKPEND 0x12 135#define FWOHCIEV_ACKBSX 0x14 136#define FWOHCIEV_ACKBSA 0x15 137#define FWOHCIEV_ACKBSB 0x16 138#define FWOHCIEV_ACKTARD 0x1b 139#define FWOHCIEV_ACKDERR 0x1d 140#define FWOHCIEV_ACKTERR 0x1e 141 142#define FWOHCIEV_MASK 0x1f 143 144struct ohci_registers { 145 fwohcireg_t ver; /* Version No. 0x0 */ 146 fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 147 fwohcireg_t retry; /* AT retries 0x8 */ 148#define FWOHCI_RETRY 0x8 149 fwohcireg_t csr_data; /* CSR data 0xc */ 150 fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 151 fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 152 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 153 fwohcireg_t bus_id; /* BUS_ID 0x1c */ 154 fwohcireg_t bus_opt; /* BUS option 0x20 */ 155#define FWOHCIGUID_H 0x24 156#define FWOHCIGUID_L 0x28 157 fwohcireg_t guid_hi; /* GUID hi 0x24 */ 158 fwohcireg_t guid_lo; /* GUID lo 0x28 */ 159 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 160 fwohcireg_t config_rom; /* config ROM map 0x34 */ 161 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 162 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 163 fwohcireg_t vender; /* vender ID 0x40 */ 164 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 165 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 166 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 167#define OHCI_HCC_BIGEND (1 << 30) 168#define OHCI_HCC_PRPHY (1 << 23) 169#define OHCI_HCC_PHYEN (1 << 22) 170#define OHCI_HCC_LPS (1 << 19) 171#define OHCI_HCC_POSTWR (1 << 18) 172#define OHCI_HCC_LINKEN (1 << 17) 173#define OHCI_HCC_RESET (1 << 16) 174 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 175 fwohcireg_t dummy3[1]; /* dummy 0x60 */ 176 fwohcireg_t sid_buf; /* self id buffer 0x64 */ 177 fwohcireg_t sid_cnt; /* self id count 0x68 */ 178 fwohcireg_t dummy4[1]; /* dummy 0x6c */ 179 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 180 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 181 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 182 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 183#define FWOHCI_INTSTAT 0x80 184#define FWOHCI_INTSTATCLR 0x84 185#define FWOHCI_INTMASK 0x88 186#define FWOHCI_INTMASKCLR 0x8c 187 fwohcireg_t int_stat; /* 0x80 */ 188 fwohcireg_t int_clear; /* 0x84 */ 189 fwohcireg_t int_mask; /* 0x88 */ 190 fwohcireg_t int_mask_clear; /* 0x8c */ 191 fwohcireg_t it_int_stat; /* 0x90 */ 192 fwohcireg_t it_int_clear; /* 0x94 */ 193 fwohcireg_t it_int_mask; /* 0x98 */ 194 fwohcireg_t it_mask_clear; /* 0x9c */ 195 fwohcireg_t ir_int_stat; /* 0xa0 */ 196 fwohcireg_t ir_int_clear; /* 0xa4 */ 197 fwohcireg_t ir_int_mask; /* 0xa8 */ 198 fwohcireg_t ir_mask_clear; /* 0xac */ 199 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 200 fwohcireg_t fairness; /* fairness control 0xdc */ 201 fwohcireg_t link_cntl; /* Chip control 0xe0*/ 202 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 203#define FWOHCI_NODEID 0xe8 204 fwohcireg_t node; /* Node ID 0xe8 */ 205#define OHCI_NODE_VALID (1 << 31) 206#define OHCI_NODE_ROOT (1 << 30) 207 208#define OHCI_ASYSRCBUS 1 209 210 fwohcireg_t phy_access; /* PHY cntl 0xec */ 211#define PHYDEV_RDDONE (1<<31) 212#define PHYDEV_RDCMD (1<<15) 213#define PHYDEV_WRCMD (1<<14) 214#define PHYDEV_REGADDR 8 215#define PHYDEV_WRDATA 0 216#define PHYDEV_RDADDR 24 217#define PHYDEV_RDDATA 16 218 219 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 220 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 221 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 222 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 223 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 224 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 225 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 226 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 227 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 228 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 229 230 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 231 232 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 233 234 struct ohci_dma{ 235 fwohcireg_t cntl; 236 237#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 238 239#define OHCI_CNTL_BUFFIL (0x1 << 31) 240#define OHCI_CNTL_ISOHDR (0x1 << 30) 241#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 242#define OHCI_CNTL_MULTICH (0x1 << 28) 243 244#define OHCI_CNTL_DMA_RUN (0x1 << 15) 245#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 246#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 247#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 248#define OHCI_CNTL_DMA_BT (0x1 << 8) 249#define OHCI_CNTL_DMA_BAD (0x1 << 7) 250#define OHCI_CNTL_DMA_STAT (0xff) 251 252 fwohcireg_t cntl_clr; 253 fwohcireg_t dummy0; 254 fwohcireg_t cmd; 255 fwohcireg_t match; 256 fwohcireg_t dummy1; 257 fwohcireg_t dummy2; 258 fwohcireg_t dummy3; 259 }; 260 /* 0x180, 0x184, 0x188, 0x18c */ 261 /* 0x190, 0x194, 0x198, 0x19c */ 262 /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 263 /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 264 /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 265 /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 266 /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 267 /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 268 struct ohci_dma dma_ch[0x4]; 269 270 /* 0x200, 0x204, 0x208, 0x20c */ 271 /* 0x210, 0x204, 0x208, 0x20c */ 272 struct ohci_itdma{ 273 fwohcireg_t cntl; 274 fwohcireg_t cntl_clr; 275 fwohcireg_t dummy0; 276 fwohcireg_t cmd; 277 }; 278 struct ohci_itdma dma_itch[0x20]; 279 280 /* 0x400, 0x404, 0x408, 0x40c */ 281 /* 0x410, 0x404, 0x408, 0x40c */ 282 283 struct ohci_dma dma_irch[0x20]; 284}; 285 286struct fwohcidb_tr{ 287 STAILQ_ENTRY(fwohcidb_tr) link; 288 struct fw_xfer *xfer; 289 volatile struct fwohcidb *db; 290 caddr_t buf; 291 caddr_t dummy; 292 int dbcnt; 293}; 294 295/* 296 * OHCI info structure. 297 */ 298#if 0 299struct fwohci_softc { 300 struct fw_softc fc; 301 volatile struct ohci_registers *base; 302 int init; 303#define SIDPHASE 1 304 u_int32_t flags; 305 struct fwohcidb_tr *db_tr[OHCI_MAX_DMA_CH]; 306 struct fwohcidb_tr *db_first[OHCI_MAX_DMA_CH]; 307 struct fwohcidb_tr *db_last[OHCI_MAX_DMA_CH]; 308 struct { 309 int tail; 310 struct fwohcidb_tr *db_tr; 311 struct fwohcidb *db; 312 }dbdvtx[MAX_DVFRAME], dbdvrx[MAX_DVFRAME]; 313 int ndb[OHCI_MAX_DMA_CH]; 314 u_int32_t isohdr[OHCI_MAX_DMA_CH]; 315 int queued[OHCI_MAX_DMA_CH]; 316 int dma_ch[OHCI_MAX_DMA_CH]; 317}; 318#endif 319struct fwohci_txpkthdr{ 320 union{ 321 u_int32_t ld[4]; 322 struct { 323 u_int32_t res3:4, 324 tcode:4, 325 res2:8, 326 spd:3, 327 res1:13; 328 }common; 329 struct { 330 u_int32_t res3:4, 331 tcode:4, 332 tlrt:8, 333 spd:3, 334 res2:4, 335 srcbus:1, 336 res1:8; 337 u_int32_t res4:16, 338 dst:16; 339 }asycomm; 340 struct { 341 u_int32_t sy:4, 342 tcode:4, 343 chtag:8, 344 spd:3, 345 res1:13; 346 u_int32_t res2:16, 347 len:16; 348 }stream; 349 }mode; 350}; 351struct fwohci_trailer{ 352 u_int32_t time:16, 353 stat:16; 354}; 355 356#define OHCI_CNTL_CYCSRC (0x1 << 22) 357#define OHCI_CNTL_CYCMTR (0x1 << 21) 358#define OHCI_CNTL_CYCTIMER (0x1 << 20) 359#define OHCI_CNTL_PHYPKT (0x1 << 10) 360#define OHCI_CNTL_SID (0x1 << 9) 361 362#define OHCI_INT_DMA_ATRQ (0x1 << 0) 363#define OHCI_INT_DMA_ATRS (0x1 << 1) 364#define OHCI_INT_DMA_ARRQ (0x1 << 2) 365#define OHCI_INT_DMA_ARRS (0x1 << 3) 366#define OHCI_INT_DMA_PRRQ (0x1 << 4) 367#define OHCI_INT_DMA_PRRS (0x1 << 5) 368#define OHCI_INT_DMA_IT (0x1 << 6) 369#define OHCI_INT_DMA_IR (0x1 << 7) 370#define OHCI_INT_PW_ERR (0x1 << 8) 371#define OHCI_INT_LR_ERR (0x1 << 9) 372 373#define OHCI_INT_PHY_SID (0x1 << 16) 374#define OHCI_INT_PHY_BUS_R (0x1 << 17) 375 376#define OHCI_INT_PHY_INT (0x1 << 19) 377#define OHCI_INT_CYC_START (0x1 << 20) 378#define OHCI_INT_CYC_64SECOND (0x1 << 21) 379#define OHCI_INT_CYC_LOST (0x1 << 22) 380#define OHCI_INT_CYC_ERR (0x1 << 23) 381 382#define OHCI_INT_ERR (0x1 << 24) 383#define OHCI_INT_CYC_LONG (0x1 << 25) 384#define OHCI_INT_PHY_REG (0x1 << 26) 385 386#define OHCI_INT_EN (0x1 << 31) 387 388#define IP_CHANNELS 0x0234 389#define FWOHCI_MAXREC 2048 390 391#define OHCI_ISORA 0x02 392#define OHCI_ISORB 0x04 393 394#define FWOHCITCODE_PHY 0xe 395