1256806Sian/*- 2256806Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3256806Sian * All rights reserved. 4256806Sian * 5256806Sian * Redistribution and use in source and binary forms, with or without 6256806Sian * modification, are permitted provided that the following conditions 7256806Sian * are met: 8256806Sian * 1. Redistributions of source code must retain the above copyright 9256806Sian * notice, this list of conditions and the following disclaimer. 10256806Sian * 2. Redistributions in binary form must reproduce the above copyright 11256806Sian * notice, this list of conditions and the following disclaimer in the 12256806Sian * documentation and/or other materials provided with the distribution. 13256806Sian * 14256806Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15256806Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16256806Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17256806Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18256806Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19256806Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20256806Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21256806Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22256806Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23256806Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24256806Sian * SUCH DAMAGE. 25256806Sian * 26256806Sian */ 27256806Sian 28256806Sian#ifndef IF_FFECREG_H 29256806Sian#define IF_FFECREG_H 30256806Sian 31256806Sian#include <sys/cdefs.h> 32256806Sian__FBSDID("$FreeBSD: releng/11.0/sys/dev/ffec/if_ffecreg.h 258780 2013-11-30 22:17:27Z eadler $"); 33256806Sian 34256806Sian/* 35256806Sian * Hardware defines for Freescale Fast Ethernet Controller. 36256806Sian */ 37256806Sian 38256806Sian/* 39256806Sian * MAC registers. 40256806Sian */ 41256806Sian#define FEC_IER_REG 0x0004 42256806Sian#define FEC_IEM_REG 0x0008 43258780Seadler#define FEC_IER_HBERR (1U << 31) 44256806Sian#define FEC_IER_BABR (1 << 30) 45256806Sian#define FEC_IER_BABT (1 << 29) 46256806Sian#define FEC_IER_GRA (1 << 28) 47256806Sian#define FEC_IER_TXF (1 << 27) 48256806Sian#define FEC_IER_TXB (1 << 26) 49256806Sian#define FEC_IER_RXF (1 << 25) 50256806Sian#define FEC_IER_RXB (1 << 24) 51256806Sian#define FEC_IER_MII (1 << 23) 52256806Sian#define FEC_IER_EBERR (1 << 22) 53256806Sian#define FEC_IER_LC (1 << 21) 54256806Sian#define FEC_IER_RL (1 << 20) 55256806Sian#define FEC_IER_UN (1 << 19) 56256806Sian#define FEC_IER_PLR (1 << 18) 57256806Sian#define FEC_IER_WAKEUP (1 << 17) 58256806Sian#define FEC_IER_AVAIL (1 << 16) 59256806Sian#define FEC_IER_TIMER (1 << 15) 60256806Sian 61256806Sian#define FEC_RDAR_REG 0x0010 62256806Sian#define FEC_RDAR_RDAR (1 << 24) 63256806Sian 64256806Sian#define FEC_TDAR_REG 0x0014 65256806Sian#define FEC_TDAR_TDAR (1 << 24) 66256806Sian 67256806Sian#define FEC_ECR_REG 0x0024 68256806Sian#define FEC_ECR_DBSWP (1 << 8) 69256806Sian#define FEC_ECR_STOPEN (1 << 7) 70256806Sian#define FEC_ECR_DBGEN (1 << 6) 71256806Sian#define FEC_ECR_SPEED (1 << 5) 72256806Sian#define FEC_ECR_EN1588 (1 << 4) 73256806Sian#define FEC_ECR_SLEEP (1 << 3) 74256806Sian#define FEC_ECR_MAGICEN (1 << 2) 75256806Sian#define FEC_ECR_ETHEREN (1 << 1) 76256806Sian#define FEC_ECR_RESET (1 << 0) 77256806Sian 78256806Sian#define FEC_MMFR_REG 0x0040 79256806Sian#define FEC_MMFR_ST_SHIFT 30 80256806Sian#define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT) 81256806Sian#define FEC_MMFR_OP_SHIFT 28 82256806Sian#define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT) 83256806Sian#define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT) 84256806Sian#define FEC_MMFR_PA_SHIFT 23 85256806Sian#define FEC_MMFR_PA_MASK (0x1f << FEC_MMFR_PA_SHIFT) 86256806Sian#define FEC_MMFR_RA_SHIFT 18 87256806Sian#define FEC_MMFR_RA_MASK (0x1f << FEC_MMFR_RA_SHIFT) 88256806Sian#define FEC_MMFR_TA_SHIFT 16 89256806Sian#define FEC_MMFR_TA_VALUE (0x02 << FEC_MMFR_TA_SHIFT) 90256806Sian#define FEC_MMFR_DATA_SHIFT 0 91256806Sian#define FEC_MMFR_DATA_MASK (0xffff << FEC_MMFR_DATA_SHIFT) 92256806Sian 93256806Sian#define FEC_MSCR_REG 0x0044 94256806Sian#define FEC_MSCR_HOLDTIME_SHIFT 8 95256806Sian#define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT) 96256806Sian#define FEC_MSCR_DIS_PRE (1 << 7) 97256806Sian#define FEC_MSCR_MII_SPEED_SHIFT 1 98256806Sian#define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT) 99256806Sian 100256806Sian#define FEC_MIBC_REG 0x0064 101258780Seadler#define FEC_MIBC_DIS (1U << 31) 102256806Sian#define FEC_MIBC_IDLE (1 << 30) 103256806Sian#define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */ 104256806Sian 105256806Sian#define FEC_RCR_REG 0x0084 106258780Seadler#define FEC_RCR_GRS (1U << 31) 107256806Sian#define FEC_RCR_NLC (1 << 30) 108256806Sian#define FEC_RCR_MAX_FL_SHIFT 16 109256806Sian#define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT) 110256806Sian#define FEC_RCR_CFEN (1 << 15) 111256806Sian#define FEC_RCR_CRCFWD (1 << 14) 112256806Sian#define FEC_RCR_PAUFWD (1 << 13) 113256806Sian#define FEC_RCR_PADEN (1 << 12) 114256806Sian#define FEC_RCR_RMII_10T (1 << 9) 115256806Sian#define FEC_RCR_RMII_MODE (1 << 8) 116256806Sian#define FEC_RCR_RGMII_EN (1 << 6) 117256806Sian#define FEC_RCR_FCE (1 << 5) 118256806Sian#define FEC_RCR_BC_REJ (1 << 4) 119256806Sian#define FEC_RCR_PROM (1 << 3) 120256806Sian#define FEC_RCR_MII_MODE (1 << 2) 121256806Sian#define FEC_RCR_DRT (1 << 1) 122256806Sian#define FEC_RCR_LOOP (1 << 0) 123256806Sian 124256806Sian#define FEC_TCR_REG 0x00c4 125256806Sian#define FEC_TCR_ADDINS (1 << 9) 126256806Sian#define FEC_TCR_ADDSEL_SHIFT 5 127256806Sian#define FEC_TCR_ADDSEL_MASK (0x07 << FEC_TCR_ADDSEL_SHIFT) 128256806Sian#define FEC_TCR_RFC_PAUSE (1 << 4) 129256806Sian#define FEC_TCR_TFC_PAUSE (1 << 3) 130256806Sian#define FEC_TCR_FDEN (1 << 2) 131256806Sian#define FEC_TCR_GTS (1 << 0) 132256806Sian 133256806Sian#define FEC_PALR_REG 0x00e4 134256806Sian#define FEC_PALR_PADDR1_SHIFT 0 135256806Sian#define FEC_PALR_PADDR1_MASK (0xffffffff << FEC_PALR_PADDR1_SHIFT) 136256806Sian 137256806Sian#define FEC_PAUR_REG 0x00e8 138256806Sian#define FEC_PAUR_PADDR2_SHIFT 16 139256806Sian#define FEC_PAUR_PADDR2_MASK (0xffff << FEC_PAUR_PADDR2_SHIFT) 140256806Sian#define FEC_PAUR_TYPE_VALUE (0x8808) 141256806Sian 142256806Sian#define FEC_OPD_REG 0x00ec 143256806Sian#define FEC_OPD_PAUSE_DUR_SHIFT 0 144256806Sian#define FEC_OPD_PAUSE_DUR_MASK (0xffff << FEC_OPD_PAUSE_DUR_SHIFT) 145256806Sian 146256806Sian#define FEC_IAUR_REG 0x0118 147256806Sian#define FEC_IALR_REG 0x011c 148256806Sian 149256806Sian#define FEC_GAUR_REG 0x0120 150256806Sian#define FEC_GALR_REG 0x0124 151256806Sian 152256806Sian#define FEC_TFWR_REG 0x0144 153256806Sian#define FEC_TFWR_STRFWD (1 << 8) 154256806Sian#define FEC_TFWR_TWFR_SHIFT 0 155256806Sian#define FEC_TFWR_TWFR_MASK (0x3f << FEC_TFWR_TWFR_SHIFT) 156256806Sian#define FEC_TFWR_TWFR_128BYTE (0x02 << FEC_TFWR_TWFR_SHIFT) 157256806Sian 158256806Sian#define FEC_RDSR_REG 0x0180 159256806Sian 160256806Sian#define FEC_TDSR_REG 0x0184 161256806Sian 162256806Sian#define FEC_MRBR_REG 0x0188 163256806Sian#define FEC_MRBR_R_BUF_SIZE_SHIFT 0 164256806Sian#define FEC_MRBR_R_BUF_SIZE_MASK (0x3fff << FEC_MRBR_R_BUF_SIZE_SHIFT) 165256806Sian 166256806Sian#define FEC_RSFL_REG 0x0190 167256806Sian#define FEC_RSEM_REG 0x0194 168256806Sian#define FEC_RAEM_REG 0x0198 169256806Sian#define FEC_RAFL_REG 0x019c 170256806Sian#define FEC_TSEM_REG 0x01a0 171256806Sian#define FEC_TAEM_REG 0x01a4 172256806Sian#define FEC_TAFL_REG 0x01a8 173256806Sian#define FEC_TIPG_REG 0x01ac 174256806Sian#define FEC_FTRL_REG 0x01b0 175256806Sian 176256806Sian#define FEC_TACC_REG 0x01c0 177256806Sian#define FEC_TACC_PROCHK (1 << 4) 178256806Sian#define FEC_TACC_IPCHK (1 << 3) 179256806Sian#define FEC_TACC_SHIFT16 (1 << 0) 180256806Sian 181256806Sian#define FEC_RACC_REG 0x01c4 182256806Sian#define FEC_RACC_SHIFT16 (1 << 7) 183256806Sian#define FEC_RACC_LINEDIS (1 << 6) 184256806Sian#define FEC_RACC_PRODIS (1 << 2) 185256806Sian#define FEC_RACC_IPDIS (1 << 1) 186256806Sian#define FEC_RACC_PADREM (1 << 0) 187256806Sian 188256806Sian/* 189256806Sian * Statistics registers 190256806Sian */ 191256806Sian#define FEC_RMON_T_DROP 0x200 192256806Sian#define FEC_RMON_T_PACKETS 0x204 193256806Sian#define FEC_RMON_T_BC_PKT 0x208 194256806Sian#define FEC_RMON_T_MC_PKT 0x20C 195256806Sian#define FEC_RMON_T_CRC_ALIGN 0x210 196256806Sian#define FEC_RMON_T_UNDERSIZE 0x214 197256806Sian#define FEC_RMON_T_OVERSIZE 0x218 198256806Sian#define FEC_RMON_T_FRAG 0x21C 199256806Sian#define FEC_RMON_T_JAB 0x220 200256806Sian#define FEC_RMON_T_COL 0x224 201256806Sian#define FEC_RMON_T_P64 0x228 202256806Sian#define FEC_RMON_T_P65TO127 0x22C 203256806Sian#define FEC_RMON_T_P128TO255 0x230 204256806Sian#define FEC_RMON_T_P256TO511 0x234 205256806Sian#define FEC_RMON_T_P512TO1023 0x238 206256806Sian#define FEC_RMON_T_P1024TO2047 0x23C 207256806Sian#define FEC_RMON_T_P_GTE2048 0x240 208256806Sian#define FEC_RMON_T_OCTECTS 0x240 209256806Sian#define FEC_IEEE_T_DROP 0x248 210256806Sian#define FEC_IEEE_T_FRAME_OK 0x24C 211256806Sian#define FEC_IEEE_T_1COL 0x250 212256806Sian#define FEC_IEEE_T_MCOL 0x254 213256806Sian#define FEC_IEEE_T_DEF 0x258 214256806Sian#define FEC_IEEE_T_LCOL 0x25C 215256806Sian#define FEC_IEEE_T_EXCOL 0x260 216256806Sian#define FEC_IEEE_T_MACERR 0x264 217256806Sian#define FEC_IEEE_T_CSERR 0x268 218256806Sian#define FEC_IEEE_T_SQE 0x26C 219256806Sian#define FEC_IEEE_T_FDXFC 0x270 220256806Sian#define FEC_IEEE_T_OCTETS_OK 0x274 221256806Sian#define FEC_RMON_R_PACKETS 0x284 222256806Sian#define FEC_RMON_R_BC_PKT 0x288 223256806Sian#define FEC_RMON_R_MC_PKT 0x28C 224256806Sian#define FEC_RMON_R_CRC_ALIGN 0x290 225256806Sian#define FEC_RMON_R_UNDERSIZE 0x294 226256806Sian#define FEC_RMON_R_OVERSIZE 0x298 227256806Sian#define FEC_RMON_R_FRAG 0x29C 228256806Sian#define FEC_RMON_R_JAB 0x2A0 229256806Sian#define FEC_RMON_R_RESVD_0 0x2A4 230256806Sian#define FEC_RMON_R_P64 0x2A8 231256806Sian#define FEC_RMON_R_P65TO127 0x2AC 232256806Sian#define FEC_RMON_R_P128TO255 0x2B0 233256806Sian#define FEC_RMON_R_P256TO511 0x2B4 234256806Sian#define FEC_RMON_R_P512TO1023 0x2B8 235256806Sian#define FEC_RMON_R_P1024TO2047 0x2BC 236256806Sian#define FEC_RMON_R_P_GTE2048 0x2C0 237256806Sian#define FEC_RMON_R_OCTETS 0x2C4 238256806Sian#define FEC_IEEE_R_DROP 0x2C8 239256806Sian#define FEC_IEEE_R_FRAME_OK 0x2CC 240256806Sian#define FEC_IEEE_R_CRC 0x2D0 241256806Sian#define FEC_IEEE_R_ALIGN 0x2D4 242256806Sian#define FEC_IEEE_R_MACERR 0x2D8 243256806Sian#define FEC_IEEE_R_FDXFC 0x2DC 244256806Sian#define FEC_IEEE_R_OCTETS_OK 0x2E0 245256806Sian 246256806Sian#define FEC_MIIGSK_CFGR 0x300 247256806Sian#define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */ 248256806Sian#define FEC_MIIGSK_CFGR_LBMODE (1 << 4) /* loopback mode */ 249256806Sian#define FEC_MIIGSK_CFGR_EMODE (1 << 3) /* echo mode */ 250256806Sian#define FEC_MIIGSK_CFGR_IF_MODE_MASK (0x3 << 0) 251256806Sian#define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0) 252256806Sian#define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0) 253256806Sian 254256806Sian#define FEC_MIIGSK_ENR 0x308 255256806Sian#define FEC_MIIGSK_ENR_READY (1 << 2) 256256806Sian#define FEC_MIIGSK_ENR_EN (1 << 1) 257256806Sian 258256806Sian/* 259256806Sian * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 260256806Sian * layout, but the bits in the flags field have different meanings. 261256806Sian */ 262256806Sianstruct ffec_hwdesc 263256806Sian{ 264256806Sian uint32_t flags_len; 265256806Sian uint32_t buf_paddr; 266256806Sian}; 267256806Sian 268258780Seadler#define FEC_TXDESC_READY (1U << 31) 269256806Sian#define FEC_TXDESC_T01 (1 << 30) 270256806Sian#define FEC_TXDESC_WRAP (1 << 29) 271256806Sian#define FEC_TXDESC_T02 (1 << 28) 272256806Sian#define FEC_TXDESC_L (1 << 27) 273256806Sian#define FEC_TXDESC_TC (1 << 26) 274256806Sian#define FEC_TXDESC_ABC (1 << 25) 275256806Sian#define FEC_TXDESC_LEN_MASK (0xffff) 276256806Sian 277258780Seadler#define FEC_RXDESC_EMPTY (1U << 31) 278256806Sian#define FEC_RXDESC_R01 (1 << 30) 279256806Sian#define FEC_RXDESC_WRAP (1 << 29) 280256806Sian#define FEC_RXDESC_R02 (1 << 28) 281256806Sian#define FEC_RXDESC_L (1 << 27) 282256806Sian#define FEC_RXDESC_M (1 << 24) 283256806Sian#define FEC_RXDESC_BC (1 << 23) 284256806Sian#define FEC_RXDESC_MC (1 << 22) 285256806Sian#define FEC_RXDESC_LG (1 << 21) 286256806Sian#define FEC_RXDESC_NO (1 << 20) 287256806Sian#define FEC_RXDESC_CR (1 << 18) 288256806Sian#define FEC_RXDESC_OV (1 << 17) 289256806Sian#define FEC_RXDESC_TR (1 << 16) 290256806Sian#define FEC_RXDESC_LEN_MASK (0xffff) 291256806Sian 292256806Sian#define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \ 293256806Sian FEC_RXDESC_OV | FEC_RXDESC_TR) 294256806Sian 295256806Sian/* 296256806Sian * The hardware imposes alignment restrictions on various objects involved in 297256806Sian * DMA transfers. These values are expressed in bytes (not bits). 298256806Sian */ 299256806Sian#define FEC_DESC_RING_ALIGN 16 300256806Sian#define FEC_RXBUF_ALIGN 16 301256806Sian#define FEC_TXBUF_ALIGN 16 302256806Sian 303256806Sian#endif /* IF_FFECREG_H */ 304