excareg.h revision 89948
1/* $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $ */ 2/* $FreeBSD: head/sys/dev/exca/excareg.h 89948 2002-01-29 06:48:38Z imp $ */ 3 4/* 5 * Copyright (c) 2002 M Warner Losh. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * This software may be derived from NetBSD i82365.c and other files with 28 * the following copyright: 29 * 30 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. All advertising materials mentioning features or use of this software 41 * must display the following acknowledgement: 42 * This product includes software developed by Marc Horowitz. 43 * 4. The name of the author may not be used to endorse or promote products 44 * derived from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 51 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 55 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58/* 59 * All information is from the intel 82365sl PC Card Interface Controller 60 * (PCIC) data sheet, marked "preliminary". Order number 290423-002, January 61 * 1993. 62 */ 63 64#define EXCA_IOSIZE 2 65 66#define EXCA_REG_INDEX 0 67#define EXCA_REG_DATA 1 68 69#define EXCA_NSLOTS 4 /* 2 in 2 chips */ 70 71/* 72 * I/o ports 73 */ 74#define EXCA_INDEX0 0x3e0 75 76/* 77 * The PCIC allows two chips to share the same address. In order not to run 78 * afoul of the bsd device model, this driver will treat those chips as 79 * the same device. 80 */ 81 82#define EXCA_CHIP0_BASE 0x00 83#define EXCA_CHIP1_BASE 0x80 84 85/* Each PCIC chip can drive two sockets */ 86 87#define EXCA_SOCKET_SIZE 0x40 88#define EXCA_SOCKETA_INDEX 0x00 89#define EXCA_SOCKETB_INDEX EXCA_SOCKET_SIZE 90 91/* general setup registers */ 92 93#define EXCA_IDENT 0x00 /* RO */ 94#define EXCA_IDENT_IFTYPE_MASK 0xC0 95#define EXCA_IDENT_IFTYPE_IO_ONLY 0x00 96#define EXCA_IDENT_IFTYPE_MEM_ONLY 0x40 97#define EXCA_IDENT_IFTYPE_MEM_AND_IO 0x80 98#define EXCA_IDENT_IFTYPE_RESERVED 0xC0 99#define EXCA_IDENT_ZERO 0x30 100#define EXCA_IDENT_REV_MASK 0x0F 101#define EXCA_IDENT_REV_I82365SLR0 0x02 102#define EXCA_IDENT_REV_I82365SLR1 0x03 103 104#define EXCA_IF_STATUS 0x01 /* RO */ 105#define EXCA_IF_STATUS_GPI 0x80 /* General Purpose Input */ 106#define EXCA_IF_STATUS_POWERACTIVE 0x40 107#define EXCA_IF_STATUS_READY 0x20 /* really READY/!BUSY */ 108#define EXCA_IF_STATUS_MEM_WP 0x10 109#define EXCA_IF_STATUS_CARDDETECT_MASK 0x0C 110#define EXCA_IF_STATUS_CARDDETECT_PRESENT 0x0C 111#define EXCA_IF_STATUS_BATTERY_MASK 0x03 112#define EXCA_IF_STATUS_BATTERY_DEAD1 0x00 113#define EXCA_IF_STATUS_BATTERY_DEAD2 0x01 114#define EXCA_IF_STATUS_BATTERY_WARNING 0x02 115#define EXCA_IF_STATUS_BATTERY_GOOD 0x03 116 117#define EXCA_PWRCTL 0x02 /* RW */ 118#define EXCA_PWRCTL_OE 0x80 /* output enable */ 119#define EXCA_PWRCTL_DISABLE_RESETDRV 0x40 120#define EXCA_PWRCTL_AUTOSWITCH_ENABLE 0x20 121#define EXCA_PWRCTL_PWR_ENABLE 0x10 122#define EXCA_PWRCTL_VPP2_MASK 0x0C 123/* XXX these are a little unclear from the data sheet */ 124#define EXCA_PWRCTL_VPP2_RESERVED 0x0C 125#define EXCA_PWRCTL_VPP2_EN1 0x08 126#define EXCA_PWRCTL_VPP2_EN0 0x04 127#define EXCA_PWRCTL_VPP2_ENX 0x00 128#define EXCA_PWRCTL_VPP1_MASK 0x03 129/* XXX these are a little unclear from the data sheet */ 130#define EXCA_PWRCTL_VPP1_RESERVED 0x03 131#define EXCA_PWRCTL_VPP1_EN1 0x02 132#define EXCA_PWRCTL_VPP1_EN0 0x01 133#define EXCA_PWRCTL_VPP1_ENX 0x00 134 135#define EXCA_CSC 0x04 /* RW */ 136#define EXCA_CSC_ZERO 0xE0 137#define EXCA_CSC_GPI 0x10 138#define EXCA_CSC_CD 0x08 /* Card Detect Change */ 139#define EXCA_CSC_READY 0x04 140#define EXCA_CSC_BATTWARN 0x02 141#define EXCA_CSC_BATTDEAD 0x01 /* for memory cards */ 142#define EXCA_CSC_RI 0x01 /* for i/o cards */ 143 144#define EXCA_ADDRWIN_ENABLE 0x06 /* RW */ 145#define EXCA_ADDRWIN_ENABLE_IO1 0x80 146#define EXCA_ADDRWIN_ENABLE_IO0 0x40 147#define EXCA_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */ 148#define EXCA_ADDRWIN_ENABLE_MEM4 0x10 149#define EXCA_ADDRWIN_ENABLE_MEM3 0x08 150#define EXCA_ADDRWIN_ENABLE_MEM2 0x04 151#define EXCA_ADDRWIN_ENABLE_MEM1 0x02 152#define EXCA_ADDRWIN_ENABLE_MEM0 0x01 153 154#define EXCA_CARD_DETECT 0x16 /* RW */ 155#define EXCA_CARD_DETECT_RESERVED 0xC0 156#define EXCA_CARD_DETECT_SW_INTR 0x20 157#define EXCA_CARD_DETECT_RESUME_ENABLE 0x10 158#define EXCA_CARD_DETECT_GPI_TRANSCTL 0x08 159#define EXCA_CARD_DETECT_GPI_ENABLE 0x04 160#define EXCA_CARD_DETECT_CFGRST_ENABLE 0x02 161#define EXCA_CARD_DETECT_MEMDLY_INHIBIT 0x01 162 163/* interrupt registers */ 164 165#define EXCA_INTR 0x03 /* RW */ 166#define EXCA_INTR_RI_ENABLE 0x80 167#define EXCA_INTR_RESET 0x40 /* active low (zero) */ 168#define EXCA_INTR_CARDTYPE_MASK 0x20 169#define EXCA_INTR_CARDTYPE_IO 0x20 170#define EXCA_INTR_CARDTYPE_MEM 0x00 171#define EXCA_INTR_ENABLE 0x10 172#define EXCA_INTR_IRQ_MASK 0x0F 173#define EXCA_INTR_IRQ_SHIFT 0 174#define EXCA_INTR_IRQ_NONE 0x00 175#define EXCA_INTR_IRQ_RESERVED1 0x01 176#define EXCA_INTR_IRQ_RESERVED2 0x02 177#define EXCA_INTR_IRQ3 0x03 178#define EXCA_INTR_IRQ4 0x04 179#define EXCA_INTR_IRQ5 0x05 180#define EXCA_INTR_IRQ_RESERVED6 0x06 181#define EXCA_INTR_IRQ7 0x07 182#define EXCA_INTR_IRQ_RESERVED8 0x08 183#define EXCA_INTR_IRQ9 0x09 184#define EXCA_INTR_IRQ10 0x0A 185#define EXCA_INTR_IRQ11 0x0B 186#define EXCA_INTR_IRQ12 0x0C 187#define EXCA_INTR_IRQ_RESERVED13 0x0D 188#define EXCA_INTR_IRQ14 0x0E 189#define EXCA_INTR_IRQ15 0x0F 190 191#define EXCA_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ 192 193#define EXCA_CSC_INTR 0x05 /* RW */ 194#define EXCA_CSC_INTR_IRQ_MASK 0xF0 195#define EXCA_CSC_INTR_IRQ_SHIFT 4 196#define EXCA_CSC_INTR_IRQ_NONE 0x00 197#define EXCA_CSC_INTR_IRQ_RESERVED1 0x10 198#define EXCA_CSC_INTR_IRQ_RESERVED2 0x20 199#define EXCA_CSC_INTR_IRQ3 0x30 200#define EXCA_CSC_INTR_IRQ4 0x40 201#define EXCA_CSC_INTR_IRQ5 0x50 202#define EXCA_CSC_INTR_IRQ_RESERVED6 0x60 203#define EXCA_CSC_INTR_IRQ7 0x70 204#define EXCA_CSC_INTR_IRQ_RESERVED8 0x80 205#define EXCA_CSC_INTR_IRQ9 0x90 206#define EXCA_CSC_INTR_IRQ10 0xA0 207#define EXCA_CSC_INTR_IRQ11 0xB0 208#define EXCA_CSC_INTR_IRQ12 0xC0 209#define EXCA_CSC_INTR_IRQ_RESERVED13 0xD0 210#define EXCA_CSC_INTR_IRQ14 0xE0 211#define EXCA_CSC_INTR_IRQ15 0xF0 212#define EXCA_CSC_INTR_CD_ENABLE 0x08 213#define EXCA_CSC_INTR_READY_ENABLE 0x04 214#define EXCA_CSC_INTR_BATTWARN_ENABLE 0x02 215#define EXCA_CSC_INTR_BATTDEAD_ENABLE 0x01 /* for memory cards */ 216#define EXCA_CSC_INTR_RI_ENABLE 0x01 /* for I/O cards */ 217 218#define EXCA_CSC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ 219 220/* I/O registers */ 221 222#define EXCA_IO_WINS 2 223 224#define EXCA_IOCTL 0x07 /* RW */ 225#define EXCA_IOCTL_IO1_WAITSTATE 0x80 226#define EXCA_IOCTL_IO1_ZEROWAIT 0x40 227#define EXCA_IOCTL_IO1_IOCS16SRC_MASK 0x20 228#define EXCA_IOCTL_IO1_IOCS16SRC_CARD 0x20 229#define EXCA_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00 230#define EXCA_IOCTL_IO1_DATASIZE_MASK 0x10 231#define EXCA_IOCTL_IO1_DATASIZE_16BIT 0x10 232#define EXCA_IOCTL_IO1_DATASIZE_8BIT 0x00 233#define EXCA_IOCTL_IO0_WAITSTATE 0x08 234#define EXCA_IOCTL_IO0_ZEROWAIT 0x04 235#define EXCA_IOCTL_IO0_IOCS16SRC_MASK 0x02 236#define EXCA_IOCTL_IO0_IOCS16SRC_CARD 0x02 237#define EXCA_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00 238#define EXCA_IOCTL_IO0_DATASIZE_MASK 0x01 239#define EXCA_IOCTL_IO0_DATASIZE_16BIT 0x01 240#define EXCA_IOCTL_IO0_DATASIZE_8BIT 0x00 241 242#define EXCA_IOADDR0_START_LSB 0x08 243#define EXCA_IOADDR0_START_MSB 0x09 244#define EXCA_IOADDR0_STOP_LSB 0x0A 245#define EXCA_IOADDR0_STOP_MSB 0x0B 246#define EXCA_IOADDR1_START_LSB 0x0C 247#define EXCA_IOADDR1_START_MSB 0x0D 248#define EXCA_IOADDR1_STOP_LSB 0x0E 249#define EXCA_IOADDR1_STOP_MSB 0x0F 250 251/* memory registers */ 252 253/* 254 * memory window addresses refer to bits A23-A12 of the ISA system memory 255 * address. This is a shift of 12 bits. The LSB contains A19-A12, and the 256 * MSB contains A23-A20, plus some other bits. 257 */ 258 259#define EXCA_MEM_WINS 5 260 261#define EXCA_MEM_SHIFT 12 262#define EXCA_MEM_PAGESIZE (1<<EXCA_MEM_SHIFT) 263 264#define EXCA_SYSMEM_ADDRX_SHIFT EXCA_MEM_SHIFT 265#define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80 266#define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80 267#define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00 268#define EXCA_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40 269#define EXCA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30 270#define EXCA_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F 271 272#define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0 273#define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00 274#define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40 275#define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80 276#define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0 277#define EXCA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F 278 279/* 280 * The card side of a memory mapping consists of bits A19-A12 of the card 281 * memory address in the LSB, and A25-A20 plus some other bits in the MSB. 282 * Again, the shift is 12 bits. 283 */ 284 285#define EXCA_CARDMEM_ADDRX_SHIFT EXCA_MEM_SHIFT 286#define EXCA_CARDMEM_ADDRX_MSB_WP 0x80 287#define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40 288#define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40 289#define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00 290#define EXCA_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F 291 292#define EXCA_SYSMEM_ADDR0_START_LSB 0x10 293#define EXCA_SYSMEM_ADDR0_START_MSB 0x11 294#define EXCA_SYSMEM_ADDR0_STOP_LSB 0x12 295#define EXCA_SYSMEM_ADDR0_STOP_MSB 0x13 296 297#define EXCA_CARDMEM_ADDR0_LSB 0x14 298#define EXCA_CARDMEM_ADDR0_MSB 0x15 299 300/* #define EXCA_RESERVED 0x17 */ 301 302#define EXCA_SYSMEM_ADDR1_START_LSB 0x18 303#define EXCA_SYSMEM_ADDR1_START_MSB 0x19 304#define EXCA_SYSMEM_ADDR1_STOP_LSB 0x1A 305#define EXCA_SYSMEM_ADDR1_STOP_MSB 0x1B 306 307#define EXCA_CARDMEM_ADDR1_LSB 0x1C 308#define EXCA_CARDMEM_ADDR1_MSB 0x1D 309 310#define EXCA_SYSMEM_ADDR2_START_LSB 0x20 311#define EXCA_SYSMEM_ADDR2_START_MSB 0x21 312#define EXCA_SYSMEM_ADDR2_STOP_LSB 0x22 313#define EXCA_SYSMEM_ADDR2_STOP_MSB 0x23 314 315#define EXCA_CARDMEM_ADDR2_LSB 0x24 316#define EXCA_CARDMEM_ADDR2_MSB 0x25 317 318/* #define EXCA_RESERVED 0x26 */ 319/* #define EXCA_RESERVED 0x27 */ 320 321#define EXCA_SYSMEM_ADDR3_START_LSB 0x28 322#define EXCA_SYSMEM_ADDR3_START_MSB 0x29 323#define EXCA_SYSMEM_ADDR3_STOP_LSB 0x2A 324#define EXCA_SYSMEM_ADDR3_STOP_MSB 0x2B 325 326#define EXCA_CARDMEM_ADDR3_LSB 0x2C 327#define EXCA_CARDMEM_ADDR3_MSB 0x2D 328 329/* #define EXCA_RESERVED 0x2E */ 330/* #define EXCA_RESERVED 0x2F */ 331 332#define EXCA_SYSMEM_ADDR4_START_LSB 0x30 333#define EXCA_SYSMEM_ADDR4_START_MSB 0x31 334#define EXCA_SYSMEM_ADDR4_STOP_LSB 0x32 335#define EXCA_SYSMEM_ADDR4_STOP_MSB 0x33 336 337#define EXCA_CARDMEM_ADDR4_LSB 0x34 338#define EXCA_CARDMEM_ADDR4_MSB 0x35 339 340/* #define EXCA_RESERVED 0x36 */ 341/* #define EXCA_RESERVED 0x37 */ 342/* #define EXCA_RESERVED 0x38 */ 343/* #define EXCA_RESERVED 0x39 */ 344/* #define EXCA_RESERVED 0x3A */ 345/* #define EXCA_RESERVED 0x3B */ 346/* #define EXCA_RESERVED 0x3C */ 347/* #define EXCA_RESERVED 0x3D */ 348/* #define EXCA_RESERVED 0x3E */ 349/* #define EXCA_RESERVED 0x3F */ 350 351/* cardbus extensions - memory window page registers */ 352 353#define EXCA_MEMREG_WIN_SHIFT 24 354#define EXCA_SYSMEM_ADDR0_WIN 0x40 355#define EXCA_SYSMEM_ADDR1_WIN 0x41 356#define EXCA_SYSMEM_ADDR2_WIN 0x42 357#define EXCA_SYSMEM_ADDR3_WIN 0x43 358#define EXCA_SYSMEM_ADDR4_WIN 0x44 359 360/* vendor-specific registers */ 361 362#define EXCA_INTEL_GLOBAL_CTL 0x1E /* RW */ 363#define EXCA_INTEL_GLOBAL_CTL_RESERVED 0xF0 364#define EXCA_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08 365#define EXCA_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04 366#define EXCA_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02 367#define EXCA_INTEL_GLOBAL_CTL_POWERDOWN 0x01 368 369#define EXCA_CIRRUS_MISC_CTL_2 0x1E 370#define EXCA_CIRRUS_MISC_CTL_2_SUSPEND 0x04 371 372#define EXCA_CIRRUS_CHIP_INFO 0x1F 373#define EXCA_CIRRUS_CHIP_INFO_CHIP_ID 0xC0 374#define EXCA_CIRRUS_CHIP_INFO_SLOTS 0x20 375#define EXCA_CIRRUS_CHIP_INFO_REV 0x1F 376 377#define EXCA_CIRRUS_EXTENDED_INDEX 0x2E 378#define EXCA_CIRRUS_EXTENDED_DATA 0x2F 379#define EXCA_CIRRUS_EXT_CONTROL_1 0x03 380#define EXCA_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18 381 382/* Plug and play */ 383#define EXCA_PNP_ACTIONTEC 0x1802A904 /* AEI0218 */ 384#define EXCA_PNP_IBM3765 0x65374d24 /* IBM3765 */ 385#define EXCA_PNP_82365 0x000ED041 /* PNP0E00 */ 386#define EXCA_PNP_CL_PD6720 0x010ED041 /* PNP0E01 */ 387#define EXCA_PNP_VLSI_82C146 0x020ED041 /* PNP0E02 */ 388#define EXCA_PNP_82365_CARDBUS 0x030ED041 /* PNP0E03 */ 389#define EXCA_PNP_SCM_SWAPBOX 0x69046d4c /* SMC0469 */ 390 391/* C-Bus PnP Definitions */ 392#define EXCA_NEC_PC9801_102 0x9180a3b8 /* NEC8091 PC-9801-102 */ 393#define EXCA_NEC_PC9821RA_E01 0x2181a3b8 /* NEC8121 PC-9821RA-E01 */ 394 395/* 396 * Mask of allowable interrupts. 397 * 398 * For IBM-AT machines, irqs 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 are 399 * allowed. Nearly all IBM-AT machines with pcic cards or bridges 400 * wire these interrupts (or a subset thereof) to the corresponding 401 * pins on the ISA bus. Some older laptops are reported to not route 402 * all the interrupt pins to the bus because the designers knew that 403 * some would conflict with builtin devices. Older versions of Windows 404 * NT had a special device that would probe for conflicts early in the 405 * boot process and formulate a mapping table. Maybe we should do 406 * something similar. 407 * 408 * For NEC PC-98 machines, irq 3, 5, 6, 9, 10, 11, 12, 13 are allowed. 409 * These correspond to the C-BUS signals INT 0, 1, 2, 3, 41, 42, 5, 6 410 * respectively. 411 * 412 * Hiroshi TSUKADA-san writes in FreeBSD98-testers that CBUS INT 2 413 * (mapped to IRQ 6) is routed to the IRQ 7 pin of the pcic in pc98 414 * cbus add-in cards. He has confirmed this routing with a visual 415 * inspection of his card or a VOM. 416 */ 417#ifdef PC98 418#define EXCA_INT_MASK_ALLOWED 0x3E68 /* PC98 */ 419#else 420#define EXCA_INT_MASK_ALLOWED 0xDEB8 /* AT */ 421#endif 422