1227006Smarius/* $NetBSD: pcscpreg.h,v 1.2 2008/04/28 20:23:55 martin Exp $ */ 2227006Smarius 3227006Smarius/*- 4227006Smarius * Copyright (c) 1998 The NetBSD Foundation, Inc. 5227006Smarius * All rights reserved. 6227006Smarius * 7227006Smarius * This code is derived from software contributed to The NetBSD Foundation 8227006Smarius * by Izumi Tsutsui. 9227006Smarius * 10227006Smarius * Redistribution and use in source and binary forms, with or without 11227006Smarius * modification, are permitted provided that the following conditions 12227006Smarius * are met: 13227006Smarius * 1. Redistributions of source code must retain the above copyright 14227006Smarius * notice, this list of conditions and the following disclaimer. 15227006Smarius * 2. Redistributions in binary form must reproduce the above copyright 16227006Smarius * notice, this list of conditions and the following disclaimer in the 17227006Smarius * documentation and/or other materials provided with the distribution. 18227006Smarius * 19227006Smarius * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20227006Smarius * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21227006Smarius * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22227006Smarius * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23227006Smarius * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24227006Smarius * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25227006Smarius * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26227006Smarius * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27227006Smarius * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28227006Smarius * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29227006Smarius * POSSIBILITY OF SUCH DAMAGE. 30227006Smarius */ 31227006Smarius 32227006Smarius/* $FreeBSD: releng/11.0/sys/dev/esp/am53c974reg.h 227006 2011-11-01 21:26:57Z marius $ */ 33227006Smarius 34227006Smarius#ifndef _AM53C974_H_ 35227006Smarius#define _AM53C974_H_ 36227006Smarius 37227006Smarius/* 38227006Smarius * Am53c974 DMA engine registers 39227006Smarius */ 40227006Smarius 41227006Smarius#define DMA_CMD 0x40 /* Command */ 42227006Smarius#define DMACMD_RSVD 0xFFFFFF28 /* reserved */ 43227006Smarius#define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */ 44227006Smarius#define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */ 45227006Smarius#define DMACMD_MDL 0x00000010 /* Map to Memory Description List */ 46227006Smarius#define DMACMD_DIAG 0x00000004 /* Diagnostic */ 47227006Smarius#define DMACMD_CMD 0x00000003 /* Command Code Bit */ 48227006Smarius#define DMACMD_IDLE 0x00000000 /* Idle */ 49227006Smarius#define DMACMD_BLAST 0x00000001 /* Blast */ 50227006Smarius#define DMACMD_ABORT 0x00000002 /* Abort */ 51227006Smarius#define DMACMD_START 0x00000003 /* Start */ 52227006Smarius 53227006Smarius#define DMA_STC 0x44 /* Start Transfer Count */ 54227006Smarius#define DMA_SPA 0x48 /* Start Physical Address */ 55227006Smarius#define DMA_WBC 0x4C /* Working Byte Counter */ 56227006Smarius#define DMA_WAC 0x50 /* Working Address Counter */ 57227006Smarius 58227006Smarius#define DMA_STAT 0x54 /* Status Register */ 59227006Smarius#define DMASTAT_RSVD 0xFFFFFF80 /* reserved */ 60227006Smarius#define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */ 61227006Smarius#define DMASTAT_BCMP 0x00000020 /* BLAST Complete */ 62227006Smarius#define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */ 63227006Smarius#define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */ 64227006Smarius#define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */ 65227006Smarius#define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */ 66227006Smarius#define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */ 67227006Smarius 68227006Smarius#define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */ 69227006Smarius#define DMA_WMAC 0x5C /* Working MDL Counter */ 70227006Smarius#define DMA_SBAC 0x70 /* SCSI Bus and Control */ 71227006Smarius 72227006Smarius#endif /* _AM53C974_H_ */ 73