if_epreg.h revision 7510
1963Sats/* 24435Sgibbs * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 34435Sgibbs * 4963Sats * Redistribution and use in source and binary forms, with or without 54435Sgibbs * modification, are permitted provided that the following conditions are 64435Sgibbs * met: 1. Redistributions of source code must retain the above copyright 74435Sgibbs * notice, this list of conditions and the following disclaimer. 2. The name 84435Sgibbs * of the author may not be used to endorse or promote products derived from 94435Sgibbs * this software withough specific prior written permission 104435Sgibbs * 114435Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 124435Sgibbs * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 134435Sgibbs * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 144435Sgibbs * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 154435Sgibbs * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 164435Sgibbs * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 174435Sgibbs * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 184435Sgibbs * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 194435Sgibbs * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 204435Sgibbs * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 214435Sgibbs * 227510Sjkh * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by: 234435Sgibbs * 244435Sgibbs October 2, 1994 254435Sgibbs 264435Sgibbs Modified by: Andres Vega Garcia 274435Sgibbs 284435Sgibbs INRIA - Sophia Antipolis, France 294435Sgibbs e-mail: avega@sophia.inria.fr 304435Sgibbs finger: avega@pax.inria.fr 314435Sgibbs 32963Sats */ 337510Sjkh/* 347510Sjkh * March 28 1995 357510Sjkh * 367510Sjkh * Promiscuous mode added and interrupt logic slightly changed 377510Sjkh * to reduce the number of adapter failures. Transceiver select 387510Sjkh * logic changed to use value from EEPROM. Autoconfiguration 397510Sjkh * features added. 407510Sjkh * Done by: 417510Sjkh * Serge Babkin 427510Sjkh * Chelindbank (Chelyabinsk, Russia) 437510Sjkh * babkin@hq.icb.chel.su 447510Sjkh */ 454435Sgibbs 464435Sgibbs/* 474435Sgibbs * Ethernet software status per interface. 484435Sgibbs */ 494435Sgibbsstruct ep_softc { 504435Sgibbs struct arpcom arpcom; /* Ethernet common part */ 514435Sgibbs short ep_io_addr; /* i/o bus address */ 524435Sgibbs#define MAX_MBS 8 /* # of mbufs we keep around */ 534435Sgibbs struct mbuf *mb[MAX_MBS]; /* spare mbuf storage. */ 544435Sgibbs int next_mb; /* Which mbuf to use next. */ 554435Sgibbs int last_mb; /* Last mbuf. */ 564435Sgibbs struct mbuf *top, *mcur; 574435Sgibbs short tx_start_thresh; /* Current TX_start_thresh. */ 584435Sgibbs short tx_rate; 594435Sgibbs short tx_counter; 604435Sgibbs short rx_early_thresh; /* Current RX_early_thresh. */ 614435Sgibbs short rx_latency; 624435Sgibbs short rx_avg_pkt; 634435Sgibbs short cur_len; 644435Sgibbs caddr_t bpf; /* BPF "magic cookie" */ 654435Sgibbs u_short ep_connectors; /* Connectors on this card. */ 664435Sgibbs int stat; /* some flags */ 674435Sgibbs#define F_RX_FIRST 0x1 684435Sgibbs#define F_WAIT_TRAIL 0x2 694435Sgibbs#define F_RX_TRAILER 0x4 707267Sdg#define F_PROMISC 0x8 714435Sgibbs 724435Sgibbs#define F_ACCESS_32_BITS 0x100 734435Sgibbs 744435Sgibbs#ifdef EP_LOCAL_STATS 754435Sgibbs short tx_underrun; 764435Sgibbs short rx_no_first; 774435Sgibbs short rx_no_mbuf; 784435Sgibbs short rx_bpf_disc; 794435Sgibbs short rx_overrunf; 804435Sgibbs short rx_overrunl; 814435Sgibbs#endif 824435Sgibbs}; 834435Sgibbs 844435Sgibbs/* 854435Sgibbs * Some global constants 864435Sgibbs */ 874435Sgibbs#define ETHER_MIN_LEN 64 884435Sgibbs#define ETHER_MAX_LEN 1518 894435Sgibbs#define ETHER_ADDR_LEN 6 904435Sgibbs 914435Sgibbs#define TX_INIT_RATE 16 924435Sgibbs#define TX_INIT_MAX_RATE 64 934435Sgibbs#define RX_INIT_LATENCY 64 944435Sgibbs#define RX_INIT_EARLY_THRESH 64 954435Sgibbs#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 964435Sgibbs#define MIN_RX_EARLY_THRESHL 4 974435Sgibbs 984435Sgibbs#define EEPROMSIZE 0x40 994435Sgibbs#define MAX_EEPROMBUSY 1000 1004435Sgibbs#define EP_LAST_TAG 0xd7 1014435Sgibbs#define EP_MAX_BOARDS 16 1024435Sgibbs#define EP_ID_PORT 0x100 1034435Sgibbs 1044435Sgibbs/* 1054435Sgibbs * some macros to acces long named fields 1064435Sgibbs */ 1074435Sgibbs#define IS_BASE (is->id_iobase) 1084435Sgibbs#define BASE (sc->ep_io_addr) 1094435Sgibbs 1104435Sgibbs/* 1114435Sgibbs * Commands to read/write EEPROM trough EEPROM command register (Window 0, 1124435Sgibbs * Offset 0xa) 1134435Sgibbs */ 1144435Sgibbs#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 1154435Sgibbs#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 1164435Sgibbs#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 1174435Sgibbs#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 1184435Sgibbs 1194435Sgibbs#define EEPROM_BUSY (1<<15) 1204435Sgibbs#define EEPROM_TST_MODE (1<<14) 1214435Sgibbs 1224435Sgibbs/* 1234435Sgibbs * Some short functions, worth to let them be a macro 1244435Sgibbs */ 1254435Sgibbs#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 1264435Sgibbs#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x)) 1274435Sgibbs 128963Sats/************************************************************************** 1294435Sgibbs * * 130963Sats * These define the EEPROM data structure. They are used in the probe 131963Sats * function to verify the existance of the adapter after having sent 132963Sats * the ID_Sequence. 133963Sats * 134963Sats * There are others but only the ones we use are defined here. 135963Sats * 136963Sats **************************************************************************/ 137963Sats 138963Sats#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 139963Sats#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 140963Sats#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 141963Sats#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 142963Sats#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 143963Sats#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 1444435Sgibbs#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 145963Sats 146963Sats/************************************************************************** 147963Sats * * 148963Sats * These are the registers for the 3Com 3c509 and their bit patterns when * 149963Sats * applicable. They have been taken out the the "EtherLink III Parallel * 150963Sats * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 151963Sats * from 3com. * 152963Sats * * 153963Sats **************************************************************************/ 154963Sats 1554435Sgibbs#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 1564435Sgibbs * command reg. */ 1574435Sgibbs#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 1584435Sgibbs * reg. */ 1594435Sgibbs#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 1604435Sgibbs * reg. */ 161963Sats/* 162963Sats * Window 0 registers. Setup. 163963Sats */ 1644435Sgibbs/* Write */ 165963Sats#define EP_W0_EEPROM_DATA 0x0c 166963Sats#define EP_W0_EEPROM_COMMAND 0x0a 167963Sats#define EP_W0_RESOURCE_CFG 0x08 168963Sats#define EP_W0_ADDRESS_CFG 0x06 169963Sats#define EP_W0_CONFIG_CTRL 0x04 1704435Sgibbs/* Read */ 171963Sats#define EP_W0_PRODUCT_ID 0x02 172963Sats#define EP_W0_MFG_ID 0x00 173963Sats 174963Sats/* 175963Sats * Window 1 registers. Operating Set. 176963Sats */ 1774435Sgibbs/* Write */ 178963Sats#define EP_W1_TX_PIO_WR_2 0x02 179963Sats#define EP_W1_TX_PIO_WR_1 0x00 1804435Sgibbs/* Read */ 181963Sats#define EP_W1_FREE_TX 0x0c 1824435Sgibbs#define EP_W1_TX_STATUS 0x0b /* byte */ 1834435Sgibbs#define EP_W1_TIMER 0x0a /* byte */ 184963Sats#define EP_W1_RX_STATUS 0x08 185963Sats#define EP_W1_RX_PIO_RD_2 0x02 186963Sats#define EP_W1_RX_PIO_RD_1 0x00 187963Sats 188963Sats/* 189963Sats * Window 2 registers. Station Address Setup/Read 190963Sats */ 1914435Sgibbs/* Read/Write */ 192963Sats#define EP_W2_ADDR_5 0x05 193963Sats#define EP_W2_ADDR_4 0x04 194963Sats#define EP_W2_ADDR_3 0x03 195963Sats#define EP_W2_ADDR_2 0x02 196963Sats#define EP_W2_ADDR_1 0x01 197963Sats#define EP_W2_ADDR_0 0x00 198963Sats 1994435Sgibbs/* 200963Sats * Window 3 registers. FIFO Management. 201963Sats */ 2024435Sgibbs/* Read */ 203963Sats#define EP_W3_FREE_TX 0x0c 204963Sats#define EP_W3_FREE_RX 0x0a 205963Sats 206963Sats/* 207963Sats * Window 4 registers. Diagnostics. 208963Sats */ 2094435Sgibbs/* Read/Write */ 210963Sats#define EP_W4_MEDIA_TYPE 0x0a 211963Sats#define EP_W4_CTRLR_STATUS 0x08 212963Sats#define EP_W4_NET_DIAG 0x06 213963Sats#define EP_W4_FIFO_DIAG 0x04 214963Sats#define EP_W4_HOST_DIAG 0x02 215963Sats#define EP_W4_TX_DIAG 0x00 216963Sats 217963Sats/* 218963Sats * Window 5 Registers. Results and Internal status. 219963Sats */ 2204435Sgibbs/* Read */ 221963Sats#define EP_W5_READ_0_MASK 0x0c 222963Sats#define EP_W5_INTR_MASK 0x0a 223963Sats#define EP_W5_RX_FILTER 0x08 224963Sats#define EP_W5_RX_EARLY_THRESH 0x06 225963Sats#define EP_W5_TX_AVAIL_THRESH 0x02 226963Sats#define EP_W5_TX_START_THRESH 0x00 227963Sats 228963Sats/* 229963Sats * Window 6 registers. Statistics. 230963Sats */ 2314435Sgibbs/* Read/Write */ 232963Sats#define TX_TOTAL_OK 0x0c 233963Sats#define RX_TOTAL_OK 0x0a 234963Sats#define TX_DEFERRALS 0x08 235963Sats#define RX_FRAMES_OK 0x07 236963Sats#define TX_FRAMES_OK 0x06 237963Sats#define RX_OVERRUNS 0x05 238963Sats#define TX_COLLISIONS 0x04 239963Sats#define TX_AFTER_1_COLLISION 0x03 240963Sats#define TX_AFTER_X_COLLISIONS 0x02 241963Sats#define TX_NO_SQE 0x01 242963Sats#define TX_CD_LOST 0x00 243963Sats 244963Sats/**************************************** 245963Sats * 246963Sats * Register definitions. 247963Sats * 248963Sats ****************************************/ 249963Sats 250963Sats/* 251963Sats * Command register. All windows. 252963Sats * 253963Sats * 16 bit register. 254963Sats * 15-11: 5-bit code for command to be executed. 255963Sats * 10-0: 11-bit arg if any. For commands with no args; 256963Sats * this can be set to anything. 257963Sats */ 2584435Sgibbs#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 2594435Sgibbs * after issuing */ 260963Sats#define WINDOW_SELECT (u_short) (0x1<<11) 2614435Sgibbs#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 2624435Sgibbs * determine whether 2634435Sgibbs * this is needed. If 2644435Sgibbs * so; wait 800 uSec 2654435Sgibbs * before using trans- 2664435Sgibbs * ceiver. */ 2674435Sgibbs#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 2684435Sgibbs * power-up */ 269963Sats#define RX_ENABLE (u_short) (0x4<<11) 270963Sats#define RX_RESET (u_short) (0x5<<11) 271963Sats#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 272963Sats#define TX_ENABLE (u_short) (0x9<<11) 273963Sats#define TX_DISABLE (u_short) (0xa<<11) 274963Sats#define TX_RESET (u_short) (0xb<<11) 275963Sats#define REQ_INTR (u_short) (0xc<<11) 276963Sats#define SET_INTR_MASK (u_short) (0xe<<11) 277963Sats#define SET_RD_0_MASK (u_short) (0xf<<11) 278963Sats#define SET_RX_FILTER (u_short) (0x10<<11) 2794435Sgibbs#define FIL_INDIVIDUAL (u_short) (0x1) 2804435Sgibbs#define FIL_GROUP (u_short) (0x2) 2814435Sgibbs#define FIL_BRDCST (u_short) (0x4) 2824435Sgibbs#define FIL_ALL (u_short) (0x8) 283963Sats#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 284963Sats#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 285963Sats#define SET_TX_START_THRESH (u_short) (0x13<<11) 286963Sats#define STATS_ENABLE (u_short) (0x15<<11) 287963Sats#define STATS_DISABLE (u_short) (0x16<<11) 288963Sats#define STOP_TRANSCEIVER (u_short) (0x17<<11) 2894435Sgibbs/* 2904435Sgibbs * The following C_* acknowledge the various interrupts. Some of them don't 2914435Sgibbs * do anything. See the manual. 2924435Sgibbs */ 2934435Sgibbs#define ACK_INTR (u_short) (0x6800) 2944435Sgibbs#define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 2954435Sgibbs#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 2964435Sgibbs#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 2974435Sgibbs#define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 2984435Sgibbs#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 2994435Sgibbs#define C_RX_EARLY (u_short) (ACK_INTR|0x20) 3004435Sgibbs#define C_INT_RQD (u_short) (ACK_INTR|0x40) 3014435Sgibbs#define C_UPD_STATS (u_short) (ACK_INTR|0x80) 3027510Sjkh#define C_MASK (u_short) 0xFF /* mask of C_* */ 303963Sats 304963Sats/* 305963Sats * Status register. All windows. 306963Sats * 307963Sats * 15-13: Window number(0-7). 308963Sats * 12: Command_in_progress. 309963Sats * 11: reserved. 310963Sats * 10: reserved. 311963Sats * 9: reserved. 312963Sats * 8: reserved. 313963Sats * 7: Update Statistics. 314963Sats * 6: Interrupt Requested. 315963Sats * 5: RX Early. 316963Sats * 4: RX Complete. 317963Sats * 3: TX Available. 318963Sats * 2: TX Complete. 319963Sats * 1: Adapter Failure. 320963Sats * 0: Interrupt Latch. 321963Sats */ 322963Sats#define S_INTR_LATCH (u_short) (0x1) 323963Sats#define S_CARD_FAILURE (u_short) (0x2) 324963Sats#define S_TX_COMPLETE (u_short) (0x4) 325963Sats#define S_TX_AVAIL (u_short) (0x8) 326963Sats#define S_RX_COMPLETE (u_short) (0x10) 327963Sats#define S_RX_EARLY (u_short) (0x20) 328963Sats#define S_INT_RQD (u_short) (0x40) 329963Sats#define S_UPD_STATS (u_short) (0x80) 3307510Sjkh#define S_MASK (u_short) 0xFF /* mask of S_* */ 3314435Sgibbs#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 3324435Sgibbs S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 333963Sats#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 334963Sats 3357510Sjkh/* Address Config. Register. 3367510Sjkh * Window 0/Port 06 3377510Sjkh */ 3387510Sjkh 3397510Sjkh#define ACF_CONNECTOR_BITS 14 3407510Sjkh#define ACF_CONNECTOR_UTP 0 3417510Sjkh#define ACF_CONNECTOR_AUI 1 3427510Sjkh#define ACF_CONNECTOR_BNC 3 3437510Sjkh 3447510Sjkh/* Resource configuration register. 3457510Sjkh * Window 0/Port 08 3467510Sjkh * 3477510Sjkh */ 3487510Sjkh 3497510Sjkh#define SET_IRQ(i) (((i)<<12) | 0xF00) /* set IRQ i */ 3507510Sjkh 351963Sats/* 3524435Sgibbs * FIFO Registers. 3534435Sgibbs * RX Status. Window 1/Port 08 354963Sats * 355963Sats * 15: Incomplete or FIFO empty. 356963Sats * 14: 1: Error in RX Packet 0: Incomplete or no error. 357963Sats * 13-11: Type of error. 358963Sats * 1000 = Overrun. 359963Sats * 1011 = Run Packet Error. 360963Sats * 1100 = Alignment Error. 361963Sats * 1101 = CRC Error. 362963Sats * 1001 = Oversize Packet Error (>1514 bytes) 363963Sats * 0010 = Dribble Bits. 364963Sats * (all other error codes, no errors.) 365963Sats * 366963Sats * 10-0: RX Bytes (0-1514) 367963Sats */ 3684435Sgibbs#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 3694435Sgibbs#define ERR_RX (u_short) (0x1<<14) 3704435Sgibbs#define ERR_RX_OVERRUN (u_short) (0x8<<11) 3714435Sgibbs#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 3724435Sgibbs#define ERR_RX_ALIGN (u_short) (0xc<<11) 3734435Sgibbs#define ERR_RX_CRC (u_short) (0xd<<11) 3744435Sgibbs#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 3754435Sgibbs#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 376963Sats 377963Sats/* 3784435Sgibbs * FIFO Registers. 3794435Sgibbs * TX Status. Window 1/Port 0B 380963Sats * 381963Sats * Reports the transmit status of a completed transmission. Writing this 382963Sats * register pops the transmit completion stack. 383963Sats * 384963Sats * Window 1/Port 0x0b. 385963Sats * 386963Sats * 7: Complete 387963Sats * 6: Interrupt on successful transmission requested. 388963Sats * 5: Jabber Error (TP Only, TX Reset required. ) 389963Sats * 4: Underrun (TX Reset required. ) 390963Sats * 3: Maximum Collisions. 391963Sats * 2: TX Status Overflow. 392963Sats * 1-0: Undefined. 393963Sats * 394963Sats */ 395963Sats#define TXS_COMPLETE 0x80 3964435Sgibbs#define TXS_SUCCES_INTR_REQ 0x40 397963Sats#define TXS_JABBER 0x20 398963Sats#define TXS_UNDERRUN 0x10 399963Sats#define TXS_MAX_COLLISION 0x8 400963Sats#define TXS_STATUS_OVERFLOW 0x4 401963Sats 402963Sats/* 4034435Sgibbs * Configuration control register. 4044435Sgibbs * Window 0/Port 04 4054435Sgibbs */ 4064435Sgibbs/* Read */ 4074435Sgibbs#define IS_AUI (1<<13) 4084435Sgibbs#define IS_BNC (1<<12) 4094435Sgibbs#define IS_UTP (1<<9) 4104435Sgibbs/* Write */ 4114435Sgibbs#define ENABLE_DRQ_IRQ 0x0001 4124435Sgibbs#define W0_P4_CMD_RESET_ADAPTER 0x4 4134435Sgibbs#define W0_P4_CMD_ENABLE_ADAPTER 0x1 4144435Sgibbs/* 4154435Sgibbs * Media type and status. 4164435Sgibbs * Window 4/Port 0A 4174435Sgibbs */ 4184435Sgibbs#define ENABLE_UTP 0xc0 4194435Sgibbs#define DISABLE_UTP 0x0 4204435Sgibbs 4214435Sgibbs/* 422963Sats * Misc defines for various things. 423963Sats */ 4244435Sgibbs#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 4254435Sgibbs#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ 4264435Sgibbs#define PROD_ID 0x9150 4274435Sgibbs 428963Sats#define AUI 0x1 429963Sats#define BNC 0x2 430963Sats#define UTP 0x4 4314435Sgibbs 432963Sats#define ETHER_ADDR_LEN 6 433963Sats#define ETHER_MAX 1536 434963Sats#define RX_BYTES_MASK (u_short) (0x07ff) 4352478Sats 4364435Sgibbs /* EISA support */ 4374435Sgibbs#define EP_EISA_START 0x1000 4384435Sgibbs#define EP_EISA_W0 0x0c80 439