1139749Simp/*- 24435Sgibbs * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 38876Srgrimes * 4963Sats * Redistribution and use in source and binary forms, with or without 54435Sgibbs * modification, are permitted provided that the following conditions are 64435Sgibbs * met: 1. Redistributions of source code must retain the above copyright 74435Sgibbs * notice, this list of conditions and the following disclaimer. 2. The name 84435Sgibbs * of the author may not be used to endorse or promote products derived from 913765Smpp * this software without specific prior written permission 108876Srgrimes * 114435Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 124435Sgibbs * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 134435Sgibbs * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 144435Sgibbs * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 154435Sgibbs * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 164435Sgibbs * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 174435Sgibbs * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 184435Sgibbs * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 194435Sgibbs * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 204435Sgibbs * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 218876Srgrimes * 2250477Speter * $FreeBSD: releng/11.0/sys/dev/ep/if_epreg.h 218909 2011-02-21 09:01:34Z brucec $ 237510Sjkh */ 244435Sgibbs 254435Sgibbs/* 2651673Smdodd * DELAY_MULTIPLE: How much to boost "base" delays, except 2751673Smdodd * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 2816374Snate */ 2951673Smdodd#define DELAY_MULTIPLE 10 3051673Smdodd#define BIT_DELAY_MULTIPLE 10 3116374Snate 3216374Snate/* 334435Sgibbs * Some global constants 344435Sgibbs */ 354435Sgibbs#define TX_INIT_RATE 16 364435Sgibbs#define TX_INIT_MAX_RATE 64 374435Sgibbs#define RX_INIT_LATENCY 64 38117700Smarkm#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */ 3930398Sitojun#define RX_NEXT_EARLY_THRESH 500 404435Sgibbs 414435Sgibbs#define EEPROMSIZE 0x40 424435Sgibbs#define MAX_EEPROMBUSY 1000 434435Sgibbs#define EP_LAST_TAG 0xd7 444435Sgibbs#define EP_MAX_BOARDS 16 4514259Sgibbs#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */ 464435Sgibbs 474435Sgibbs/* 484435Sgibbs * Commands to read/write EEPROM trough EEPROM command register (Window 0, 494435Sgibbs * Offset 0xa) 504435Sgibbs */ 514435Sgibbs#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 524435Sgibbs#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 534435Sgibbs#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 544435Sgibbs#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 554435Sgibbs 564435Sgibbs#define EEPROM_BUSY (1<<15) 574435Sgibbs#define EEPROM_TST_MODE (1<<14) 584435Sgibbs 594435Sgibbs/* 604435Sgibbs * Some short functions, worth to let them be a macro 614435Sgibbs */ 62121492Simp#define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 63121588Simp#define GO_WINDOW(sc, x) CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT|(x)) 644435Sgibbs 65963Sats/************************************************************************** 664435Sgibbs * * 67963Sats * These define the EEPROM data structure. They are used in the probe 6813765Smpp * function to verify the existence of the adapter after having sent 69963Sats * the ID_Sequence. 70963Sats * 71963Sats **************************************************************************/ 72963Sats 73963Sats#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 74963Sats#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 75963Sats#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 76963Sats#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 77117700Smarkm#define EEPROM_MFG_DATE 0x4 /* Manufacturing date */ 78117700Smarkm#define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */ 79117700Smarkm#define EEPROM_MFG_PRODUCT 0x6 /* Product code */ 80963Sats#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 81963Sats#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 82117700Smarkm#define ADDR_CFG_EISA 0x1f 83117700Smarkm#define ADDR_CFG_MASK 0x1f 844435Sgibbs#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 8554201Smdodd#define EEPROM_OEM_ADDR0 0xa 8654201Smdodd#define EEPROM_OEM_ADDR1 0xb 8754201Smdodd#define EEPROM_OEM_ADDR2 0xc 8854201Smdodd#define EEPROM_SOFTINFO 0xd 8954201Smdodd#define EEPROM_COMPAT 0xe 9054201Smdodd#define EEPROM_SOFTINFO2 0xf 9154201Smdodd#define EEPROM_CAP 0x10 92117700Smarkm#define CAP_ISA 0x2083 93117700Smarkm#define CAP_PCMCIA 0x2082 9454201Smdodd#define EEPROM_INT_CONFIG_0 0x12 9554201Smdodd#define EEPROM_INT_CONFIG_1 0x13 9654201Smdodd/* RAM Partition TX FIFO/RX FIFO */ 97117700Smarkm#define ICW1_RAM_PART_MASK 0x03 98117700Smarkm#define ICW1_RAM_PART_35 0x00 /* 2:5 (only legal if RAM size == 000b 99117700Smarkm * default power-up/reset */ 100117700Smarkm#define ICW1_RAM_PART_13 0x01 /* 1:3 (only legal if RAM size == 101117700Smarkm * 000b) */ 102117700Smarkm#define ICW1_RAM_PART_11 0x10 /* 1:1 */ 103117700Smarkm#define ICW1_RAM_PART_RESV 0x11 /* Reserved */ 10454201Smdodd/* ISA Adapter Selection */ 105117700Smarkm#define ICW1_IAS_MASK 0x0c 106117700Smarkm#define ICW1_IAS_DIS 0x00 /* Both mechanisms disabled (default) */ 107117700Smarkm#define ICW1_IAS_ISA 0x04 /* ISA contention only */ 108117700Smarkm#define ICW1_IAS_PNP 0x08 /* ISA Plug and Play only */ 109117700Smarkm#define ICW1_IAS_BOTH 0x0c /* Both mechanisms enabled */ 110963Sats 11154201Smdodd#define EEPROM_CHECKSUM_EL3 0x17 11254201Smdodd 113963Sats/************************************************************************** 114148579Simp * * 115963Sats * These are the registers for the 3Com 3c509 and their bit patterns when * 116218909Sbrucec * applicable. They have been taken out the "EtherLink III Parallel * 117963Sats * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 118963Sats * from 3com. * 119148579Simp * * 120963Sats **************************************************************************/ 121963Sats 1224435Sgibbs#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a 1234435Sgibbs * command reg. */ 1244435Sgibbs#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status 1254435Sgibbs * reg. */ 1264435Sgibbs#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window 1274435Sgibbs * reg. */ 128963Sats/* 129963Sats * Window 0 registers. Setup. 130963Sats */ 1314435Sgibbs/* Write */ 132963Sats#define EP_W0_EEPROM_DATA 0x0c 133963Sats#define EP_W0_EEPROM_COMMAND 0x0a 134963Sats#define EP_W0_RESOURCE_CFG 0x08 135963Sats#define EP_W0_ADDRESS_CFG 0x06 136963Sats#define EP_W0_CONFIG_CTRL 0x04 137121492Simp /* Read */ 138963Sats#define EP_W0_PRODUCT_ID 0x02 139963Sats#define EP_W0_MFG_ID 0x00 140963Sats 141963Sats/* 142963Sats * Window 1 registers. Operating Set. 143963Sats */ 1444435Sgibbs/* Write */ 145963Sats#define EP_W1_TX_PIO_WR_2 0x02 146963Sats#define EP_W1_TX_PIO_WR_1 0x00 1474435Sgibbs/* Read */ 148963Sats#define EP_W1_FREE_TX 0x0c 1494435Sgibbs#define EP_W1_TX_STATUS 0x0b /* byte */ 1504435Sgibbs#define EP_W1_TIMER 0x0a /* byte */ 151963Sats#define EP_W1_RX_STATUS 0x08 152963Sats#define EP_W1_RX_PIO_RD_2 0x02 153963Sats#define EP_W1_RX_PIO_RD_1 0x00 154963Sats 155963Sats/* 156963Sats * Window 2 registers. Station Address Setup/Read 157963Sats */ 1584435Sgibbs/* Read/Write */ 159190907Simp#define EP_W2_PHY_MGMT 0x0c 160121902Simp#define EP_W2_ALT_EEPROM 0x0a 161963Sats#define EP_W2_ADDR_5 0x05 162963Sats#define EP_W2_ADDR_4 0x04 163963Sats#define EP_W2_ADDR_3 0x03 164963Sats#define EP_W2_ADDR_2 0x02 165963Sats#define EP_W2_ADDR_1 0x01 166963Sats#define EP_W2_ADDR_0 0x00 167963Sats 1684435Sgibbs/* 169963Sats * Window 3 registers. FIFO Management. 170963Sats */ 1714435Sgibbs/* Read */ 172963Sats#define EP_W3_FREE_TX 0x0c 173963Sats#define EP_W3_FREE_RX 0x0a 17449070Shosokawa#define EP_W3_OPTIONS 0x08 175963Sats 176963Sats/* 177963Sats * Window 4 registers. Diagnostics. 178963Sats */ 1794435Sgibbs/* Read/Write */ 180963Sats#define EP_W4_MEDIA_TYPE 0x0a 181963Sats#define EP_W4_CTRLR_STATUS 0x08 182963Sats#define EP_W4_NET_DIAG 0x06 183963Sats#define EP_W4_FIFO_DIAG 0x04 184963Sats#define EP_W4_HOST_DIAG 0x02 185963Sats#define EP_W4_TX_DIAG 0x00 186963Sats 187963Sats/* 188963Sats * Window 5 Registers. Results and Internal status. 189963Sats */ 1904435Sgibbs/* Read */ 191963Sats#define EP_W5_READ_0_MASK 0x0c 192963Sats#define EP_W5_INTR_MASK 0x0a 193963Sats#define EP_W5_RX_FILTER 0x08 194963Sats#define EP_W5_RX_EARLY_THRESH 0x06 195963Sats#define EP_W5_TX_AVAIL_THRESH 0x02 196963Sats#define EP_W5_TX_START_THRESH 0x00 197963Sats 198963Sats/* 199963Sats * Window 6 registers. Statistics. 200963Sats */ 2014435Sgibbs/* Read/Write */ 202963Sats#define TX_TOTAL_OK 0x0c 203963Sats#define RX_TOTAL_OK 0x0a 204963Sats#define TX_DEFERRALS 0x08 205963Sats#define RX_FRAMES_OK 0x07 206963Sats#define TX_FRAMES_OK 0x06 207963Sats#define RX_OVERRUNS 0x05 208963Sats#define TX_COLLISIONS 0x04 209963Sats#define TX_AFTER_1_COLLISION 0x03 210963Sats#define TX_AFTER_X_COLLISIONS 0x02 211963Sats#define TX_NO_SQE 0x01 212963Sats#define TX_CD_LOST 0x00 213963Sats 214963Sats/**************************************** 215963Sats * 216963Sats * Register definitions. 217963Sats * 218963Sats ****************************************/ 219963Sats 220117700Smarkm/* 22155834Smdodd * Command parameter that disables threshold interrupts 22255834Smdodd * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work. 22355834Smdodd * "busmastering" cards need 8188. 22455834Smdodd * The implicit two-bit upshift done by busmastering cards means 22555834Smdodd * a value of 2047 disables threshold interrupts on both. 226117700Smarkm */ 22755834Smdodd#define EP_THRESH_DISABLE 2047 22855834Smdodd 229963Sats/* 230963Sats * Command register. All windows. 231963Sats * 232963Sats * 16 bit register. 233963Sats * 15-11: 5-bit code for command to be executed. 234963Sats * 10-0: 11-bit arg if any. For commands with no args; 235963Sats * this can be set to anything. 236963Sats */ 2374435Sgibbs#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms 2384435Sgibbs * after issuing */ 239963Sats#define WINDOW_SELECT (u_short) (0x1<<11) 2404435Sgibbs#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to 2414435Sgibbs * determine whether 2424435Sgibbs * this is needed. If 2434435Sgibbs * so; wait 800 uSec 2444435Sgibbs * before using trans- 2454435Sgibbs * ceiver. */ 2464435Sgibbs#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on 2474435Sgibbs * power-up */ 248963Sats#define RX_ENABLE (u_short) (0x4<<11) 249963Sats#define RX_RESET (u_short) (0x5<<11) 250963Sats#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 251963Sats#define TX_ENABLE (u_short) (0x9<<11) 252963Sats#define TX_DISABLE (u_short) (0xa<<11) 253963Sats#define TX_RESET (u_short) (0xb<<11) 254963Sats#define REQ_INTR (u_short) (0xc<<11) 255121492Simp/* 256121492Simp * The following C_* acknowledge the various interrupts. Some of them don't 257121492Simp * do anything. See the manual. 258121492Simp */ 259121492Simp#define ACK_INTR (u_short) (0x6800) 260121492Simp# define C_INTR_LATCH (u_short) (ACK_INTR|0x1) 261121492Simp# define C_CARD_FAILURE (u_short) (ACK_INTR|0x2) 262121492Simp# define C_TX_COMPLETE (u_short) (ACK_INTR|0x4) 263121492Simp# define C_TX_AVAIL (u_short) (ACK_INTR|0x8) 264121492Simp# define C_RX_COMPLETE (u_short) (ACK_INTR|0x10) 265121492Simp# define C_RX_EARLY (u_short) (ACK_INTR|0x20) 266121492Simp# define C_INT_RQD (u_short) (ACK_INTR|0x40) 267121492Simp# define C_UPD_STATS (u_short) (ACK_INTR|0x80) 268963Sats#define SET_INTR_MASK (u_short) (0xe<<11) 269963Sats#define SET_RD_0_MASK (u_short) (0xf<<11) 270963Sats#define SET_RX_FILTER (u_short) (0x10<<11) 271121492Simp# define FIL_INDIVIDUAL (u_short) (0x1) 272121492Simp# define FIL_MULTICAST (u_short) (0x02) 273121492Simp# define FIL_BRDCST (u_short) (0x04) 274121492Simp# define FIL_PROMISC (u_short) (0x08) 275963Sats#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 276963Sats#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 277963Sats#define SET_TX_START_THRESH (u_short) (0x13<<11) 278963Sats#define STATS_ENABLE (u_short) (0x15<<11) 279963Sats#define STATS_DISABLE (u_short) (0x16<<11) 280963Sats#define STOP_TRANSCEIVER (u_short) (0x17<<11) 281148579Simp#define TX_PLL_ENABLE (u_short) (0x18<<11) 282148579Simp#define TX_PLL_DISABLE (u_short) (0x19<<11) 283148579Simp#define POWER_UP (u_short) (0x1b<<11) 284148579Simp#define POWER_DOWN (u_short) (0x1b<<11) 285148579Simp#define POWER_AUTO (u_short) (0x1b<<11) 286963Sats 287963Sats/* 288963Sats * Status register. All windows. 289963Sats * 290963Sats * 15-13: Window number(0-7). 291963Sats * 12: Command_in_progress. 292963Sats * 11: reserved. 293963Sats * 10: reserved. 294963Sats * 9: reserved. 295963Sats * 8: reserved. 296963Sats * 7: Update Statistics. 297963Sats * 6: Interrupt Requested. 298963Sats * 5: RX Early. 299963Sats * 4: RX Complete. 300963Sats * 3: TX Available. 301963Sats * 2: TX Complete. 302963Sats * 1: Adapter Failure. 303963Sats * 0: Interrupt Latch. 304963Sats */ 305963Sats#define S_INTR_LATCH (u_short) (0x1) 306963Sats#define S_CARD_FAILURE (u_short) (0x2) 307963Sats#define S_TX_COMPLETE (u_short) (0x4) 308963Sats#define S_TX_AVAIL (u_short) (0x8) 309963Sats#define S_RX_COMPLETE (u_short) (0x10) 310963Sats#define S_RX_EARLY (u_short) (0x20) 311963Sats#define S_INT_RQD (u_short) (0x40) 312963Sats#define S_UPD_STATS (u_short) (0x80) 313117700Smarkm#define S_MASK (u_short) 0xFF /* mask of S_* */ 3144435Sgibbs#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ 3154435Sgibbs S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 316963Sats#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 317963Sats 318196970Sphk#define EP_BUSY_WAIT(sc) while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS) 319121492Simp 3207510Sjkh/* Address Config. Register. 3217510Sjkh * Window 0/Port 06 3227510Sjkh */ 3237510Sjkh 3247510Sjkh#define ACF_CONNECTOR_BITS 14 3257510Sjkh#define ACF_CONNECTOR_UTP 0 3267510Sjkh#define ACF_CONNECTOR_AUI 1 3277510Sjkh#define ACF_CONNECTOR_BNC 3 3287510Sjkh 3297510Sjkh/* Resource configuration register. 3307510Sjkh * Window 0/Port 08 3317510Sjkh * 3327510Sjkh */ 3337510Sjkh 334121492Simp#define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \ 335121492Simp ((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) | \ 336121492Simp ((u_short)(irq)<<12)) ) /* set IRQ i */ 3377510Sjkh 338963Sats/* 3398876Srgrimes * FIFO Registers. 3404435Sgibbs * RX Status. Window 1/Port 08 341963Sats * 342963Sats * 15: Incomplete or FIFO empty. 343963Sats * 14: 1: Error in RX Packet 0: Incomplete or no error. 344963Sats * 13-11: Type of error. 345963Sats * 1000 = Overrun. 346963Sats * 1011 = Run Packet Error. 347963Sats * 1100 = Alignment Error. 348963Sats * 1101 = CRC Error. 349963Sats * 1001 = Oversize Packet Error (>1514 bytes) 350963Sats * 0010 = Dribble Bits. 351963Sats * (all other error codes, no errors.) 352963Sats * 353963Sats * 10-0: RX Bytes (0-1514) 354963Sats */ 3554435Sgibbs#define ERR_RX_INCOMPLETE (u_short) (0x1<<15) 3564435Sgibbs#define ERR_RX (u_short) (0x1<<14) 3574435Sgibbs#define ERR_RX_OVERRUN (u_short) (0x8<<11) 3584435Sgibbs#define ERR_RX_RUN_PKT (u_short) (0xb<<11) 3594435Sgibbs#define ERR_RX_ALIGN (u_short) (0xc<<11) 3604435Sgibbs#define ERR_RX_CRC (u_short) (0xd<<11) 3614435Sgibbs#define ERR_RX_OVERSIZE (u_short) (0x9<<11) 3624435Sgibbs#define ERR_RX_DRIBBLE (u_short) (0x2<<11) 363963Sats 364963Sats/* 3658876Srgrimes * FIFO Registers. 3664435Sgibbs * TX Status. Window 1/Port 0B 367963Sats * 368963Sats * Reports the transmit status of a completed transmission. Writing this 369963Sats * register pops the transmit completion stack. 370963Sats * 371963Sats * Window 1/Port 0x0b. 372963Sats * 373963Sats * 7: Complete 374963Sats * 6: Interrupt on successful transmission requested. 375963Sats * 5: Jabber Error (TP Only, TX Reset required. ) 376963Sats * 4: Underrun (TX Reset required. ) 377963Sats * 3: Maximum Collisions. 378963Sats * 2: TX Status Overflow. 379963Sats * 1-0: Undefined. 380963Sats * 381963Sats */ 382963Sats#define TXS_COMPLETE 0x80 3834435Sgibbs#define TXS_SUCCES_INTR_REQ 0x40 384963Sats#define TXS_JABBER 0x20 385963Sats#define TXS_UNDERRUN 0x10 386963Sats#define TXS_MAX_COLLISION 0x8 387963Sats#define TXS_STATUS_OVERFLOW 0x4 388963Sats 389963Sats/* 3908876Srgrimes * Configuration control register. 3914435Sgibbs * Window 0/Port 04 3924435Sgibbs */ 3934435Sgibbs/* Read */ 3944435Sgibbs#define IS_AUI (1<<13) 3954435Sgibbs#define IS_BNC (1<<12) 3964435Sgibbs#define IS_UTP (1<<9) 3974435Sgibbs/* Write */ 3984435Sgibbs#define ENABLE_DRQ_IRQ 0x0001 3994435Sgibbs#define W0_P4_CMD_RESET_ADAPTER 0x4 4004435Sgibbs#define W0_P4_CMD_ENABLE_ADAPTER 0x1 401121492Simp 4028876Srgrimes/* 4034435Sgibbs * Media type and status. 4044435Sgibbs * Window 4/Port 0A 4054435Sgibbs */ 406121492Simp#define JABBER_GUARD_ENABLE 0x40 407121492Simp#define LINKBEAT_ENABLE 0x80 408121492Simp#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 409121492Simp#define DISABLE_UTP 0x0 410190907Simp#define MT_CSD 0x0004 /* CRC Strip disable */ 411190907Simp#define MT_SQE 0x0008 /* SQE Enable */ 412190907Simp#define MT_C0 0x0010 /* Collison */ 413190907Simp#define MT_CS 0x0020 /* Carrier Sense */ 414190907Simp#define MT_J 0x0200 /* Jabber detected */ 415190907Simp#define MT_PL 0x0400 /* Plarity Inverted */ 416190907Simp#define MT_LB 0x0800 /* Link Beat detected */ 417190907Simp#define MT_SQ 0x1000 /* SQE Present */ 418190907Simp#define MT_IN 0x2000 /* Reserved */ 419190907Simp#define MT_CE 0x4000 /* Coax */ 420190907Simp#define MT_TPE 0x8000 4214435Sgibbs 4224435Sgibbs/* 423963Sats * Misc defines for various things. 424963Sats */ 425117700Smarkm#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */ 426117700Smarkm#define MFG_ID 0x6d50 /* in EEPROM and W0 427117700Smarkm * ADDR_CONFIG */ 4284435Sgibbs#define PROD_ID 0x9150 4294435Sgibbs 430963Sats#define AUI 0x1 431963Sats#define BNC 0x2 432963Sats#define UTP 0x4 4334435Sgibbs 434963Sats#define RX_BYTES_MASK (u_short) (0x07ff) 435