if_edvar.h revision 190794
1/*- 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/ed/if_edvar.h 190794 2009-04-07 05:41:38Z imp $ 28 */ 29 30#ifndef SYS_DEV_ED_IF_EDVAR_H 31#define SYS_DEV_ED_IF_EDVAR_H 32/* 33 * ed_softc: per line info and status 34 */ 35struct ed_softc { 36 struct ifnet *ifp; 37 struct ifmedia ifmedia; /* Media info */ 38 device_t dev; 39 struct mtx sc_mtx; 40 41 char *type_str; /* pointer to type string */ 42 u_char vendor; /* interface vendor */ 43 u_char type; /* interface type code */ 44 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */ 45 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 46 u_char mem_shared; /* NIC memory is shared with host */ 47 u_char xmit_busy; /* transmitter is busy */ 48 u_char enaddr[6]; 49 50 int port_rid; /* resource id for port range */ 51 int port_used; /* nonzero if ports used */ 52 struct resource* port_res; /* resource for port range */ 53 bus_space_tag_t port_bst; 54 bus_space_handle_t port_bsh; 55 int mem_rid; /* resource id for memory range */ 56 int mem_used; /* nonzero if memory used */ 57 struct resource* mem_res; /* resource for memory range */ 58 bus_space_tag_t mem_bst; 59 bus_space_handle_t mem_bsh; 60 int irq_rid; /* resource id for irq */ 61 struct resource* irq_res; /* resource for irq */ 62 void* irq_handle; /* handle for irq handler */ 63 int modem_rid; /* resource ID for modem part of device */ 64 int (*sc_media_ioctl)(struct ed_softc *sc, struct ifreq *ifr, 65 u_long command); 66 void (*sc_mediachg)(struct ed_softc *); 67 device_t miibus; /* MII bus for cards with MII. */ 68 void (*mii_writebits)(struct ed_softc *, u_int, int); 69 u_int (*mii_readbits)(struct ed_softc *, int); 70 struct callout tick_ch; 71 void (*sc_tick)(void *); 72 void (*readmem)(struct ed_softc *sc, bus_size_t src, uint8_t *dst, 73 uint16_t amount); 74 u_short (*sc_write_mbufs)(struct ed_softc *, struct mbuf *, bus_size_t); 75 76 int nic_offset; /* NIC (DS8390) I/O bus address offset */ 77 int asic_offset; /* ASIC I/O bus address offset */ 78 79/* 80 * The following 'proto' variable is part of a work-around for 8013EBT asics 81 * being write-only. It's sort of a prototype/shadow of the real thing. 82 */ 83 u_char wd_laar_proto; 84 u_char cr_proto; 85 86/* 87 * HP PC LAN PLUS card support. 88 */ 89 90 u_short hpp_options; /* flags controlling behaviour of the HP card */ 91 u_short hpp_id; /* software revision and other fields */ 92 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 93 94 bus_size_t mem_start; /* NIC memory start address */ 95 bus_size_t mem_end; /* NIC memory end address */ 96 uint32_t mem_size; /* total NIC memory size */ 97 bus_size_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 98 99 u_char txb_cnt; /* number of transmit buffers */ 100 u_char txb_inuse; /* number of TX buffers currently in-use */ 101 102 u_char txb_new; /* pointer to where new buffer will be added */ 103 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 104 u_short txb_len[8]; /* buffered xmit buffer lengths */ 105 u_char tx_page_start; /* first page of TX buffer area */ 106 u_char rec_page_start; /* first page of RX ring-buffer */ 107 u_char rec_page_stop; /* last page of RX ring-buffer */ 108 u_char next_packet; /* pointer to next unread RX packet */ 109 u_int tx_mem; /* Total amount of RAM for tx */ 110 u_int rx_mem; /* Total amount of RAM for rx */ 111 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 112}; 113 114#define ed_nic_inb(sc, port) \ 115 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 116 117#define ed_nic_outb(sc, port, value) \ 118 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 119 (sc)->nic_offset + (port), (value)) 120 121#define ed_nic_inw(sc, port) \ 122 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port)) 123 124#define ed_nic_outw(sc, port, value) \ 125 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 126 (sc)->nic_offset + (port), (value)) 127 128#define ed_nic_insb(sc, port, addr, count) \ 129 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 130 (sc)->nic_offset + (port), (addr), (count)) 131 132#define ed_nic_outsb(sc, port, addr, count) \ 133 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 134 (sc)->nic_offset + (port), (addr), (count)) 135 136#define ed_nic_insw(sc, port, addr, count) \ 137 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 138 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 139 140#define ed_nic_outsw(sc, port, addr, count) \ 141 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 142 (sc)->nic_offset + (port), (uint16_t *)(addr), (count)) 143 144#define ed_nic_insl(sc, port, addr, count) \ 145 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 146 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 147 148#define ed_nic_outsl(sc, port, addr, count) \ 149 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 150 (sc)->nic_offset + (port), (uint32_t *)(addr), (count)) 151 152#define ed_asic_inb(sc, port) \ 153 bus_space_read_1(sc->port_bst, sc->port_bsh, \ 154 (sc)->asic_offset + (port)) 155 156#define ed_asic_outb(sc, port, value) \ 157 bus_space_write_1(sc->port_bst, sc->port_bsh, \ 158 (sc)->asic_offset + (port), (value)) 159 160#define ed_asic_inw(sc, port) \ 161 bus_space_read_2(sc->port_bst, sc->port_bsh, \ 162 (sc)->asic_offset + (port)) 163 164#define ed_asic_outw(sc, port, value) \ 165 bus_space_write_2(sc->port_bst, sc->port_bsh, \ 166 (sc)->asic_offset + (port), (value)) 167 168#define ed_asic_insb(sc, port, addr, count) \ 169 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \ 170 (sc)->asic_offset + (port), (addr), (count)) 171 172#define ed_asic_outsb(sc, port, addr, count) \ 173 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \ 174 (sc)->asic_offset + (port), (addr), (count)) 175 176#define ed_asic_insw(sc, port, addr, count) \ 177 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \ 178 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 179 180#define ed_asic_outsw(sc, port, addr, count) \ 181 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \ 182 (sc)->asic_offset + (port), (uint16_t *)(addr), (count)) 183 184#define ed_asic_insl(sc, port, addr, count) \ 185 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \ 186 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 187 188#define ed_asic_outsl(sc, port, addr, count) \ 189 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \ 190 (sc)->asic_offset + (port), (uint32_t *)(addr), (count)) 191 192void ed_release_resources(device_t); 193int ed_alloc_port(device_t, int, int); 194int ed_alloc_memory(device_t, int, int); 195int ed_alloc_irq(device_t, int, int); 196 197int ed_probe_generic8390(struct ed_softc *); 198int ed_probe_WD80x3(device_t, int, int); 199int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]); 200int ed_probe_RTL80x9(device_t, int, int); 201#ifdef ED_3C503 202int ed_probe_3Com(device_t, int, int); 203#endif 204#ifdef ED_SIC 205int ed_probe_SIC(device_t, int, int); 206#endif 207int ed_probe_Novell_generic(device_t, int); 208int ed_probe_Novell(device_t, int, int); 209void ed_Novell_read_mac(struct ed_softc *); 210#ifdef ED_HPP 211int ed_probe_HP_pclanp(device_t, int, int); 212#endif 213 214int ed_attach(device_t); 215int ed_detach(device_t); 216int ed_clear_memory(device_t); 217int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */ 218void ed_stop(struct ed_softc *); 219void ed_shmem_readmem16(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 220void ed_shmem_readmem8(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 221u_short ed_shmem_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t); 222void ed_pio_readmem(struct ed_softc *, bus_size_t, uint8_t *, uint16_t); 223void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t); 224u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, bus_size_t); 225 226void ed_disable_16bit_access(struct ed_softc *); 227void ed_enable_16bit_access(struct ed_softc *); 228 229void ed_gen_ifmedia_init(struct ed_softc *); 230 231driver_intr_t edintr; 232 233extern devclass_t ed_devclass; 234 235 236/* 237 * Vendor types 238 */ 239#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 240#define ED_VENDOR_3COM 0x01 /* 3Com */ 241#define ED_VENDOR_NOVELL 0x02 /* Novell */ 242#define ED_VENDOR_HP 0x03 /* Hewlett Packard */ 243#define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */ 244 245/* 246 * Configure time flags 247 */ 248/* 249 * this sets the default for enabling/disabling the transceiver 250 */ 251#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 252 253/* 254 * This forces the board to be used in 8/16bit mode even if it 255 * autoconfigs differently 256 */ 257#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 258#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 259 260/* 261 * This disables the use of double transmit buffers. 262 */ 263#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 264 265/* 266 * This forces all operations with the NIC memory to use Programmed 267 * I/O (i.e. not via shared memory) 268 */ 269#define ED_FLAGS_FORCE_PIO 0x0010 270 271/* 272 * This forces a PC Card, and disables ISA memory range checks 273 */ 274#define ED_FLAGS_PCCARD 0x0020 275 276/* 277 * These are flags describing the chip type. 278 */ 279#define ED_FLAGS_TOSH_ETHER 0x10000 280#define ED_FLAGS_GWETHER 0x20000 281 282#define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000) 283 284#define ED_MUTEX(_sc) (&(_sc)->sc_mtx) 285#define ED_LOCK(_sc) mtx_lock(ED_MUTEX(_sc)) 286#define ED_UNLOCK(_sc) mtx_unlock(ED_MUTEX(_sc)) 287#define ED_LOCK_INIT(_sc) \ 288 mtx_init(ED_MUTEX(_sc), device_get_nameunit(_sc->dev), \ 289 MTX_NETWORK_LOCK, MTX_DEF) 290#define ED_LOCK_DESTROY(_sc) mtx_destroy(ED_MUTEX(_sc)); 291#define ED_ASSERT_LOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_OWNED); 292#define ED_ASSERT_UNLOCKED(_sc) mtx_assert(ED_MUTEX(_sc), MA_NOTOWNED); 293 294#endif /* SYS_DEV_ED_IF_EDVAR_H */ 295